CN102147780A - Link interface circuit based on serial data transmission mode - Google Patents
Link interface circuit based on serial data transmission mode Download PDFInfo
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Abstract
The invention discloses a link interface circuit based on a serial data transmission mode. The link interface circuit comprises an interface circuit at the link transmitting end of a processor kernel, an interface circuit at the link receiving end of the processor kernel, an 8-bit data wire and three control wires which are linked between link ports of the link transmitting end and the link receiving end, a link port associated clock generator for generating a link transmission associated clock, a link port direct memory access (DMA) control register for setting a control signal required by link DAM transmission, a link port DMA controller for generating a time sequence required by a link transmission protocol and accessing an address of an internal memory, a link port pingpang buffer register for storing data needed to be subjected to parallel-to-serial conversion transmission and data needed to be subjected to serial-to-parallel conversion receiving during link transmission, and a parallel-to-serial conversion circuit for outputting serial data of eight channels at the same time; and the link port adopts a transmission protocol that the transmitting end transmits parameters to the receiving end so as to realize link transmission of interfaces between two digital signal processors (DSP).
Description
Technical field
The present invention relates to a kind of link interface circuit, be used for two high speed serialization LVDS data transmission between the DSP based on the serial data transmission mode.
Background technology
In the system that multiprocessor is formed, carry out data transmission manner between the processor and generally realize by all kinds of buses or point-to-point transmission mode.Based on the data transmission architecture of bus because a plurality of processors sharing buses need be carried out bus arbitration between each processor.Bus arbitration is unfavorable for the application scenario of processing in real time, because after application program is submitted the bus application to, the mandate that must wait bus arbitration mechanism just can take bus afterwards and carry out data transmission, and the time application programs that this section waits is difficult to predict.
Different with bus transmission model, the transmission of point-to-point transmission mode is initiated to be controlled by application program fully opportunity, therefore the time application programs of transmission can be predicted fully, application program just can made accurate budget aspect the arrangement of time between exchanges data and the data processing like this, meets the application demand of real-time processing.The point-to-point transmission mode is used in real-time processing domain to some extent, for example just used the point-to-point transmission mode in the bullhead shark series processors of ADI company, but the host-host protocol of the said firm regulation, must identical transmission mode, transmission length parameter be set in transmitting terminal and receiving end correspondence, need transmitting terminal and receiving end to do identical setting, this set is appointed in advance, can not change in real time.
Summary of the invention
The object of the present invention is to provide a kind of receiving end parameter configuration, transmitting terminal can simplified to change transmission parameter in real time, make transmission more flexibly based on the link interface circuit of serial data transmission mode.
Its technical scheme is: a kind of link interface circuit based on the serial data transmission mode, the interface circuit that comprises processor cores Link transmitting terminal, the interface circuit of processor cores Link receiving end, and be linked at 8 position datawires and three control lines between Link transmitting terminal and the Link receiving end link port;
The interface circuit of described processor cores Link transmitting terminal has:
DMA transmits control register, is used to be provided with the control signal of link DMA transmission needs;
According to be provided with control word can according to 2,4,6,8 different frequency division cycles of system's major clock produce with the road clock generator;
Can produce the transmitting terminal on-chip memory and read the address according to the control word content is set, and also produce the transmitting terminal dma controller of the transfer request signal in the Link oral instructions transmission protocol simultaneously;
The transmission ping-pong buffers device of 2*8*32bit is used for the DMA metadata cache;
8 the parallel parallel-to-serial converters that can support 16bit or 32bit bit wide are used for exporting simultaneously the serial data of 8 passages;
The interface circuit of described processor cores Link receiving end has:
DMA receives control register, is used for the control signal that configuration link DMA receives needs;
Can produce receiving end on-chip memory write address according to the control word content, also produce the receiving end dma controller of the transmission answer signal in the Link oral instructions transmission protocol simultaneously;
The reception ping-pong buffers device of 2*8*32bit is used for the DMA metadata cache;
8 the parallel serial-parallel conversion circuits that can support 16bit or 32bit bit wide are used for receiving simultaneously the serial data of 8 passages;
Described link port adopts transmitting terminal to the host-host protocol that receiving end passes a parameter, and is used for realizing between two digital signal processors the link transmission based on the LVDS interface.
Above-mentioned link port is a bidirectional interface independently, can receive data from the other side when sending.
Above-mentioned link port is all carried out data transmission with the rising edge and the negative edge of road clock.
Above-mentioned host-host protocol is:
First step judges that transmitting terminal DMA transmits whether effectively start;
Second step produces frequency division with road clock TR_CLK according to default corresponding control word value;
Third step if effectively start according to the receiving end ack signal, judges whether to be ready to set up link transmission, satisfies the transmission requests enabling signal IRQ that then produces sign indicating number shape " 110011 " as condition, begins to set up link transmission one time;
The 4th step, transmitting terminal by and go here and there ALT-CH alternate channel 02 32bit control words passed to receiving end;
The 5th step, the transmitting terminal dma controller produces on-chip memory continuously and reads the address, the row address bus arbitration of going forward side by side;
The 6th step, if obtain the read bus control, just data are written in the transmission ping-pong buffer in the storer that this address is read, and continuation calculating next address, if invalid, wait for that then arbitration continues the calculation of next address ground after effective again;
The 7th step, the table tennis buffer memory in the ping-pong buffer write full after, begin to carry out and go here and there conversion, data serial is sent to receiving end, switch getting in touch of internal memory and ping-pong buffer simultaneously, will write pang the buffer memory from the on-chip memory reading of data;
The 8th step, receiving end receive serial data and go here and there and conversion work, the parallel data after the conversion are deposited in receive in the table tennis buffer memory;
The 9th step, receiving end start dma controller, produce the on-chip memory write address row address bus arbitration of going forward side by side continuously;
The tenth step, if obtain the write bus control, to receive then that data are written in the corresponding on-chip memory in the buffer memory, and next address is calculated in continuation, if it is invalid, then continue next address ground again after the wait arbitration effectively and calculate, after will ping data cachedly reading sky, switch to pang buffer memory and continue to wait for number;
In the 11 step, the receiving end dma controller judges whether to continue to respond the transmission requests of transmit port and send the ACK answer signal simultaneously;
The 12 step, the ack signal effective (' 1 ') full when transmitting terminal pang buffer memory and receiving end responds, then continue above-mentioned steps, with process of the data in transmitting terminal pang the buffer memory and string---string and conversion are transferred to receiving end pang buffer memory, repetitive operation reaches the DMA transmission length that the programmer sets until the address counting step, end-of-job is failed in the Link oral instructions, provides to send end mark and receive end mark.
Its technique effect is: the present invention adopts point-to-point data transfer mode, and in host-host protocol, adopt by the transmitting terminal of data and initiate transmission, and transmission mode, transmission length parameter send receiving end to by transmitting terminal, receiving end is the control register that disposes receiving end automatically after receiving parameter, and the application program of receiving end is simplified aspect parameter configuration; Simultaneously, when each transmission begins, transmitting terminal sends transmission mode, transmission length information to receiving end, transmitting terminal just can be each different pattern and length parameters of transmission configuration like this, reach the effect of real-time change transmission mode and transmission length, make data transmission more flexible, thereby effectively solved the data transmission problems of real-time processing application scenario, for the inside of dsp processor or outside data transmission provide one fast, communication mechanism independently, this interface circuit also can use the I/O equipment of same protocol to be connected communication with other.
Description of drawings
Fig. 1 is a structured flowchart of the present invention.
Fig. 2 is the interface circuit structural drawing of processor cores Link transmitting terminal.
Fig. 3 is the parallel-to-serial converter structural drawing of transmitting terminal.
Fig. 4 is the interface circuit structural drawing of processor cores Link receiving end.
Fig. 5 is the serial-parallel conversion circuit structural drawing of receiving end.
Fig. 6 is the TR_CLK signal, the timing waveform between irq signal and the ack signal.
Embodiment
As shown in Figure 1, link interface circuit based on the serial data transmission mode, the interface circuit that comprises processor cores Link transmitting terminal, the interface circuit of processor cores Link receiving end, and be linked at 8 position datawire LINK_DATA[7:0 between Link transmitting terminal and the Link receiving end link port] and three control line TR_CLK, IRQ, ACK.TR_CLK wherein, IRQ and LINK_DATA[7:0] be to export to Link mouth receiving end by Link mouth transmitting terminal, ack signal then is to feed back to Link mouth transmitting terminal by Link mouth receiving end.
The interface circuit (see figure 2) of processor cores Link transmitting terminal has: DMA transmits control register, with the road clock generator, and dma controller, the table tennis metadata cache of one group of 2*8*32bit and 8 parallel-to-serial converters, carry-out bit 8*1bit serial data.Each dma controller need carry out proper configuration to corresponding DMA control register according to the programmer could log-on data transmission work.The decision of data transmission length needs data quantity transmitted in a data transmission procedure.
The DMA metadata cache is the 16*32bit data register of one group of ping-pong structure, when one group of data register carries out data transmission, another group data register receives the data that send from the memory read bus, when DTD, whether the data register of checking another group of received receives, when the ready while of data register, check whether Link mouth receiving end is ready to, in case it is all ready, then the table tennis exchange takes place in the internal data buffer memory, and next group data transmission just begins to carry out.
In step 1, the DMA starting impulse is determined that by instruction in case the DMA enabling signal is sent in instruction, then execution in step two, produces frequency division with road clock TR_CLK according to default corresponding control word value.Execution in step three simultaneously, DMA transmitting terminal controller checks whether Link mouth receiving end is ready to, and Link mouth receiving end DMA is at electrification reset or to keep receiving response signal ACK after the DMA end of transmission (EOT) last time be high level, and expression stops DMA and receives work.When correct configuration Link mouth receiving end DMA control register and put receive the transmission enable bit effectively after, receiving response signal ACK drags down, expression is ready for DMA and is received work, make a start and send the DMA transmission request signal of yard shape continuously for " 110011 " by transfer request signal IRQ, and execution in step four subsequently, send two 32bit control words continuously and give receiving end.This moment, IRQ kept low level.Receiving end detects the laggard line control word of this IRQ sign indicating number shape signal and receives preparation, and 2 32bit control word step-by-steps difference assignment will receiving are subsequently drawn high ack signal expression afterwards and can be received normal data to receiving the pairing control bit of control register.In step 5, transmitting terminal is drawn high irq signal after sending control word, simultaneously the source start address being delivered to the read bus arbitration circuit arbitrates, in case obtain bus control right, execution in step six, 32bit data (Ram_data) are written in the corresponding transmission table tennis buffer memory in the storer that this address is visited, add step value with start address then and calculate the address value (raddr) that makes new advances, and repetition aforesaid operations, fill up and provide buffer memory full scale will (reg_full) until the transmission table tennis buffer memory that with the degree of depth is 8, switch to subsequently and send pang buffer memory, continue calculated address and fill up until 8 registers that will send pang buffer memory.In step 7, when transmitting terminal table tennis buffer memory is write full and is exchanged ripple signal (Tr_reg_switch) sensing pang buffer memory, irq signal is dragged down, sending in the table tennis buffer memory 8 32bit data (corresponding 8 serial LVDS passages) begins to carry out and go here and there conversion and transmission work, receiving end execution in step eight, begin to receive serial data and go here and there and conversion work, and the 32bit parallel data after will change deposits in and receives ping in the buffer memory.All also goes here and there---and string and conversion, transmission and reception work are all synchronous in strict accordance with the negative edge of irq signal.When once and go here and there conversion work when finishing, provide an end of transmission (EOT) sign, whether detect transmitting terminal buffer memory full scale will and ack signal simultaneously all is high level, in this way, represent that then 8 32bit data of next group are ready to (pang buffer memory is write full) and the buffer memory of receiving end also is ready to (pang buffer memory is for empty), can continue to receive data, this moment, the buffer memory exchange ripple signal of transmitting terminal overturn, irq signal is kept low level, continues and string conversion and data transmission work.If this moment, transmitting terminal buffer memory full scale will or ack signal had one to be low level, then stop data and string conversion and transmission work, and irq signal is drawn high, transmitting terminal buffer memory exchange ripple signal remains unchanged; When transmitting terminal buffer memory full scale will and ack signal all are ' 1 ', irq signal is dragged down once more the buffer memory exchange ripple signal of the transmitting terminal that overturns simultaneously.When upset takes place in transmitting terminal buffer memory exchange ripple signal, transmitting terminal buffer memory full scale will zero clearing (dragging down) can be continued to read the address counting simultaneously, the negative edge of irq signal then can start the conversion of also string and transmission work of next data.Repetitive operation reaches the DMA transmission length that the programmer sets until the address counting step, and the Link mouth sends end-of-job and provides the transmission end mark.
The serial data transmission word is wide to be 32bit, these data are all transmitted according to serial data mode, for whether check data exists mistake in the middle of transmission course, each data can increase by a bit parity check code, promptly increases by a bit parity check position on the basis of original data bits.If the result of receiving end string and conversion back data parity check is ' 1 ', show that then mistake appears in data in transmission course.
The working method of parallel-to-serial converter (see figure 3) is: at first the 32bit data (or not enough 32bit) with metadata cache output resolve into two 16bit data (or not enough 16bit) by parity bit, two data after the decomposition begin simultaneously and go here and there conversion work, the first low level rear high-lying of conversion output, utilizing serial clock TR_CLK to carry out parity bit data output at the conversion output terminal selects, TR_CLK selects even number section serial output data during for high level, select odd number section output data when low, so just be equal to the rising edge that utilizes TR_CLK and negative edge all carries out data and string is changed and output services.As being 250MHz with the road clock, then the serial ports transfer rate can reach 500MHz.
The interface circuit (see figure 4) of processor cores Link receiving end has: DMA receives control register, receiving end dma controller, the table tennis metadata cache of one group of 2*8*32bit and 8 serial-parallel conversion circuits.Receiving dma controller needs the programmer that corresponding DMA control register is carried out the correct correctly log-on data reception work that is provided with.
The DRP data reception process of Link receiving end is: 8 tunnel serial datas that receive are gone here and there earlier and are converted into 8 road 32bit parallel datas, data after string and the conversion are deposited in the ping-pong buffer of a 2*8*32bit, the serial received port starts dma controller then, and be written in the corresponding memory data cached according to the on-chip memory sequence of addresses that DMA calculates, judge whether simultaneously to continue to respond the transmission requests of transmit port and send the ACK answer signal.Concrete sequential relationship is described below: it is low level that Link mouth receiving end DMA keeps receiving response signal ACK after the programmer correctly is provided with control register, expression is ready to DMA and receives work, if this moment, transmitting terminal started the DMA transmission, to receive the DMA transmission request signal IRQ of yard shape for " 110011 ", receiving end detects the laggard line control word of this irq signal and receives preparation, and 2 32bit control word assignment will receiving are subsequently given the receiving end control register.Transmitting terminal is drawn high irq signal after sending control word, in the time of transmitting terminal table tennis buffer memory ready (writing full) the formal transmission of beginning data, irq signal can be dragged down, 8 32bit data in the table tennis buffer memory of transmitting terminal (corresponding 8 serial LVDS passages) begin to carry out and go here and theres conversion and transmission work, receiving end enters step 8 at this moment, begin to receive serial data and go here and there and conversion work, the 32bit parallel data after will change simultaneously deposits receiving end in ping in the buffer memory.All also goes here and there---and string and conversion, transmission and reception work are all synchronous in strict accordance with the negative edge of irq signal.After receiving end table tennis buffer memory is finished and deposited in to a Data Receiving, upset takes place and points to receiving end pang buffer memory in receiving end buffer memory exchange ripple signal (Rx_reg_switch), sense data from write full table tennis buffer memory simultaneously, carry out the step 9 operation, this moment, the receiving end dma controller began to produce data-carrier store write address (waddr) in the sheet, the address is delivered to the write bus arbitration circuit and is arbitrated, in case obtain bus control right, implementation step ten, the 32bi data that the access of postponing is gone out are written in the on-chip memory appropriate address space of visiting this address, add step value with start address then and calculate the address value that makes new advances, and repetition aforesaid operations, after the reception table tennis cache read sky that with the degree of depth is 8 also all was written to on-chip memory, providing and receiving the empty sign of buffer memory (reg_empty) was height.In step 11, once go here and there and change when receiving end-of-job, providing a reception end mark is ' 1 ', detects simultaneously whether the empty sign of receiving end buffer memory is high level, in this way, then expression reception pang buffer memory is ready to, can continue to receive data, ack signal is kept high level, the buffer memory exchange ripple signal generation once inside out of receiving end, begin the reception work of next data, simultaneously with the zero clearing of the empty sign of receiving end buffer memory.If the empty marking signal of receiving end buffer memory this moment is a low level, represent the data cached sky of not reading as yet of another group, can not continue to receive data, drag down ack signal this moment, and it is constant to keep receiving end buffer memory exchange ripple level, and transmitting terminal stops data transmission work, be masked as when high up to receiving end buffer memory sky, again ack signal is put height, receiving end buffer memory exchange ripple signal overturns, and starts string and the conversion and the reception work of next group data.Repetitive operation then stops Data Receiving work until transmitting terminal request signal IRQ perseverance for height, then works as DMA write address counting step and reaches the DMA transmission length that prior control word sets, and Link mouth reception work finishes fully, provides the reception end mark.
Each Link receiving port is made of 8 LVDS data channel, and with serial mode input 1bit data, 8 passages are receiving the 8bit data in the beat to these 8 passages at the same time simultaneously respectively.Receive the work that will go here and there and change after the serial data, each passage has a serial-parallel conversion circuit (see figure 5), and the parallel data that the serial data that is about to a string 1bit is transformed into a 32bit deposits buffer memory in.Data transfer mode is first low level rear high-lying.String and switching rate are by determining with road clock TR_CLK that transmitting terminal provides.The serial data that receives is being done string and during conversion work, and parity checking in the control word that need send in advance according to transmitting terminal, data word be wide, information such as signed number is determined to operate accordingly.Its working method is: at first the 1bit serial data of input is utilized the rising edge of clock TR_CLK to squeeze in the different moment with negative edge in (string and conversion) two 16bit registers respectively, be respectively the required parity bit that obtains data.(rising edge is adopted odd data and is done string and conversion, and negative edge is adopted even data and done string and conversion.) according to the transmission data word wide be set in receive once complete serial data after, the parity bit parallel data is merged into a complete 32bit parallel data, carry out parity checking simultaneously.Afterwards data are deposited in the ping-pong buffer.
TR_CLK signal in the present embodiment, the sequential relationship between irq signal and the ack signal is seen Fig. 6.
Claims (4)
1. link interface circuit based on the serial data transmission mode, the interface circuit that comprises processor cores Link transmitting terminal, the interface circuit of processor cores Link receiving end, and be linked at 8 position datawires and three control lines between Link transmitting terminal and the Link receiving end link port; It is characterized in that:
The interface circuit of described processor cores Link transmitting terminal has:
DMA transmits control register, is used to be provided with the control signal of link DMA transmission needs;
According to be provided with control word can according to 2,4,6,8 different frequency division cycles of system's major clock produce with the road clock generator;
Can produce the transmitting terminal on-chip memory and read the address according to the control word content is set, and also produce the transmitting terminal dma controller of the transfer request signal in the Link oral instructions transmission protocol simultaneously;
The transmission ping-pong buffers device of 2*8*32bit is used for the DMA metadata cache;
8 the parallel parallel-to-serial converters that can support 16bit or 32bit bit wide are used for exporting simultaneously the serial data of 8 passages;
The interface circuit of described processor cores Link receiving end has:
DMA receives control register, is used for the control signal that configuration link DMA receives needs;
Can produce receiving end on-chip memory write address according to the control word content, also produce the receiving end dma controller of the transmission answer signal in the Link oral instructions transmission protocol simultaneously;
The reception ping-pong buffers device of 2*8*32bit is used for the DMA metadata cache;
8 the parallel serial-parallel conversion circuits that can support 16bit or 32bit bit wide are used for receiving simultaneously the serial data of 8 passages;
Described link port adopts transmitting terminal to the host-host protocol that receiving end passes a parameter, and is used for realizing between two digital signal processors the link transmission based on the LVDS interface.
2. a kind of link interface circuit based on the serial data transmission mode according to claim 1 is characterized in that: described link port is a bidirectional interface independently, can receive data from the other side when sending.
3. a kind of link interface circuit based on the serial data transmission mode according to claim 1 is characterized in that: described link port is all carried out data transmission with the rising edge and the negative edge of road clock.
4. a kind of link interface circuit according to claim 1 based on the serial data transmission mode, it is characterized in that: described host-host protocol is:
First step judges that transmitting terminal DMA transmits whether effectively start;
Second step produces frequency division with road clock TR_CLK according to default corresponding control word value;
Third step if effectively start according to the receiving end ack signal, judges whether to be ready to set up link transmission, satisfies the transmission requests enabling signal IRQ that then produces sign indicating number shape " 110011 " as condition, begins to set up link transmission one time;
The 4th step, transmitting terminal by and go here and there ALT-CH alternate channel 02 32bit control words passed to receiving end;
The 5th step, the transmitting terminal dma controller produces on-chip memory continuously and reads the address, the row address bus arbitration of going forward side by side;
The 6th step, if obtain the read bus control, just data are written in the transmission ping-pong buffer in the storer that this address is read, and continuation calculating next address, if invalid, wait for that then arbitration continues the calculation of next address ground after effective again;
The 7th step, the table tennis buffer memory in the ping-pong buffer write full after, begin to carry out and go here and there conversion, data serial is sent to receiving end, switch getting in touch of internal memory and ping-pong buffer simultaneously, will write pang the buffer memory from the on-chip memory reading of data;
The 8th step, receiving end receive serial data and go here and there and conversion work, the parallel data after the conversion are deposited in receive in the table tennis buffer memory;
The 9th step, receiving end start dma controller, produce the on-chip memory write address row address bus arbitration of going forward side by side continuously;
The tenth step, if obtain the write bus control, to receive then that data are written in the corresponding on-chip memory in the buffer memory, and next address is calculated in continuation, if it is invalid, then continue next address ground again after the wait arbitration effectively and calculate, after will ping data cachedly reading sky, switch to pang buffer memory and continue to wait for number;
In the 11 step, the receiving end dma controller judges whether to continue to respond the transmission requests of transmit port and send the ACK answer signal simultaneously;
The 12 step, the ack signal effective (' 1 ') full when transmitting terminal pang buffer memory and receiving end responds, then continue above-mentioned steps, with process of the data in transmitting terminal pang the buffer memory and string---string and conversion are transferred to receiving end pang buffer memory, repetitive operation reaches the DMA transmission length that the programmer sets until the address counting step, end-of-job is failed in the Link oral instructions, provides to send end mark and receive end mark.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103034610A (en) * | 2011-10-09 | 2013-04-10 | 中兴通讯股份有限公司 | Methods and devices for transmission and reception of advanced extensible interface (AXI) bus signal between split modules |
| CN107741920A (en) * | 2017-10-13 | 2018-02-27 | 肇庆市立泰电子产品有限公司 | A kind of slide cam selector Data Transport Protocol simplified |
| CN109062847A (en) * | 2018-07-31 | 2018-12-21 | 深圳职业技术学院 | System on chip, IP kernel and its control method for RS485 serial communication |
| CN110442543A (en) * | 2019-08-09 | 2019-11-12 | 瓴盛科技有限公司 | Communication device and communication means |
| CN111200581A (en) * | 2018-11-19 | 2020-05-26 | 北京华航无线电测量研究所 | Data receiving and transmitting module based on LVDS bus |
| CN111475447A (en) * | 2019-01-24 | 2020-07-31 | 广州彩熠灯光股份有限公司 | L VDS-based high-speed serial transmission device and method thereof |
| CN113094310A (en) * | 2019-12-23 | 2021-07-09 | 华为技术有限公司 | Memory manager, processor memory subsystem, processor and electronic equipment |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050188129A1 (en) * | 2004-02-20 | 2005-08-25 | International Business Machines Corporation | Facilitating inter-DSP data communications |
| CN202025311U (en) * | 2011-04-27 | 2011-11-02 | 中国电子科技集团公司第三十八研究所 | Link interface circuit based on serial data transmission mode |
-
2011
- 2011-04-27 CN CN 201110106644 patent/CN102147780B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050188129A1 (en) * | 2004-02-20 | 2005-08-25 | International Business Machines Corporation | Facilitating inter-DSP data communications |
| CN202025311U (en) * | 2011-04-27 | 2011-11-02 | 中国电子科技集团公司第三十八研究所 | Link interface circuit based on serial data transmission mode |
Non-Patent Citations (2)
| Title |
|---|
| 《ADSP SHARC系列DSP应用系统设计》 20030228 刘书明，罗军辉 3.5 ADSP SHARC系列处理器链路口的应用 电子工业出版社 136-165 , * |
| 《ADSP-TS201 TigerSHARC Processor Hardware Reference》 20041231 ANALOG DEVICES DIRECT MEMORY ACCESS 7-8-7-70 , * |
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| CN103034610A (en) * | 2011-10-09 | 2013-04-10 | 中兴通讯股份有限公司 | Methods and devices for transmission and reception of advanced extensible interface (AXI) bus signal between split modules |
| CN107741920A (en) * | 2017-10-13 | 2018-02-27 | 肇庆市立泰电子产品有限公司 | A kind of slide cam selector Data Transport Protocol simplified |
| CN107741920B (en) * | 2017-10-13 | 2020-09-29 | 肇庆市立泰电子产品有限公司 | Simplified data transmission method for needle selector |
| CN109062847A (en) * | 2018-07-31 | 2018-12-21 | 深圳职业技术学院 | System on chip, IP kernel and its control method for RS485 serial communication |
| CN109062847B (en) * | 2018-07-31 | 2023-08-25 | 深圳职业技术学院 | System on chip, IP core for RS485 serial port communication and control method thereof |
| CN111200581A (en) * | 2018-11-19 | 2020-05-26 | 北京华航无线电测量研究所 | Data receiving and transmitting module based on LVDS bus |
| CN111200581B (en) * | 2018-11-19 | 2022-08-16 | 北京华航无线电测量研究所 | Data receiving and transmitting module based on LVDS bus |
| CN111475447A (en) * | 2019-01-24 | 2020-07-31 | 广州彩熠灯光股份有限公司 | L VDS-based high-speed serial transmission device and method thereof |
| CN111475447B (en) * | 2019-01-24 | 2021-10-22 | 广州彩熠灯光股份有限公司 | High-speed serial transmission device based on LVDS and data transmission method |
| CN110442543A (en) * | 2019-08-09 | 2019-11-12 | 瓴盛科技有限公司 | Communication device and communication means |
| CN110442543B (en) * | 2019-08-09 | 2023-09-08 | 瓴盛科技有限公司 | Communication device and communication method |
| CN113094310A (en) * | 2019-12-23 | 2021-07-09 | 华为技术有限公司 | Memory manager, processor memory subsystem, processor and electronic equipment |
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| CN102147780B (en) | 2013-04-17 |
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