TWI411074B - Fine-pitch matrix connectors - Google Patents

Fine-pitch matrix connectors Download PDF

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TWI411074B
TWI411074B TW98145021A TW98145021A TWI411074B TW I411074 B TWI411074 B TW I411074B TW 98145021 A TW98145021 A TW 98145021A TW 98145021 A TW98145021 A TW 98145021A TW I411074 B TWI411074 B TW I411074B
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layer
connector
cantilever
connector structure
structures
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TW98145021A
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TW201123382A (en
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Ben Hwa Jang
Shin Way Lin
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Ind Tech Res Inst
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Abstract

Fine-pitch matrix connectors that are fabricated through micromechanical technology have self-detecting mechanism for co-planarity and normal force. The matrix connectors can provide low and stable contact resistance under small normal force, which improves the transmission quality of electrical signals.

Description

細間距陣列型連接器Fine pitch array type connector

本發明是有關於一種陣列式連接器,且特別是有關於一種細間距陣列式連接器。This invention relates to an array connector and, more particularly, to a fine pitch array connector.

一般陣列式連接器受模具與製程等相關限制,最小端子間距只能達到0.8mm,更由於陣列式連接器之塑膠本體,於塑膠射出時易產生翹曲的現象,隨著陣列式連接器腳位增加,將不易控制各腳位間之共面度。另隨著BGA晶片對外IO連接腳位增多且間距變小,導致以傳統光學量測晶片錫球的共面度更加不易。Generally, the array connector is limited by the mold and the process, and the minimum terminal spacing can only reach 0.8mm. Moreover, due to the plastic body of the array connector, the phenomenon of warpage is easily generated when the plastic is shot, with the array connector foot. As the bit increases, it will be difficult to control the coplanarity between the feet. In addition, as the BGA chip increases the external IO connection pin and the pitch becomes smaller, it is more difficult to measure the coplanarity of the wafer solder ball by conventional optical measurement.

除此之外,隨著連接器細間距化的發展,單根端子所能提供的正向力亦會降低,造成過大的接觸電阻,大大地影響訊號的傳遞品質。In addition, with the development of the fine pitch of the connector, the positive force that the single terminal can provide will also be reduced, resulting in excessive contact resistance, which greatly affects the transmission quality of the signal.

在實際的應用上,若能改善陣列式連接器之本體結構,使得微小化之陣列式連接器在較低的正向力作用下,亦能保持低且穩定之接觸電阻,將可提昇陣列式連接器電氣連接特性。除此之外,若能利用陣列式連接器同時量測晶片錫球的共面度,更可大幅增加其產業利用價值。In practical applications, if the body structure of the array connector can be improved, the miniaturized array connector can maintain a low and stable contact resistance under a low positive force, which can enhance the array type. Connector electrical connection characteristics. In addition, if the array connector is used to simultaneously measure the coplanarity of the wafer solder balls, the industrial utilization value can be greatly increased.

本發明提供一種具自我共面度與正向力檢測機制之細間距陣列型連接器。該陣列型連接器利用奈米碳管之良好的機械與導電特性,將可在低正向力作用下,提供接觸面小而穩定的接觸電阻。The invention provides a fine pitch array type connector with self-coplanarity and positive force detection mechanism. The array type connector utilizes the good mechanical and electrical properties of the carbon nanotubes to provide a small and stable contact resistance under low positive force.

本發明提供一種具自我共面度之細間距陣列型連接器,由於連接器本體乃由矽晶圓所製造,因此可提供較強韌的本體結構剛性,不會造成本體翹曲的行為,影響連接器使用時的可靠度。The invention provides a fine pitch array type connector with self-coplanarity. Since the connector body is manufactured by a silicon wafer, it can provide a strong tough structural rigidity of the body without causing the behavior of the body warping, affecting Reliability when using the connector.

本發明提供一種細間距陣列型連接器陣列型,透過微機電製程方式,製作具奈米碳管結構之低且穩定接觸電阻陣列型連接器。The invention provides a fine pitch array type connector array type, which is capable of fabricating a low and stable contact resistance array type connector having a carbon nanotube structure through a microelectromechanical process.

本發明提出一種連接器結構,包括環狀體結構與位於該環狀體結構中央之柱狀結構、位於該環狀體結構上多個第一塊狀結構、位於該柱狀結構上之第二塊狀結構、至少一懸臂結構、位於該些第一塊狀結構上多個銲料凸塊,以及位於該第二塊狀結構上之奈米碳管層。其中,該懸臂結構與該第二塊狀結構與至少一個該第一塊狀結構相連,而該懸臂結構與該第一塊狀結構相連處更包括一壓電材料層或一壓阻材料層,透過此一壓電材料層或壓阻材料層,可感測懸臂結構位移,進而量測晶片錫球的共面度。The present invention provides a connector structure including an annular body structure and a columnar structure located at the center of the annular body structure, a plurality of first block structures on the annular body structure, and a second structure on the columnar structure. a block structure, at least one cantilever structure, a plurality of solder bumps on the first block structures, and a carbon nanotube layer on the second block structure. Wherein the cantilever structure is connected to the second block structure and the at least one first block structure, and the cantilever structure and the first block structure further comprise a piezoelectric material layer or a piezoresistive material layer. Through the piezoelectric material layer or the piezoresistive material layer, the displacement of the cantilever structure can be sensed, and the coplanarity of the wafer solder ball can be measured.

依照本發明的一較佳實施例所述,在上述之連接器結構中該環狀體結構與該柱狀結構為疊層結構,包括位於半導體基底之上表面之氧化矽層。In accordance with a preferred embodiment of the present invention, in the connector structure described above, the annular body structure and the columnar structure are laminated structures including a ruthenium oxide layer on a surface of the semiconductor substrate.

依照本發明的一較佳實施例所述,在上述之連接器結構中該第一、第二塊狀結構以及該懸臂結構為疊層結構,包括一多晶矽層、位於該多晶矽層上之一種子層與位於該種子層上之一金屬層。According to a preferred embodiment of the present invention, in the connector structure, the first and second block structures and the cantilever structure are a laminated structure including a polysilicon layer and a seed on the polysilicon layer. A layer and a metal layer on the seed layer.

依照本發明的一較佳實施例所述,在上述之連接器結構中之壓電材料層位於該多晶矽層與該種子層之間。In accordance with a preferred embodiment of the present invention, a layer of piezoelectric material in the connector structure is located between the polysilicon layer and the seed layer.

依照本發明的一較佳實施例所述,在上述之連接器結構中之壓阻材料層為一摻雜區位於該多晶矽層之中。In accordance with a preferred embodiment of the present invention, the layer of piezoresistive material in the connector structure is a doped region located in the polysilicon layer.

依照本發明的較佳實施例所述,上述之連接器結構中,該壓電材料層之材質包括氧化鋅。According to a preferred embodiment of the present invention, in the connector structure, the material of the piezoelectric material layer comprises zinc oxide.

依照本發明的較佳實施例所述,上述之連接器結構中,該壓阻材料層之材質包括硼或鍺。According to a preferred embodiment of the present invention, in the connector structure, the material of the piezoresistive material layer comprises boron or germanium.

依照本發明的較佳實施例所述,上述之連接器結構中,該金屬層之材質包括鋁、銅或金。According to a preferred embodiment of the present invention, in the connector structure, the material of the metal layer comprises aluminum, copper or gold.

依照本發明的較佳實施例所述,上述之連接器結構中,該種子層之材質包括鈦、金或鉻。According to a preferred embodiment of the present invention, in the connector structure, the material of the seed layer comprises titanium, gold or chromium.

依照本發明的較佳實施例所述,上述之連接器結構中,該銲料凸塊之材質包括錫、錫銀合金或錫鉛合金。According to a preferred embodiment of the present invention, in the connector structure, the material of the solder bump comprises tin, tin-silver alloy or tin-lead alloy.

由於本發明所提出的連接器結構乃設計利用壓電或壓阻感測機制來測量晶片錫球共面度或所受正向力,可提升產品應用的範圍。Since the connector structure proposed by the present invention is designed to measure the coplanarity or positive force of the wafer solder ball by using a piezoelectric or piezoresistive sensing mechanism, the range of application of the product can be improved.

本發明所提供之微連接器結構之接觸面更具備奈米碳管層,可降低接觸電阻。本發明所提供之微連接器結構特別適合設置於細間距(小於500微米)之微接點電氣連接之結構中。The contact surface of the micro connector structure provided by the invention further has a carbon nanotube layer, which can reduce the contact resistance. The micro connector structure provided by the present invention is particularly suitable for use in a fine pitch (less than 500 micron) microcontact electrical connection structure.

此外,本發明之連接器結構的製造方法可輕易整合至現行的微機電製程中進行,因此不會增加額外的成本。In addition, the method of fabricating the connector structure of the present invention can be easily integrated into current MEMS processes, thereby not adding additional cost.

為讓本發明之上述和其他目的、特徵和優點能更明顯易懂,下文特舉較佳實施例,並配合所附圖式,作詳細說明如下。The above and other objects, features and advantages of the present invention will become more <RTIgt;

圖1A-1B&圖1F-1H所繪示為本發明一實施例之陣列式連接器的製造流程剖面圖,而圖1C-1E所繪示為本發明一實施例之陣列式連接器的製造流程上視圖。1A-1B and FIGS. 1F-1H are cross-sectional views showing a manufacturing process of an array connector according to an embodiment of the present invention, and FIGS. 1C-1E illustrate a manufacturing process of an array connector according to an embodiment of the present invention. Top view.

請參照圖1A,首先提供一基底100,該基底100例如為一半導體矽晶圓或晶片,首先在該基底100之上表面100a上利用例如熱氧化方式成長一氧化矽層102。接著利用例如低壓化學氣相沈積法(LPCVD)於該氧化矽層102上沉積一多晶矽層104。接著並於該多晶矽層104上形成一圖案化之薄膜壓電材料層106。其中壓電材料層106的材質例如是氧化鋅(ZnO)。Referring to FIG. 1A, a substrate 100 is first provided. The substrate 100 is, for example, a semiconductor germanium wafer or wafer. First, the germanium oxide layer 102 is grown on the upper surface 100a of the substrate 100 by, for example, thermal oxidation. A polysilicon layer 104 is then deposited over the yttrium oxide layer 102 using, for example, low pressure chemical vapor deposition (LPCVD). A patterned thin film piezoelectric material layer 106 is then formed on the polysilicon layer 104. The material of the piezoelectric material layer 106 is, for example, zinc oxide (ZnO).

參照圖1B,利用例如電子槍真空蒸鍍方式於該基底100之上表面100a與下表面100b之上分別蒸鍍一種子層108a與108b。該種子層材料例如是鉻/金(Cr/Au)或鈦/金(Ti/Au)。接著,在該種子層108a/108b上進行後續電鍍製程,分別於基底100正、反面電鍍形成一金屬層110a/110b。該金屬層110a/110b材料例如為鋁、銅或金。Referring to FIG. 1B, a sub-layer 108a and 108b are respectively deposited on the upper surface 100a and the lower surface 100b of the substrate 100 by, for example, electron gun vacuum evaporation. The seed layer material is, for example, chromium/gold (Cr/Au) or titanium/gold (Ti/Au). Next, a subsequent electroplating process is performed on the seed layer 108a/108b, and a metal layer 110a/110b is formed on the front and back sides of the substrate 100, respectively. The metal layer 110a/110b material is, for example, aluminum, copper or gold.

參照圖1C,利用微影蝕刻步驟,圖案化基底100正面之金屬層110a(圖1B),以形成接觸墊110c與導線110d。Referring to FIG. 1C, a metal layer 110a (FIG. 1B) on the front side of the substrate 100 is patterned by a lithography etching step to form a contact pad 110c and a wire 110d.

參照圖1D,利用微影蝕刻步驟定義出焊錫的圖形,接著進行電鍍製程形成銲料凸塊120。在形成銲料凸塊120之前,更可包括先形成另一種層112(圖1F),再電鍍形成銲料凸塊120。銲料凸塊120可提供間隔高度,作為間隙物之用。銲料凸塊之材質包括錫、錫銀合金或錫鉛合金。但是,若後續所形成銲料凸塊並不需要種子層,亦可省略此一步驟。Referring to FIG. 1D, a pattern of solder is defined by a lithography etching step, followed by an electroplating process to form solder bumps 120. Before forming the solder bumps 120, it may be further included to form another layer 112 (FIG. 1F) and then plated to form the solder bumps 120. The solder bumps 120 can provide a spacer height for use as a spacer. The material of the solder bumps includes tin, tin-silver alloy or tin-lead alloy. However, if a subsequent formation of the solder bump does not require a seed layer, this step can also be omitted.

參照圖1E,利用微影蝕刻步驟,圖案化基底100正面之該多晶矽層104(圖1B),圖案化的多晶矽層104a(圖1F)之圖案與基底100正面之圖案化金屬層110a相同。此處所示,乃是利用壓電材料層106與金屬層所構成之壓電感測機制,而於後續連接過程中,可達到共面度檢測或正向力檢測之目的。Referring to FIG. 1E, the polysilicon layer 104 (FIG. 1B) on the front side of the substrate 100 is patterned by a lithography etching step, and the pattern of the patterned polysilicon layer 104a (FIG. 1F) is the same as the patterned metal layer 110a on the front side of the substrate 100. As shown here, the piezoelectric sensing mechanism formed by the piezoelectric material layer 106 and the metal layer is utilized, and in the subsequent connection process, the purpose of the coplanarity detection or the positive force detection can be achieved.

圖1E中,圖案化多晶矽層104a之圖案至少包括四根懸臂(後續作為懸浮彈簧結構)與位於中央與四根相連之接觸墊的多晶矽結構。此處懸臂之數目至少大於一個,而其尺寸大小可視連接器之間距尺寸或後續相連接觸墊尺寸而調整;其接觸墊形狀並不侷限於方形,亦可為圓形或多角形。微影蝕刻步驟中例如包括深反應式離子蝕刻步驟來蝕刻圖案化多晶矽層。In FIG. 1E, the pattern of the patterned polysilicon layer 104a includes at least four cantilevers (subsequently as a suspended spring structure) and a polycrystalline germanium structure in the center and four connected contact pads. Here, the number of cantilevers is at least one, and the size thereof can be adjusted according to the size of the connector or the size of the subsequent connected contact pads; the shape of the contact pad is not limited to a square shape, and may be circular or polygonal. The lithography etching step includes, for example, a deep reactive ion etching step to etch the patterned polysilicon layer.

參照圖1F,利用微影蝕刻步驟,圖案化基底100背面之種子層108與金屬層110b而成一硬罩幕層125。Referring to FIG. 1F, the seed layer 108 and the metal layer 110b on the back side of the substrate 100 are patterned into a hard mask layer 125 by a lithography etching step.

參照圖1G,以硬罩幕層125作為蝕刻罩幕,從基底100的背面蝕刻基底100矽基材與氧化矽層102,直至多晶矽層104a暴露出來。該蝕刻步驟例如包括深反應式離子蝕刻步驟。Referring to FIG. 1G, the substrate 100 substrate and the ruthenium oxide layer 102 are etched from the back surface of the substrate 100 with the hard mask layer 125 as an etch mask until the polysilicon layer 104a is exposed. The etching step includes, for example, a deep reactive ion etching step.

請參照圖1H,移除硬罩幕層125,然後利用圖形化光阻(未示),將奈米碳管材料塗佈於金屬層110a之接觸墊110c金屬表面上,並利用外加磁場將奈米碳管材料準直地結合在中央接觸墊110c表面上而成一奈米碳管層130,作為探針頭。之後,再移除多餘之光阻材料。Referring to FIG. 1H, the hard mask layer 125 is removed, and then a carbon nanotube material is coated on the metal surface of the contact pad 110c of the metal layer 110a by using a patterned photoresist (not shown), and the magnetic field is applied by an external magnetic field. The carbon nanotube material is collimatedly bonded to the surface of the center contact pad 110c to form a carbon nanotube layer 130 as a probe head. After that, remove the excess photoresist material.

圖1A-1H僅繪示出單一連接器,以便於解說各層形成相對位置,但可代表製造陣列連接器之普遍性製程。上述各層之形成步驟僅是舉例,但於此技術領域具有普通知識者可輕易推知,該些形成順序與步驟均可視元件設計或製程需要更改。本案並非限定本案之製造方法僅限於此。Figures 1A-1H depict only a single connector to facilitate the illustration of the relative positions of the layers, but may represent a general process for fabricating array connectors. The steps of forming the above layers are merely examples, but those skilled in the art can easily infer that the order of formation and the steps need to be changed in terms of component design or process. This case is not limited to the manufacturing method of this case is limited to this.

圖2A所繪示為本發明一實施例之陣列式連接器的立體示意圖。圖2B所繪示為圖2A的陣列單元放大立體示意圖。圖2C為圖2B沿著剖面線I-I’之剖面示意圖。圖2A-2C中均省略銲料凸塊,以方便描述。2A is a perspective view of an array connector according to an embodiment of the invention. FIG. 2B is an enlarged perspective view of the array unit of FIG. 2A. Figure 2C is a schematic cross-sectional view of Figure 2B taken along section line I-I'. Solder bumps are omitted in Figures 2A-2C for ease of description.

參照圖2A,為多個陣列單元所組成之陣列狀排列的連接器20,圖2B中僅刻意放大顯示單一個陣列單元。其中,矽基材之基底200乃包括環狀體結構200a並於中央具有一柱狀結構200b。而基底200上具多個塊狀結構240a分佈於環狀體結構200a上、單一塊狀結構240b位於中央柱狀結構200b上以及與單一塊狀結構240b相連之四根懸臂結構240c。單一塊狀結構240b上更具有一奈米碳管層230。Referring to FIG. 2A, a connector 20 of an array of a plurality of array units is arranged, and only a single array unit is deliberately enlarged in FIG. 2B. The base substrate 200 of the base material includes an annular body structure 200a and has a columnar structure 200b at the center. The substrate 200 has a plurality of block structures 240a distributed on the annular body structure 200a, a single block structure 240b on the central columnar structure 200b and four cantilever structures 240c connected to the single block structure 240b. The single block structure 240b further has a carbon nanotube layer 230.

參見圖2C,環狀體結構200a與中央柱狀結構200b乃為疊層結構,包括多晶矽層204、氧化矽層202與基底200(由上到下)。從上述圖1G可知,以硬罩幕層125作為蝕刻罩幕,從基底100的背面蝕刻基底100矽基材與氧化矽層102,直至多晶矽層104a暴露出來,可以得到如圖2B之環狀體結構200a與中央柱狀結構200b。Referring to FIG. 2C, the annular body structure 200a and the central columnar structure 200b are a laminated structure including a polysilicon layer 204, a ruthenium oxide layer 202, and a substrate 200 (from top to bottom). As can be seen from FIG. 1G above, the substrate 100 矽 substrate and the ruthenium oxide layer 102 are etched from the back surface of the substrate 100 with the hard mask layer 125 as an etch mask until the polysilicon layer 104a is exposed, and the ring body as shown in FIG. 2B can be obtained. Structure 200a and central columnar structure 200b.

參見圖2C,分佈於環狀體結構200a上之塊狀結構240a、位於中央柱狀結構200b上之單一塊狀結構240b以及與四根懸臂結構240c亦為疊層結構,包括金屬層210a、種子層208a與多晶矽層204。而懸臂結構240c更在與塊狀結構240a相連處兩旁更包括一壓電材料層206。壓電材料層206之尺寸遠小於懸臂結構240c之尺寸,其厚度與形狀亦可依照設計需要而調整。Referring to FIG. 2C, the block structure 240a distributed on the annular structure 200a, the single block structure 240b on the central column structure 200b, and the four cantilever structures 240c are also laminated, including the metal layer 210a, the seed. Layer 208a and polysilicon layer 204. The cantilever structure 240c further includes a piezoelectric material layer 206 on both sides of the junction with the block structure 240a. The size of the piezoelectric material layer 206 is much smaller than the size of the cantilever structure 240c, and its thickness and shape can also be adjusted according to design requirements.

由於四根懸臂彈簧連結固定端處,各設計一組壓電材料,可利用壓電特性,感測懸臂位移量,進可推估四根懸臂彈簧所提供正向力的大小。因此陣列式微型連接器將具有位移與力量感測的功能。Since the four cantilever springs are connected to the fixed end, a set of piezoelectric materials is designed, and the piezoelectric characteristics can be utilized to sense the displacement of the cantilever, and the magnitude of the forward force provided by the four cantilever springs can be estimated. Therefore, the array micro connector will have the function of displacement and force sensing.

當然,除了利用壓電材料外,亦可利用壓阻材料或利用上部元件接觸金屬與下部元件接觸金屬間所形成之電容,以壓阻或電容特性,感測懸臂位移量或推估正向力的大小。Of course, in addition to using a piezoelectric material, a piezoresistive material or a capacitor formed by contacting the metal with the lower member by the upper member may be utilized to sense the displacement of the cantilever or to estimate the positive force by piezoresistive or capacitive characteristics. the size of.

位於單一塊狀結構240b上之奈米碳管層230在後續封裝步驟,因奈米碳管具有良好的機械特性與導電性,在微小接觸力作用下,即可刺穿其他晶片之接點(凸塊或BGA封裝錫球)接觸表面上的氧化膜,而有效降低接觸電阻的大小,增加訊號傳遞時的穩定度,達到良好電性連接。The carbon nanotube layer 230 on the single block structure 240b is in the subsequent packaging step, and the carbon nanotubes have good mechanical properties and electrical conductivity, and can pierce the contacts of other wafers under the action of a small contact force ( The bump or BGA package solder ball contacts the oxide film on the surface, effectively reducing the contact resistance, increasing the stability of signal transmission, and achieving a good electrical connection.

上述各結構之各疊層之材料可參考前述製程中所述材料,但該些材料仍可視元件設計或製程需要更改。The materials of the respective layers of the above structures may refer to the materials described in the foregoing processes, but the materials may still be changed depending on the component design or process.

根據本發明之另一實施例,與前述圖1A之製造流程不同的是在圖1A形成多晶矽層104之後,省略形成壓電材料層之步驟。如圖3所示,於基底300上依序形成氧化矽層302與多晶矽層304之後,直接以摻雜方式於特定區域形成摻雜區306,摻雜物質例如是硼或鍺。此摻雜區306可視為一壓阻材料,可與後續形成之金屬層構成之壓阻感測機制,達到共面度檢測或正向力檢測之目的。後續製程參考前述圖1B-1H之製造流程,而最終結構顯示於圖4。According to another embodiment of the present invention, unlike the foregoing manufacturing flow of FIG. 1A, the step of forming the piezoelectric material layer is omitted after the polysilicon layer 104 is formed in FIG. 1A. As shown in FIG. 3, after the yttrium oxide layer 302 and the polysilicon layer 304 are sequentially formed on the substrate 300, the doping region 306 is formed directly in a specific region by doping, and the dopant substance is, for example, boron or germanium. The doped region 306 can be regarded as a piezoresistive material, and can be formed by a piezoresistive sensing mechanism formed by a subsequently formed metal layer to achieve the purpose of coplanarity detection or positive force detection. The subsequent process is referred to the manufacturing process of Figures 1B-1H above, and the final structure is shown in Figure 4.

圖4所繪示為本發明另一實施例之連接器的剖面示意圖。圖4中省略銲料凸塊,以方便描述。4 is a cross-sectional view showing a connector according to another embodiment of the present invention. Solder bumps are omitted in FIG. 4 for convenience of description.

請參照圖4,矽基材之基底400乃包括環狀體結構400a並於中央具有一柱狀結構400b。環狀體結構400a與中央柱狀結構400b乃為疊層結構,包括多晶矽層404、氧化矽層402與基底400(由上到下)。參見圖4,位於環狀體結構400a上之塊狀結構440a、位於中央柱狀結構400b上之單一塊狀結構440b以及與懸臂結構440c亦為疊層結構,包括金屬層410a、種子層408a與多晶矽層404。而懸臂結構440c更在與塊狀結構440a相連處兩旁之多晶矽層404中具摻雜區406。單一塊狀結構440b上更具有一奈米碳管層430。Referring to FIG. 4, the base substrate 400 of the base material includes an annular body structure 400a and has a columnar structure 400b at the center. The annular body structure 400a and the central columnar structure 400b are a laminated structure including a polycrystalline germanium layer 404, a tantalum oxide layer 402, and a substrate 400 (from top to bottom). Referring to FIG. 4, the block structure 440a on the annular body structure 400a, the single block structure 440b on the central columnar structure 400b, and the cantilever structure 440c are also laminated structures, including a metal layer 410a and a seed layer 408a. Polycrystalline germanium layer 404. The cantilever structure 440c has a doped region 406 in the polysilicon layer 404 on both sides of the junction with the bulk structure 440a. The single block structure 440b further has a carbon nanotube layer 430.

由於懸臂彈簧連結固定端處設計有壓阻材料(例如:摻雜區或其他適用金屬),而利用此壓阻感測特性,陣列式微型連接器將具有位移與力量感測的功能。Since the cantilever spring is fixed at the fixed end with a piezoresistive material (for example, a doped region or other suitable metal), and with this piezoresistive sensing characteristic, the array micro connector will have the function of displacement and force sensing.

因此本發明實施例之陣列式微型連接器設計於懸臂彈簧連接固定端處具壓電材料或壓阻材料,可分別利用壓電或壓阻感測機制,量測懸臂位移量與懸臂彈簧所提供正向力的大小。而本發明之陣列式連接器可適用於高密度或超細間距接合結構,因其具有量測共面度與正向力之機制,更可提升其功能與產業利用價值。Therefore, the array type micro connector of the embodiment of the invention is designed with a piezoelectric material or a piezoresistive material at the fixed end of the cantilever spring connection, and can measure the displacement of the cantilever and the cantilever spring by using a piezoelectric or piezoresistive sensing mechanism, respectively. The magnitude of the positive force. The array connector of the present invention can be applied to a high-density or ultra-fine pitch joint structure, and has the mechanism of measuring the coplanarity and the positive force, thereby improving its function and industrial utilization value.

此外,陣列式連接器在接觸金屬表面備置奈米碳管結構,因奈米碳管具有良好的機械特性與導電性,在微小接觸力作用下,即可刺穿凸塊或BGA錫球接觸表面的氧化膜,而有效降低接觸電阻的大小,增加訊號傳遞時的穩定度。In addition, the array connector is provided with a carbon nanotube structure on the contact metal surface, and the carbon nanotube has good mechanical properties and electrical conductivity, and can pierce the bump or BGA solder ball contact surface under the action of a small contact force. The oxide film effectively reduces the contact resistance and increases the stability of signal transmission.

本發明所提出之製造流程與現有製程相容,無須添加額外步驟或使用特殊材料,故元件之成本並未增加。此外,可視產品設計需要,調整製程步驟與/或搭配不同形狀圖案設計,更有彈性地製造陣列式連接器。The manufacturing process proposed by the present invention is compatible with existing processes, and no additional steps or special materials are required, so the cost of the components is not increased. In addition, visual product design needs, adjustment process steps and / or with different shape pattern design, more flexible manufacturing of array connectors.

雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

20...連接器20. . . Connector

100、200、300、400...基底100, 200, 300, 400. . . Base

100a...上表面100a. . . Upper surface

100b...下表面100b. . . lower surface

102、202、302、402...氧化矽層102, 202, 302, 402. . . Cerium oxide layer

104、204、304、404...多晶矽層104, 204, 304, 404. . . Polycrystalline layer

106、206...壓電材料層106, 206. . . Piezoelectric layer

306、406...摻雜區306, 406. . . Doped region

108a、108b、208a、408a...種子層108a, 108b, 208a, 408a. . . Seed layer

110a、110b、210a、410a...金屬層110a, 110b, 210a, 410a. . . Metal layer

112...種層112. . . Seed layer

120...銲料凸塊120. . . Solder bump

125...硬罩幕層125. . . Hard mask layer

130、230、430...奈米碳管層130, 230, 430. . . Carbon nanotube layer

200a...環狀體結構200a. . . Ring structure

200b...柱狀結構200b. . . Columnar structure

240a、240b、440a、440b...塊狀結構240a, 240b, 440a, 440b. . . Block structure

240c、440c...懸臂結構240c, 440c. . . Cantilever structure

圖1A~圖1H所繪示為本發明一實施例之陣列式連接器的製造流示意圖。1A-1H are schematic diagrams showing the manufacturing flow of an array connector according to an embodiment of the invention.

圖2A所繪示為本發明一實施例之陣列式連接器的立體示意圖。2A is a perspective view of an array connector according to an embodiment of the invention.

圖2B所繪示為圖2A的部份放大立體示意圖。FIG. 2B is a partially enlarged perspective view of FIG. 2A.

圖2C為圖2B沿著剖面線I-I’之剖面示意圖。Figure 2C is a schematic cross-sectional view of Figure 2B taken along section line I-I'.

圖3所繪示為本發明另一實施例之連接器的部份製造流程剖面圖。3 is a cross-sectional view showing a part of a manufacturing process of a connector according to another embodiment of the present invention.

圖4所繪示為本發明另一實施例之連接器的剖面示意圖。4 is a cross-sectional view showing a connector according to another embodiment of the present invention.

20...連接器20. . . Connector

Claims (12)

一種連接器結構,適用於封裝結構中,該連接器結構至少包括:一半導體基底,至少包括一環狀體結構與位於該環狀體結構中央之一柱狀結構;至少一懸臂結構,與該環狀體結構中央之該柱狀結構相連。A connector structure suitable for use in a package structure, the connector structure comprising at least: a semiconductor substrate comprising at least one annular body structure and a columnar structure at a center of the annular body structure; at least one cantilever structure, and The columnar structure in the center of the annular structure is connected. 如申請專利範圍第1項所述之連接器結構,其中更包括:多個第一塊狀結構位於該環狀體結構上;多個銲料凸塊,位於該些第一塊狀結構上;一第二塊狀結構位於該柱狀結構上;以及一奈米碳管層,位於該柱狀結構上之該第二塊狀結構,其中該懸臂結構與該環狀體結構相連處更包括一壓電材料層或一壓阻材料層。The connector structure of claim 1, further comprising: a plurality of first block structures on the annular body structure; a plurality of solder bumps on the first block structures; a second block structure is located on the columnar structure; and a carbon nanotube layer, the second block structure on the columnar structure, wherein the cantilever structure and the annular body structure further comprise a pressure A layer of electrical material or a layer of piezoresistive material. 如申請專利範圍第1項所述之連接器結構,其中該環狀體結構與該柱狀結構為疊層結構,更包括一氧化矽層位於該半導體基底之一上表面。The connector structure of claim 1, wherein the annular structure and the columnar structure are laminated structures, and further comprising a ruthenium oxide layer on an upper surface of the semiconductor substrate. 如申請專利範圍第2項所述之連接器結構,其中該第一、第二塊狀結構以及該懸臂結構為疊層結構,包括一多晶矽層、位於該多晶矽層上之一種子層與位於該種子層上之一金屬層。The connector structure of claim 2, wherein the first and second block structures and the cantilever structure are a laminated structure, comprising a polysilicon layer, a seed layer on the polysilicon layer, and the One of the metal layers on the seed layer. 如申請專利範圍第4項所述之連接器結構,其中該壓電材料層位於該多晶矽層與該種子層之間。The connector structure of claim 4, wherein the piezoelectric material layer is between the polysilicon layer and the seed layer. 如申請專利範圍第5項所述之連接器結構,其中該壓電材料層之材質包括氧化鋅。The connector structure of claim 5, wherein the material of the piezoelectric material layer comprises zinc oxide. 如申請專利範圍第2項所述之連接器結構,其中該壓阻材料層為一摻雜區位於該多晶矽層之中。The connector structure of claim 2, wherein the layer of piezoresistive material is a doped region located in the polysilicon layer. 如申請專利範圍第4項所述之連接器結構,其中其中該金屬層之材質包括鋁、銅或金。The connector structure of claim 4, wherein the material of the metal layer comprises aluminum, copper or gold. 如申請專利範圍第4項所述之連接器結構,其中該種子層之材質包括鈦、金或鉻。The connector structure of claim 4, wherein the seed layer material comprises titanium, gold or chromium. 如申請專利範圍第2項所述之連接器結構,其中該銲料凸塊之材質包括錫、錫銀合金或錫鉛合金。The connector structure of claim 2, wherein the material of the solder bump comprises tin, tin-silver alloy or tin-lead alloy. 如申請專利範圍第1項所述之連接器結構,至少包括兩相對的懸臂結構。The connector structure of claim 1, comprising at least two opposing cantilever structures. 如申請專利範圍第1項所述之連接器結構,至少包括四個互相相對的懸臂結構。The connector structure of claim 1, comprising at least four mutually opposite cantilever structures.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW461003B (en) * 2000-06-21 2001-10-21 Phicom Corp Connector apparatus
TW490890B (en) * 2000-05-02 2002-06-11 Fci Japan Kk Connector
TWI277244B (en) * 2003-12-09 2007-03-21 Fci Americas Technology Inc LGA-BGA connector housing and contacts
TW201104267A (en) * 2009-07-22 2011-02-01 Hon Hai Prec Ind Co Ltd Test apparatus for matrix type connector
TW201107770A (en) * 2009-08-24 2011-03-01 Hon Hai Prec Ind Co Ltd Testing device for surface mounted memory connector

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW490890B (en) * 2000-05-02 2002-06-11 Fci Japan Kk Connector
TW461003B (en) * 2000-06-21 2001-10-21 Phicom Corp Connector apparatus
TWI277244B (en) * 2003-12-09 2007-03-21 Fci Americas Technology Inc LGA-BGA connector housing and contacts
TW201104267A (en) * 2009-07-22 2011-02-01 Hon Hai Prec Ind Co Ltd Test apparatus for matrix type connector
TW201107770A (en) * 2009-08-24 2011-03-01 Hon Hai Prec Ind Co Ltd Testing device for surface mounted memory connector

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