201104267 六、發明說明： 【發明所屬之技術領域】 _]本發明涉及—種連接器測試裝置，尤指一種陣列型連接 器測試裝置。 【先前技術】 [0002]201104267 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a connector testing device, and more particularly to an array type connector testing device. [Prior Art] [0002]
[0003] [0004] ❹ 098124654 陣列型連接器為刀片式飼服器常用之表面連接設備之連 接器，其特點是針腳數量多、封裝精密、體積大’因而 給測试帶來了較大之困難。特別是在對連接器針腳焊點 之開路以及短路測試時，習知之KT (In Current[0003] [0004] [0004] 098 098124654 Array type connector is a connector for a surface connection device commonly used in a blade type feeding device, which is characterized by a large number of pins, a precise package, and a large volume, thus bringing a large test to the test. difficult. Especially in the open circuit and short circuit test of the connector pin solder joint, the conventional KT (In Current
Test)測試和飛針測試由於容易造成連接器針腳之損壞Test) and flying probe test are easy to cause damage to the connector pins
’因而無法對_型連接器進行測試，業界暫時沒有 類連接器之測試設備。 S 【發明内容】 馨於乂上内今，有必要提供—種陣列型連接器测試震置 -種陣列型連接器測試裝置，用於對一待測 少一陣列型連接器進_試，包括-資料獲取電路、 主控電路一存儲單元及—顯示單元’ 一 採集待測絲上之陣列型連接器之針 =電路 到之針腳資訊傳送給該主將採集 路電性相連，其中儲存有:路，該存館單元和主控電 訊，該主控電路將採隼=:之陣列型連接器之針卿資 之針腳資訊進行比較^訊與存儲單元中正常 “ 轉比較結果顯示在該顯千。。 上提示待測主板上之陣列型連接器之針腳是否正常平元 相較於習知技術’本發料㈣連接器 表單編號湖〇】 & } S 展置藉由談 乐'^頁〆共】3頁 衣 〇982〇42〇92~〇 [0005] 201104267 主控電路控制資料獲取電路對該陣列型連接器之各個針 腳進行測試’避免了習知测試治具對連接器針腳之損壞 【實施方式】 [0006] [0007] 凊參閱圖卜本發明陣列型連接器測試裝置較佳實施方式 I括-待測主板！〇〇、一資料獲取電路_、—主控電路 _ '-存儲單—開關單元咖及_顯示^元_ 。該貢料獲取電路200採集待測主板100上之陣列型連接 器之針«訊’並將採集到之針腳資訊傳送給該主控電 路300。該存儲單元4〇〇和主控電路_電性相連其中 儲存有正常之陣列型連接器之針脚資訊。該主控電路3〇〇 將採集到之針腳資訊與存儲單元備中正常之針腳資訊進 行比較，並將比較結果顯示在該顯示單元㈣〇上提示待測 主板上之陣列型連接器之針腳是否正常。該開關單元5〇〇 與主控電路300電性相連，用於向該主控電路3〇〇輸入密 碼並將正常之陣列型連接器之針g資訊错存到存儲單元 4 0 0 内。 請參閱圖2，該資料獲取電路⑽包括—複雜可編程邏輯 器件U1、一資料傳輸連接器：π、一25M晶振J2 '複數n溝 道場效電晶體Q0、Q1〜Qn及複數電阻。該複雜可編程邏輯 器件U1包括複數資料獲取引腳A1〜Αη、Β1〜βη、一資料發 送引腳Cl、複數時鐘引腳C2、CLK0〜CLK3、複數程式燒 入引腳TD0、TD1、TMS、TCK、控制引_D1、D2、複數 電源引腳VCC卜VCCn及複數接地引腳GND1〜GNDn。該複 數資料獲取引腳Al〜An分別經由複數電阻連接一3 電 098124654 表單編號A0101 第4頁/共13頁 0982042092-0 201104267 Ο 源’该複數負料獲取引腳Β1 *- Β η分別經由複數電阻接地。 該資料傳輸連接器J1包括一資料端DATA及一時鐘端CLK ’該資料發送引腳Cl和時鐘引腳C2分別連接資料端…以 及時鐘端CLK。該資料獲取引腳A1〜An、Bl~Bn分別用以 電性連接待測主板100上之陣列型連接器針腳並採集針腳 資訊，該複雜可編程邏輯器件U1對採集到之針腳資訊進 行處理後由資料發送引腳C1輸出。該晶振j2.包括一振盈 訊號輸出端OUT，該時鐘引腳CLK0~CLK3連接振盈訊號輸 出端OUT。該控制引腳Dl、D2分別連接場效電晶體q〇之 閘極和源極，該場效電晶體Q0之汲極連接該3. 3V電源。 該複數資料獲取引腳Bl~Bn還分別連接相應之場效電晶體 Q1〜Qn之源極，該場效電晶體Ql~Qn之閘極和没極連接該 3. 3V電源。該複雜可編程邏輯器件U1藉由控制場效電晶 體Q0、Q卜Qn之導通和截止對與該陣列型連接器針腳相連 接之電子元件充電和放電’從而獲得連接器針腳之焊點 資訊。該複數電源引腳VCC卜VCCn連接該3. 3V電源，該 ο [0008] 複數接地引腳GND1〜GNDn接地》 請參閱圖3，該主控電路300包括一微控制器U2及一功率 場效電晶體Q10。該微控制器U2包括複數資料登錄引腳H1 、H2、F0~Fn、控制引腳Gl、G4、一資料接收引腳G2、 一時鐘引腳G3、振盪訊號輸入端0SC1、振盪訊號輸出端 0SC2及複數資料輸出引腳E1〜En。該功率場效電晶體Q10 包括一閘極G、複數源極S1~S3及複數汲極D1〜D4。該控 制引腳G1連接功率場效電晶體Q10之閘極G和源極S1~S3 。該資料接收引腳G2和時鐘引腳G3連接功率場效電晶體 098124654 表單編號A0101 第5頁/共13頁 0982042092-0 201104267 之複數汲極01〜D4。該微控制器U2藉由控制功率場效 電晶體Q10之導通和截止對複雜可編程邏輯器件U1放電和 上電，避免在該複雜可編程邏輯器件υι在和陣列型連接 益之針腳熱插拔過程中燒壞複雜可編程邏輯器件U1。該 振盪Λ號輸入端0SC1和振盪訊號輸出端〇SC2經由一 12Μ 日曰振J4接地。该資料接收引腳G2和時鐘引腳⑵還分別連 接貢料傳輪連接器J1之資料端^了八和時鐘端CLK。 [0009] [⑻ 10] [0011] 098124654 該存儲單元400包括-電可擦可編程唯讀記憶體ϋ3及一跳 帽J3。該電可擦可編程唯讀記憶體ϋ3包括—串列時鐘引 腳SCL、-串列資料引腳SDA及一防寫引腳肝。該資料登 錄引腳Η1、H2分別連接串列時鐘.引腳似和串列資料引腳 SDA ’該防寫引腳WP經由該跳帽J3接地。該電可擦可編程 唯讀記憶體U3中儲存有正常之陣連接器之針腳資訊 ’當斷開該跳帽】3時可對電可擦可編程唯讀記憶體㈣ 打寫入資訊之操作，而當辑接該跳帽】3時可對電可擦可 編程唯讀記憶體U3進行擦除資訊之操作。 該開關單元500包括複數開關s〇〜Sn，該微控制器u2之資 料登錄引腳F0〜Fn分別連接複數開關S()〜Sn。該開關單元 500用於向主控電路300輸入密碼並將正常之陣列型連接 器之針腳資訊儲存到該存儲單元綱内。其中開關s〇為重 定開關，用於重定開關單元5〇〇之密碼。 該顯不單tlGGG包括-液晶顯示面板】5及一場效電晶體 Q20。該液晶顯示面板J5包括複數資料匯流排引腳 DB卜DBn及一背光控制引腳LEDK，該資料輸出引腳 E卜En分別連接複數資料匯流排引腳DM DBn，該控制引 表單編號A0101 第6頁/共13頁 〇982 201104267 [0012] Ο [0013]Ο [0014] 098124654 腳G4經由該場效電晶體㈣連接背光控制引腳lem。該 顯示皁tg600接收來自主控電路3〇〇之比較結果，並將比 較結果顯不在液晶顯示面板】5上提示待測主板1〇〇上之陣 列型連接器之針腳是否正常。其中控制引腳G4藉由該場 效電晶體Q20控制顯示單元6〇〇之背光顯示。 測試時，按照圖卜3所示將待測主板接入本發明陣列型連 接器測試裝置’該複雜可編程邏輯器件旧之資料獲取引 腳AHn、M~Bn分別採集待測主板1〇〇上之陣列型連接 器針腳資訊，該複雜可編程邏輯器件um採集到之針腳 資訊進行處理後㈣料發送_ei經由微控制謂之資 料接收引腳G2善送給該微控制器ϋ2。賴控制器Μ將接 收到之針腳資訊與儲存在存儲單元4〇〇中正常之針腳資訊 進订比較，並將比較結果㈣找顯_元_上提示待 測主板上之陣列型連接器之針腳是否正常。 本發明陣列型連接H測試裝置不限於對單_之陣列型連 接錢行測試’還可藉由主控電路3〇〇連接多個資料獲取 電路200同時對多個陣列型連接器進行測試，此時主控電 路30〇對不同資料獲取電路20 0採集到之針 工 單元咖中正常之針腳資訊進行比較，並將比較結果和不 同資枓獲取電路200之身份標識碼發送給顯示單元6〇()， 該顯示單元6GG根據比較結果顯示不同陣列型連接器之 腳是否正常。 碎上所述，本創作確已符合發明專利要求，爰依法提出 專利申請。惟’以上所述者僅為本創作之較佳實施例， 舉凡熟悉本創作技 藝之人士，爰依本創作之精神所作之 表單編號A〇l01 S 7頁/共13頁 0982042092-0 201104267 等效修飾或變化，皆應涵蓋於以下之申請專利範圍内。 【圖式簡單說明】 [0015] [⑻ 16] [0017] [0018] 圖1係本發明較佳實施方式陣列型連接器測試裝置之組成 框圖，該陣列型連接器測試裝置包括一待測主板、一資 料獲取電路、一主控電路、一存儲單元、一開關單元及 一顯示單元。 圖2係圖1中資料獲取電路之電路圖。 圖3係圖1中主控電路、存儲單元、開關單元及顯示單元 電性連接之電路圖。 【主要元件符號說明】 待測主板 100 資料獲取電路 200 主控電路 300 存儲單元 400 開關單元 500 顯示單元 600 複雜可編程邏 U1 微控制器 U2 輯器件 電可擦可編程 U3 資料傳輸連接 J1 唯讀記憶體 器 ' 2 5M晶振 J2 跳帽 J3 1 2 Μ晶振 J4 液晶顯不面板 J5 場效電晶體 Q0 、 Q1〜Qn 、 功率場效電晶 Q10 Q20 體 開關 S0~Sn 098124654 表單編號A0101 第8頁/共13頁 0982042092-0Therefore, it is impossible to test the _ type connector, and there is no test equipment for the type connector in the industry. S [Summary of the Invention] It is necessary to provide a type of array type connector test-sense-type array type connector test device for testing one array of connectors to be tested. The data acquisition circuit, the main control circuit, the storage unit, and the display unit are coupled to the pin of the array type connector on the wire to be tested, and the pin information is transmitted to the main device to connect the main circuit, wherein the storage device is: The road, the depository unit and the main control telecommunications, the main control circuit will compare the pin information of the array type connector of the 隼=: array and the normal information in the storage unit. It is suggested that the stitch of the array connector on the motherboard to be tested is normal. Compared with the prior art, the present invention (the fourth material (4) connector form number is 〇] & } S is displayed by the talker '^ 〆 】 】 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 0005 Damage [embodiment] [0006] [0007] Referring to the drawings, the preferred embodiment of the array type connector testing device of the present invention includes a motherboard to be tested, a data acquisition circuit, a main control circuit, a storage unit, a switch unit, and a The gongs acquisition circuit 200 collects the needles of the array connector on the motherboard 100 to be tested and transmits the collected pin information to the main control circuit 300. The storage unit 4 and the main The control circuit _ electrically connected therein stores the pin information of the normal array type connector. The main control circuit 3 compares the collected pin information with the normal pin information in the storage unit, and displays the comparison result in The display unit (4) indicates whether the pin of the array connector on the motherboard to be tested is normal. The switch unit 5 is electrically connected to the main control circuit 300, and is used to input a password to the main control circuit 3〇〇 The pin information of the normal array type connector is stored in the memory unit 400. Referring to FIG. 2, the data acquisition circuit (10) includes a complex programmable logic device U1, a data transmission connector: π, a 25M crystal oscillator. J2 'plural n The channel field effect transistor Q0, Q1~Qn and the complex resistor. The complex programmable logic device U1 includes a plurality of data acquisition pins A1~Αη, Β1~βη, a data transmission pin C1, a plurality of clock pins C2, CLK0~ CLK3, the complex program is burned into the pins TD0, TD1, TMS, TCK, the control leads _D1, D2, the complex power supply pins VCC Bu VCCn, and the complex ground pins GND1 ~ GNDn. The complex data acquisition pins A1 to An are respectively Complex resistance connection a 3 electric 098124654 Form No. A0101 Page 4 / Total 13 page 0982042092-0 201104267 Ο Source 'The complex negative material acquisition pin Β1 *- Β η is grounded via a complex resistor. The data transmission connector J1 includes a data terminal DATA and a clock terminal CLK'. The data transmission pin C1 and the clock pin C2 are respectively connected to the data terminal and the clock terminal CLK. The data acquisition pins A1~An, B1~Bn are respectively used to electrically connect the array connector pins on the motherboard 100 to be tested and collect pin information, and the complex programmable logic device U1 processes the collected pin information. Output by data transmission pin C1. The crystal oscillator j2 includes a vibration signal output terminal OUT, and the clock pins CLK0~CLK3 are connected to the oscillation signal output terminal OUT. The control pins D1 and D2 are respectively connected to the gate and the source of the field-effect transistor, and the drain of the field-effect transistor Q0 is connected to the 3. 3V power supply. The plurality of data acquisition pins B1 to Bn are also respectively connected to the sources of the corresponding field effect transistors Q1 to Qn, and the gates and the gates of the field effect transistors Q1 to Qn are connected to the 3. 3V power supply. The complex programmable logic device U1 obtains solder joint information of the connector pins by controlling the on and off of the field effect transistors Q0, Qb, Qn to charge and discharge the electronic components connected to the array connector pins. The plurality of power supply pins VCCBu VCCn are connected to the 3. 3V power supply, and the multiple ground pins GND1 to GNDn are grounded. Referring to FIG. 3, the main control circuit 300 includes a microcontroller U2 and a power field effect. Transistor Q10. The microcontroller U2 includes a plurality of data registration pins H1, H2, F0~Fn, control pins G1, G4, a data receiving pin G2, a clock pin G3, an oscillating signal input terminal 0SC1, and an oscillating signal output terminal 0SC2. And complex data output pins E1 ~ En. The power field effect transistor Q10 includes a gate G, a plurality of sources S1 to S3, and a plurality of gates D1 to D4. The control pin G1 is connected to the gate G and the source S1 to S3 of the power field effect transistor Q10. The data receiving pin G2 and the clock pin G3 are connected to the power field effect transistor 098124654 Form No. A0101 Page 5 of 13 0982042092-0 201104267 The plural bungee 01 to D4. The microcontroller U2 discharges and powers up the complex programmable logic device U1 by controlling the turn-on and turn-off of the power field effect transistor Q10, thereby avoiding hot plugging of the pins in the complex programmable logic device. The complex programmable logic device U1 is burned out during the process. The oscillation signal input terminal 0SC1 and the oscillation signal output terminal 〇SC2 are grounded via a 12-turn day resonance J4. The data receiving pin G2 and the clock pin (2) are also connected to the data terminal of the tributary transfer connector J1 and the clock terminal CLK, respectively. [0010] [0011] The memory unit 400 includes an electrically erasable programmable read only memory unit 3 and a jumper cap J3. The electrically erasable programmable read-only memory 3 includes a serial clock pin SCL, a serial data pin SDA, and an anti-write pin liver. The data registration pins Η1 and H2 are respectively connected to the serial clock. Pin-like and serial data pins SDA' The anti-write pin WP is grounded via the jumper J3. The electrically erasable programmable read-only memory U3 stores the stitch information of the normal array connector 'When the jump cap is turned off' 3, the operation of writing the information to the electrically erasable programmable read only memory (4) When the jump cap is 3, the operation of erasing information can be performed on the electrically erasable programmable read-only memory U3. The switch unit 500 includes a plurality of switches s〇~Sn, and the data registration pins F0 to Fn of the microcontroller u2 are connected to the plurality of switches S() to Sn, respectively. The switch unit 500 is configured to input a password to the main control circuit 300 and store pin information of a normal array type connector into the storage unit. The switch s〇 is a reset switch for resetting the password of the switch unit 5〇〇. The display tlGGG includes a liquid crystal display panel 5 and a power transistor Q20. The liquid crystal display panel J5 includes a plurality of data bus bar pins DBb DBn and a backlight control pin LEDK, and the data output pins Eb En are respectively connected to the plurality of data bus bar pins DM DBn, and the control lead form number A0101 is 6 Page / Total 13 pages 〇 982 201104267 [0012] 098 098124654 The foot G4 is connected to the backlight control pin lem via the field effect transistor (4). The display soap tg600 receives the comparison result from the main control circuit 3, and displays the comparison result on the liquid crystal display panel 5 to indicate whether the stitch of the array connector on the motherboard 1 to be tested is normal. The control pin G4 controls the backlight display of the display unit 6 by the field effect transistor Q20. During the test, the motherboard to be tested is connected to the array type connector test device of the present invention as shown in Figure 3, and the old data acquisition pins AHn and M~Bn of the complex programmable logic device are respectively collected on the motherboard to be tested. The array type connector pin information, after the complex programmable logic device um collects the pin information for processing (4), the material transmission _ei is sent to the microcontroller 经由2 via the micro control data receiving pin G2. The controller 进 compares the received pin information with the normal pin information stored in the storage unit 4〇〇, and compares the result (4) to the _ element_ to prompt the pin of the array connector on the motherboard to be tested. Is it normal? The array type connection H test device of the present invention is not limited to the single-array type connection test. It is also possible to connect a plurality of data acquisition circuits 200 by the main control circuit 3 to simultaneously test a plurality of array type connectors. The main control circuit 30 compares the normal pin information in the pin unit collected by the different data acquisition circuit 20 0, and sends the comparison result and the identification code of the different asset acquisition circuit 200 to the display unit 6 ( The display unit 6GG displays whether the feet of the different array type connectors are normal according to the comparison result. As stated above, this creation has indeed met the requirements of the invention patent and has filed a patent application in accordance with the law. However, the above description is only a preferred embodiment of the present invention. For those who are familiar with the creative technique, the form number A〇l01 S 7 pages/13 pages 0982042092-0 201104267 equivalent to the spirit of the creation is equivalent. Modifications or variations are intended to be included within the scope of the claims below. BRIEF DESCRIPTION OF THE DRAWINGS [0018] FIG. 1 is a block diagram showing the composition of an array type connector testing device according to a preferred embodiment of the present invention. The array type connector testing device includes a test unit. The main board, a data acquisition circuit, a main control circuit, a storage unit, a switch unit and a display unit. 2 is a circuit diagram of the data acquisition circuit of FIG. 1. 3 is a circuit diagram of the main control circuit, the storage unit, the switch unit, and the display unit in FIG. [Main component symbol description] Motherboard to be tested 100 Data acquisition circuit 200 Main control circuit 300 Memory unit 400 Switch unit 500 Display unit 600 Complex programmable logic U1 Microcontroller U2 Device Erasable programmable U3 Data transmission connection J1 Read only Memory device ' 2 5M crystal oscillator J2 jump cap J3 1 2 Μ crystal oscillator J4 LCD display panel J5 field effect transistor Q0, Q1~Qn, power field effect crystal Q10 Q20 body switch S0~Sn 098124654 Form No. A0101 Page 8 / Total 13 pages 0982042092-0