CN208781208U - PCI bus test board card - Google Patents
PCI bus test board card Download PDFInfo
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- CN208781208U CN208781208U CN201821673050.6U CN201821673050U CN208781208U CN 208781208 U CN208781208 U CN 208781208U CN 201821673050 U CN201821673050 U CN 201821673050U CN 208781208 U CN208781208 U CN 208781208U
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Abstract
The utility model discloses a PCI bus test integrated circuit board, this PCI bus test integrated circuit board includes: a PCI bus interface; the PCI bus interface chip is connected with the PCI bus interface and used for receiving signals on the PCI bus; the test main control chip is connected with the PCI bus interface and the PCI bus interface chip and is used for testing signals on the PCI bus and signals output by the PCI bus interface chip; the PCI bus interface chip and the test main control chip are powered by the PCI bus. The utility model discloses based on PCI bus interface chip and the signal on the test master control chip detects the PCI bus jointly, realized quick location trouble and carried out integrality, the technological effect of conformance testing to PCI bus signal.
Description
Technical field
The utility model relates to computer card field more particularly to a kind of pci bus test boards.
Background technique
This part intends to provides background or context for the utility model embodiment stated in claims.Herein
Description recognizes it is the prior art not because not being included in this section.
Currently, in the prior art mainly using the following two kinds mode to pci bus equipment (for example, computer PCI mainboard)
It is tested:
First way, using the PCI diagnostic card of standard.Its principle is the inspection using BIOS built in self testing program in mainboard
It surveys as a result, being shown one by one by code, in conjunction with where code meaning zoom table can soon know computer glitch.Example
Such as, during computer booting, PCI diagnostic card detects signal from pci bus, if computer is in BIOS initialization process
In, there is failure, then PCI diagnostic card can provide corresponding fault message.According to corresponding fault code, computer is inquired
The failure specification provided, so that it may which then fault point carries out malfunction elimination again.
The shortcomings that this mode is: essential information and the PCI that computer can only be detected during computer booting are total
Data on line cannot detect pci bus data and signal during computer reads and writes pci bus.In addition, due to PCI
The major function of diagnostic card is detection computer BIOS initialization procedure, rather than the detection specially designed for pci bus is set
It is standby, it can only detect in pci bus with the presence or absence of conflict, if being capable of normal allocation address space, data space, IRQ sharing point
With etc. resources, can not be judged in detail for the read/write conflict in pci bus, signal sequence, logic state.
The second way tests pci bus equipment using computer, by way of software programming, to calculating owner
Module device PCI on plate is written and read test operation, checks the data of pci bus feedback during the test, if it happens
Data exception just allows the digital output of another piece of pci card to become high level.It is quick that a multichannel is accessed outside computer
Oscillograph detects corresponding digital output signal, by capturing the rising edge of digital output signal, carrys out positioning failure generation
Moment, then by the other information of software detection, come together to analyze pci bus fault condition.
The shortcomings that this mode is: whether the reading data that can only test pci bus is correct, can not judge in pci bus
Clock signal, logical signal it is whether normal.Since the read-write data of pci bus are a continuous signal interaction processes, often
One step signal interaction is likely to malfunction, and is abnormal so as to cause the data finally read, therefore this mode can only be examined
Measure last as a result, and can not detect and position the failure occurred during pci bus signal interaction.In addition, due to current
The reason of computer operating system, computer software programs may be interrupted in the process of implementation by other software, so as to cause
PCI test program can not export digital quantity signal to oscillograph at once at the time of breaking down, and also can not just capture event in time
Hinder the moment, to the generation of fault location mistake occur.
It is total since PCI can not be detected by upper analysis it is found that the prior art is when carrying out fault detection to pci bus
The failure occurred during line signal interaction, there are problems that test result it is imperfect, can not quick positioning failure.
Utility model content
The utility model embodiment provides a kind of pci bus test board, existing to pci bus progress failure to solve
The scheme test result of detection is imperfect, can not quick positioning failure the technical issues of, which includes: PCI
Bus interface；Pci bus interface chip, connect with pci bus interface, for receiving the signal in pci bus；Test master control core
Piece is connect with pci bus interface and pci bus interface chip, for the signal and pci bus interface chip in pci bus
The signal of output is tested；Wherein, pci bus interface chip and test main control chip are powered by pci bus.
Further, pci bus test board further include: order DIP device is connect, for receiving with test main control chip
Test command.
Further, pci bus test board further include: LED charactrons are connect, for showing with test main control chip
The status information and/or test result information of pci bus test board.
Further, pci bus test board further include: string turns and chip, is connected to test main control chip and LED is digital
Between pipe, for the serial signal for testing main control chip to be converted to the parallel signal of driving LED charactrons.
Optionally, string turns and chip is 74HC595D chip.
Further, pci bus test board further include: serial communication interface is connect, for connecing with test main control chip
Acceptance Tests order.
Optionally, serial communication interface is also used to export the status information and/or test result letter of pci bus test board
Breath.
Further, pci bus test board further include: serial communication interface driving chip is connected to test master control core
Between piece and serial communication interface, it to be used for level conversion.
Optionally, serial communication interface driving chip is MAX232 chip.
Optionally, serial communication interface is RS232 interface.
Further, pci bus test board further include:
Digital signal output interface is connect with pci bus interface chip, is used for pci bus interface chip to external equipment
Output digit signals, wherein digital signal is used to characterize the status information and/or test result information of pci bus test board.
Further, pci bus test board further include:
Isolating chip is connected between digital signal output interface and pci bus interface chip, for electrical letter to be isolated
Number.
Optionally, pci bus interface chip is PCI9052 chip, and test main control chip is STM32 chip.
Wherein, the interface access test main control chip of following at least one signal of pci bus interface chip: CS# piece choosing
Signal, RD# read command signal, WR# write command signal, RES# assist command signal, WIF# assist command signal, BHE# auxiliary life
Enable signal, Addr [12:0] address signal.
Wherein, the interface access test main control chip of following at least one signal of pci bus: FRAME# signal, IRDY#
Signal, CLK signal, RST# signal.
In the utility model embodiment, pci bus is received by the pci bus interface chip connecting with pci bus interface
On signal detected in pci bus by the test main control chip being all connected with pci bus interface and pci bus interface chip
Signal and pci bus interface chip output signal, reached based on pci bus interface chip and test main control chip
The purpose of signal in common detection pci bus, to realize quick positioning failure and be carried out to pci bus signal complete
Property, the technical effect of uniformity test.
Detailed description of the invention
In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment
Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is only
It is some embodiments of the utility model, for those of ordinary skill in the art, in the premise not made the creative labor
Under, it is also possible to obtain other drawings based on these drawings.In the accompanying drawings:
Fig. 1 is the pci bus test board schematic diagram in the utility model embodiment；
Fig. 2 is that the signal of the pci bus interface chip and test main control chip in the utility model embodiment transmits signal
Figure；
Fig. 3 is that the string in the utility model embodiment turns simultaneously LED charactrons drive circuit schematic diagram；
Fig. 4 is the PCI power supply distribution schematic diagram in the utility model embodiment.
Specific embodiment
It is right with reference to the accompanying drawing for the objectives, technical solutions, and advantages of the embodiments of the present invention are more clearly understood
The utility model embodiment is described in further details.Here, the illustrative embodiments and their description of the utility model are for solving
The utility model is released, but is not intended to limit the scope of the present invention.
Due to having occurred in pci bus transmission data procedures, many orders are given, information feedback, read data exchange, write number
According to processes such as exchanges, during each can the timing of strict control bus signals will lead to tight in case of timing error
Weight error in data.And there is presently no a set of equipment tested specifically for pci bus data and devices, therefore are occurring
Pci bus reading and writing data mistake or pci bus read-write data it is slow when, can not fault point, it is even more impossible to check failure.
To solve the above-mentioned problems, the utility model embodiment provides a kind of pci bus test board, as shown in Figure 1,
The pci bus test board includes: pci bus interface 10, pci bus interface chip 20 and test main control chip 30.
Wherein, pci bus interface chip 20 is connect with pci bus interface 10, for receiving the signal in pci bus；
Main control chip 30 is tested, is connect with pci bus interface 10 and pci bus interface chip 20, for pci bus
Signal and pci bus interface chip output signal tested；
Wherein, pci bus interface chip 20 and test main control chip 30 are powered by pci bus.
As a kind of optional embodiment, pci bus interface chip 20 that the utility model embodiment uses can be for
PCI9052 chip, the test main control chip 30 used can be STM32 chip.Wherein, pci bus interface chip 20 is as follows
At least one signal interface access test main control chip: CS# chip selection signal, RD# read command signal, WR# write command signal,
RES# assist command signal, WIF# assist command signal, BHE# assist command signal, Addr [12:0] address signal；Pci bus
Following at least one signal interface access test main control chip 30:FRAME# signal, IRDY# signal, CLK signal, RST#
Signal.
Fig. 2 is that the signal of the pci bus interface chip and test main control chip in the utility model embodiment transmits signal
Figure, as shown in Fig. 2, from computer motherboard provide pci bus signal (AD [31:0], C/BE [3:0], PAR, FRAME#,
IRDY#, TRDY, STOP#, IDSEL, DEVSEL#, PERR#, SERR#, CLK, RST#, INTA#, LOCK#), it is directly entered
PCI9052 protocol chip (pci bus interface chip).Wherein, the letter that FRAME# signal starts as important pci bus communication
Number, it is directly entered STM32 main control chip (test main control chip), is used as failing edge interrupt signal；IRDY# signal conduct
The ready signal of PCI main equipment and the object of STM32 main control chip monitoring；CLK signal itself is the clock of pci bus
Signal, STM32 main control chip use external timing signal of the signal as itself chip, so that computer and this programme device
The problem of it is synchronous to realize clock, no longer will appear clock dislocation, signal analysis deviation.RST# signal is answered as pci bus
Position signal, while the also reset signal as STM32 main control chip, ensure that computer is consistent with the logic of this programme device
Property.
As shown in Fig. 2, PCI9052 protocol chip (pci bus interface chip) output local bus signal (Data [15:
0], Addr [12:0], WIF#, BHE#, INT1#, RES#, BUSY#, INT0#, RD#, WR#, CS#), access STM32 main control chip
(test main control chip), thus come monitor for signal.For important chip selection signal CS#, read command RD#, write order
WR#, assist command RES#, WIF#, BHE#, address signal Addr [12:0], are the letters of STM32 main control chip key monitoring
Number and the utility model embodiment propose PCI test extension function.
It should be noted that carrying out pci bus number by pci bus test board provided by the embodiment of the utility model
When according to test, need to be carried out according to different test commands.For this purpose, the utility model embodiment provides the following two kinds
The embodiment of input test order:
In a kind of optional embodiment, pci bus test board provided by the embodiment of the utility model can also include:
Order DIP device 40 is connect, for receiving test command with test main control chip 30.
Be easy it is noted that by order DIP device 40 receive test command in the case where, as a kind of optional side
Case, pci bus test board provided by the embodiment of the utility model can also include: LED charactrons 50, with test main control chip
30 connections, for showing the status information and/or test result information of pci bus test board.
Since pci bus test content, operating mode are complicated, the utility model embodiment can use 78 sections of LED numbers
Code pipe shows the information such as current various controller parameters, state.Cooperate different order DIP devices 40, LED charactrons can
To show system information abundant, for the program segment content for debugging and examining present day analog device to run.
Further, pci bus test board can also include: string turn and chip 60, be connected to test main control chip with
Between LED charactrons, for the serial signal for testing main control chip to be converted to the parallel signal of driving LED charactrons.
Optionally, above-mentioned string turns and chip 60 can use SN74HC595D chip.Simultaneously 74HC595D is turned using high speed string
Chip, this programme can maximize the interface pin quantity for reducing the chip and STM32 main control chip, to save preciousness
Controller resource.By by the SER signal interface of the QH ' pin of leftmost side 74HC595D chip and next 74HC595D chip
It is connected, is achieved that the cascade Mach-Zehnder interferometer of 78 sections of 74HC595D chips.
Fig. 3 is that the string in the utility model embodiment turns simultaneously LED charactrons drive circuit schematic diagram, as shown in figure 3, passing through
OC#, RCLK, SRCLR#, SRCLK, SER signal interface, STM32 main controller can directly control the output content of LED charactrons,
By serial shift read-write operation, can be reached with each luminous point of each charactron of independent control by logical combination mode
The display of any information.
Herein it should be noted that for common test pattern, toggle switch (i.e. order DIP device 40) can be passed through
It is given to carry out shortcut command, in this way for common test content and project, does not need external communication and carries out data exchange, quickly
Complete relevant test；For quick test pattern, 7 LED charactrons are activated simultaneously, recycle the state and survey of display device
Test result facilitates tester and test job is rapidly completed.
In another optional embodiment, pci bus test board provided by the embodiment of the utility model can also be wrapped
Include: serial communication interface 70 is connect, for receiving test command with test main control chip 30.Preferably, the serial communication interface
For RS232 interface.
Optionally, above-mentioned serial communication interface is also used to export the status information and/or test knot of pci bus test board
Fruit information.
By external serial communication interface (for example, RS232), test command is sent to STM32 main control chip, to PCI
The different pins of bus are tested, and even various signals carry out complicated combined test；The test of STM32 main control chip is completed
Afterwards, then by serial ports 232 test result is sent out.
Since the serial ports of STM32 main control chip is powered using 3.3V, and external serial ports 232 is 12V power supply, it is therefore desirable into
Line level conversion.As a result, as an alternative embodiment, pci bus test board provided by the embodiment of the utility model
It can also include: serial communication interface driving chip 80, be connected between test main control chip and serial communication interface, for electricity
Flat turn is changed.
Optionally, which can be MAX232 chip.
As a kind of optional embodiment, pci bus test board provided by the embodiment of the utility model can also include:
Digital signal output interface 90 is connect with pci bus interface chip, exports number to external equipment for pci bus interface chip
Word signal, wherein digital signal is used to characterize the status information and/or test result information of pci bus test board.
Further, above-mentioned pci bus test board can also include: isolating chip 11, be connected to digital signal output
Between interface 90 and pci bus interface chip 20, for electric signal to be isolated.
The digital output signal touching by being isolated may be implemented by above-mentioned digital signal output interface 90 and isolating chip 11
It sends out oscillograph and carries out fault waveform capture.
It is optional based on any one of the above or preferred embodiment, the utility model embodiment use pci bus total for PCI
The power supply of line test board, not only solves the source problem that comes of the module for power supply, also solves flexible expansion, different simulators very well
Electrical equipotential problem.
It is alternatively possible to be tested using 13 feet of the Side B of pci bus interface and 12 feet of Side A as pci bus
The reference earth signal of board power supply；Powered using 62 feet of Side B and 62 feet of Side A as pci bus test board+
5V power supply.
Fig. 4 is the PCI power supply distribution schematic diagram in the utility model embodiment, as shown in figure 4, selection PCI board card gold hand
The two sides A and Side B Side of finger selects power supply signal, will greatly improve the reliability of power supply, holds so that module is available
Continuous, stable power supply.For example, 13 feet of selection Side B and 12 feet of Side A, without selecting other pins to join as power supply
Earth signal GND is examined, is because the signal near the key is also with reference to ground GND, or is stick signal Reserved, it can be to prevent
Only user's mistake installs module damage caused by the module.In addition, select Side B 62 feet and Side A 62 feet as+
5V power supply is because the signal at most will lead to module even if setup error leads to signal poor contact in card edge
Abnormal electrical power supply, module can not work, without damaging inside modules electrical component.
Due to the counnter attack plugging function of PCI board card itself, certain protection also is provided for the correct installation of the module, is passed through
50, the empty occupy-place of 51 feet is embodied.
From the foregoing, it will be observed that the utility model embodiment using test main control chip, pci bus protocol chip, string turn and chip,
And turn the functions such as serial core piece, order dial-up, LED driving, the flexible self-checking function of the module is realized, module working condition is jumped
Turn, monitoring, setting and debugging function, based on test main control chip (STM32 chip) and pci bus interface chip (PCI9052 assist
Discuss chip), clock signal, logical signal and the data read-write in pci bus are detected jointly, quickly analysis and positioning failure
At the time of generation and failure cause, detailed report is provided by serial ports 232 or quickly shows failure by LED charactrons
Code can also carry out fault waveform capture by the digital output signal triggering oscillograph being isolated, it is total to solve PCI in the prior art
Line test is imperfect, imperfect to the process detection of clock signal, logical signal and data read-write in pci bus cycle.
Particular embodiments described above has carried out into one the purpose of this utility model, technical scheme and beneficial effects
Step is described in detail, it should be understood that being not used to limit this foregoing is merely specific embodiment of the utility model
The protection scope of utility model, within the spirit and principle of the utility model, any modification for being made, changes equivalent replacement
Into etc., it should be included within the scope of protection of this utility model.
Claims (14)
1. a kind of pci bus test board characterized by comprising
Pci bus interface；
Pci bus interface chip is connect with the pci bus interface, for receiving the signal in pci bus；
Main control chip is tested, is connect with the pci bus interface and the pci bus interface chip, for the pci bus
On signal and the pci bus interface chip output signal tested；
Wherein, the pci bus interface chip and the test main control chip are powered by pci bus.
2. pci bus test board as described in claim 1, which is characterized in that the pci bus test board further include:
Order DIP device is connect, for receiving test command with the test main control chip.
3. pci bus test board as claimed in claim 2, which is characterized in that the pci bus test board further include:
LED charactrons are connect with the test main control chip, for show the pci bus test board status information and/
Or test result information.
4. pci bus test board as claimed in claim 3, which is characterized in that the pci bus test board further include:
String turns and chip, is connected between the test main control chip and the LED charactrons, is used for the test master control core
The serial signal of piece is converted to the parallel signal for driving the LED charactrons.
5. pci bus test board as claimed in claim 4, which is characterized in that the string turns and chip is 74HC595D core
Piece.
6. pci bus test board as described in claim 1, which is characterized in that the pci bus test board further include:
Serial communication interface is connect with the test main control chip, for receiving test command, and the output pci bus
The status information and/or test result information of test board.
7. pci bus test board as claimed in claim 6, which is characterized in that the pci bus test board further include:
Serial communication interface driving chip is connected between test main control chip and the serial communication interface, is turned for level
It changes.
8. pci bus test board as claimed in claim 7, which is characterized in that the serial communication interface driving chip is
MAX232 chip.
9. pci bus test board as claimed in claim 8, which is characterized in that the serial communication interface connects for RS232
Mouthful.
10. pci bus test board as described in claim 1, which is characterized in that the pci bus test board further include:
Digital signal output interface is connect with the pci bus interface chip, is used for the pci bus interface chip to outside
Equipment output digit signals, wherein the digital signal be used for characterize the pci bus test board status information and/or
Test result information.
11. pci bus test board as claimed in claim 10, which is characterized in that the pci bus test board is also wrapped
It includes:
Isolating chip is connected between the digital signal output interface and the pci bus interface chip, electrical for being isolated
Signal.
12. the pci bus test board as described in any one of claim 1 to 11, which is characterized in that pci bus interface
Chip is PCI9052 chip, and the test main control chip is STM32 chip.
13. pci bus test board as claimed in claim 12, which is characterized in that the pci bus interface chip it is as follows
The interface of at least one signal accesses the test main control chip: CS# chip selection signal, RD# read command signal, WR# write order letter
Number, RES# assist command signal, WIF# assist command signal, BHE# assist command signal, Addr [12:0] address signal.
14. pci bus test board as claimed in claim 12, which is characterized in that the following at least one of the pci bus
The interface of signal accesses the test main control chip: FRAME# signal, IRDY# signal, CLK signal, RST# signal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821673050.6U CN208781208U (en) | 2018-10-16 | 2018-10-16 | PCI bus test board card |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821673050.6U CN208781208U (en) | 2018-10-16 | 2018-10-16 | PCI bus test board card |
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| CN208781208U true CN208781208U (en) | 2019-04-23 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110096010A (en) * | 2019-05-14 | 2019-08-06 | 广州致远电子有限公司 | Core board and equipment |
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2018
- 2018-10-16 CN CN201821673050.6U patent/CN208781208U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110096010A (en) * | 2019-05-14 | 2019-08-06 | 广州致远电子有限公司 | Core board and equipment |
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