CN203520383U - Fitec mainboard fault display circuit and display card - Google Patents
Fitec mainboard fault display circuit and display card Download PDFInfo
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- CN203520383U CN203520383U CN201320686337.3U CN201320686337U CN203520383U CN 203520383 U CN203520383 U CN 203520383U CN 201320686337 U CN201320686337 U CN 201320686337U CN 203520383 U CN203520383 U CN 203520383U
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- soaring
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- 238000012545 processing Methods 0.000 claims abstract description 9
- 239000003990 capacitor Substances 0.000 claims description 16
- 238000001914 filtration Methods 0.000 claims description 6
- 210000001699 lower leg Anatomy 0.000 claims description 2
- 238000013461 design Methods 0.000 abstract description 3
- 238000001514 detection method Methods 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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Abstract
The utility model belongs to the field of mainboard fault detection, and provides a Fitec mainboard fault display circuit and a display card. According to the Fitec mainboard fault display circuit and the display card, a decoding latch module reads a message sent to a serial port by a Fitec mainboard BIOS chip through a goldfinger connector and performs decoding latch processing, a seven-segment digital display module is used for displaying processed data and can display the fault position of a Fitec mainboard, and then, a user debugs the fault according to a display result, so that the problem of troublesome connection of serial port lines is solved, and other computers are not required for matching use. The Fitec mainboard fault display circuit provided by the embodiment is simple, stable and reliable in design.
Description
Technical field
The utility model belongs to main board failure detection field, relates in particular to a kind of main board failure display circuit and display card of soaring.
Background technology
X86 mainboard platform BIOS chip unloading phase can detect main part and peripheral equipment, whether all no problem look at, and BIOS chip can write POST CODE information 80h address in the process detecting, convenient research and development tester tests and debugging, and the POST card that X86 mainboard platform is used is generally the LPC Interface realization by South Bridge chip.
And the adjustment method of the mainboard platform of soaring at present can only be debugged by Serial Port Line, applicable Serial Port Line wiring bothers very much, also needs to mix computer of another platform and debugs, very inconvenient, LPC interface is not provided on the platform of soaring, and existing POST card is not also suitable for the mainboard of soaring.
Utility model content
The utility model provides a kind of main board failure display circuit of soaring, be intended to solve the POST card that existing X86 mainboard platform uses and can not be applied to the mainboard platform of soaring, and the existing mainboard platform of soaring shows that faulty circuit used Serial Port Line to connect and bother very much and need other computers to coordinate the problem that could debug the fault demonstrating.
In order to solve the problems of the technologies described above, the utility model is achieved in that a kind of main board failure display circuit of soaring, be connected with the mainboard BIOS chip of soaring, described in the main board failure display circuit of soaring comprise:
Golden finger connector;
By described golden finger connector with described in the mainboard BIOS chip of soaring be connected, the mainboard BIOS chip of soaring described in reading system start-up course sends to information in the serial ports row decoding of going forward side by side and latchs the decoding latch module of processing and exporting;
Be connected the seven segment numerical display module fault of the described mainboard of soaring being shown according to the output signal of described decoding latch module with the output terminal of described decoding latch module.
In the utility model, decoding latch module reads by golden finger connector the mainboard BIOS chip of soaring and sends to information in the serial ports row decoding of going forward side by side and latch processing, by seven segment numerical display module, the data after processing are shown, can show the abort situation of the mainboard of soaring, then user debugs fault according to demonstration result, solved and adopted Serial Port Line to connect the problem of trouble, and do not need other computers to be used in conjunction with, the main board failure display circuit simplicity of design, reliable and stable of soaring that the utility model embodiment provides.
Accompanying drawing explanation
Fig. 1 is the modular structure figure of the main board failure display circuit of soaring that provides of the utility model embodiment;
Fig. 2 is the circuit structure diagram of the main board failure display circuit of soaring that provides of the utility model embodiment.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein is only in order to explain the utility model, and be not used in restriction the utility model.
Below in conjunction with specific embodiment, specific implementation of the present utility model is described in detail:
Fig. 1 shows the modular structure of the main board failure display circuit of soaring that the utility model embodiment provides, and for convenience of explanation, only lists the part relevant to the utility model embodiment.
As the utility model one embodiment, the main board failure display circuit of soaring that the utility model provides, is connected with the mainboard BIOS chip U1 that soars, and this main board failure display circuit of soaring comprises:
Golden finger connector MINICARD;
By golden finger connector MINICARD, be connected with the mainboard BIOS chip U1 that soars, the mainboard BIOS chip U1 that soars in reading system start-up course sends to information in serial ports to carry out decoding and latchs the decoding latch module 101 of processing and exporting;
Be connected the seven segment numerical display module 102 fault of the mainboard of soaring being shown according to the output signal of decoding latch module 101 with the output terminal of decoding latch module 101.
As the utility model one embodiment, the main board failure display circuit of soaring also comprises:
Be connected the indicating module 103 that the duty of the main board failure display circuit of soaring is indicated with the 3V voltage output end of the mainboard BIOS chip U1 that soars;
Power end is connected with the power end of decoding latch module 101, the filtration module 104 that the voltage of input decoding latch module 101 is carried out to filtering.
Fig. 2 shows the circuit structure of the main board failure display circuit of soaring that the utility model embodiment provides, and for convenience of explanation, only lists the part relevant to the utility model embodiment.
As the utility model one embodiment, the voltage input end V3_SYS1 of golden finger connector MINICARD is connected with the 3V voltage output end V3 of the mainboard BIOS chip U1 that soars, the data receiver DEBG_URXD of golden finger connector MINICARD is connected with the signal output part VOUT of the mainboard BIOS chip U1 that soars, and the data sending terminal DEBG_UTXD of golden finger connector MINICARD is connected with the data receiver RXD of decoding latch module 101.
As the utility model one embodiment, decoding latch module 101 comprises:
Chip U2 is latched in the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, quadrielectron R4, the first capacitor C 1 and decoding;
The power end VCC of chip U2 is latched in decoding and the voltage output end V3_SYS2 of golden finger connector MINICARD is connected, the high position that chip U2 is latched in decoding shows that output terminal DGH shows that with high-order in seven segment numerical display module 102 control end DGHJ_R is connected by the first resistance R 1, the low level that chip U2 is latched in decoding shows that output terminal DGL shows that by the second resistance R 2 and low level in seven segment numerical display module 102 control end DGLJ is connected, the reset terminal RST that chip U2 is latched in decoding is connected with the voltage output end V3_SYS2 of golden finger connector MINICARD by the 3rd resistance R 3, the first capacitor C 1 is connected to decoding and latchs between the reset terminal RST and ground of chip U2, the data receiver RXD of chip U2 is latched in decoding and the data sending terminal DEBG_UTXD of golden finger connector MINICARD is connected, the data output end TXD of chip U2 is latched in decoding and the data receiver DEBG_URXD of golden finger connector DEBG_UTXD is connected, the first to the 7th digital display tube pin LED_A of chip U2 is latched in decoding, LED_B, LED_C, LED_D, LED_E, LED_F, LED_G is connected with seven segment numerical display module, the earth terminal GND ground connection of chip U2 is latched in decoding.
As the utility model one embodiment, seven segment numerical display module 102 comprises the first seven segment numerical display tube UD1 and the second seven segment numerical display tube UD2;
The first seven segment numerical display tube UD1 is high-order digital display tube, and the second seven segment numerical display tube UD2 is low level digital display tube, the first pin to the seven pin A of the first seven segment numerical display tube UD1, B, C, D, E, F, G respectively with the first pin to the seven pin A of the second seven segment numerical display tube, B, C, D, E, F, G connects, the high position that the octal AC1 of the first seven segment numerical display tube UD1 and the 9th pin AC2 are connected to seven segment numerical display module 102 shows control end DGHJ_R, the low level that the octal AC1 of the second seven segment numerical display tube UD2 and the 9th pin AC2 are connected to seven segment numerical display module 102 shows control end DGLJ, the first pin A of the first seven segment numerical display tube UD1, crus secunda B, the 6th pin F and the 7th pin G latch respectively the first digital display tube pin LED_A of chip U2 with decoding, the second digital display tube pin LED_B, the 6th digital display tube pin LED_F and the 7th digital display tube pin LED_G connect, the tripod C of the first seven segment numerical display tube UD1, the 4th pin D and the 5th pin E latch respectively the 3rd digital display tube pin LED_C of chip U2 with decoding, the 4th digital display tube pin LED_D and the 5th digital display tube pin LED_E connect.
As the utility model one embodiment, indicating module 103 comprises the 4th resistance R 4 and light emitting diode D1;
The 4th resistance R 4 and light emitting diode D1 are connected in series between the 3V voltage output end V3 and ground of the mainboard BIOS chip U1 that soars.
As the utility model one embodiment, filtration module 105 comprises:
The second capacitor C 2, the 3rd capacitor C 3 and the 4th capacitor C 4;
The second capacitor C 2 and the 3rd capacitor C 3 and the 4th capacitor C 4 are connected in parallel between the voltage output end V3_SYS2 and ground of golden finger connector MINICARD.
The principle of work of the main board failure display circuit of soaring below the utility model embodiment being provided describes.
After circuit start, by observing the pilot lamp (light emitting diode D1) of indicating module 103, whether light to judge that whether the main board failure display circuit of soaring is working properly, after light emitting diode D1 normal circuit, decoding is latched chip U2 and by golden finger connector MINICARD, from the mainboard BIOS chip U1 that soars, is read the information sending in serial ports and carry out decoding and latch processing, then export to the first seven segment numerical display tube UD1 and the second seven segment numerical display tube UD2 in seven segment numerical display module 102, controlling the signal that the first seven segment numerical display tube UD1 and the second seven segment numerical display tube UD2 latch chip U2 output to decoding shows, the connotation that user gives POSTCODE different in error code table as an addition according to the result contrast manufacturer showing is come decision problem place, then debug, deal with problems.
The utility model also provides a kind of main board failure display card of soaring, and this main board failure display card of soaring comprises the above-mentioned main board failure display circuit of soaring.
In the utility model embodiment, decoding latch module reads by golden finger connector the mainboard BIOS chip of soaring and sends to information in the serial ports row decoding of going forward side by side and latch processing, by seven segment numerical display module, the data after processing are shown, can show the abort situation of the mainboard of soaring, then user debugs fault according to demonstration result, solved and adopted Serial Port Line to connect the problem of trouble, and do not need other computers to be used in conjunction with, the main board failure display circuit simplicity of design, reliable and stable of soaring that the utility model embodiment provides.
The foregoing is only preferred embodiment of the present utility model; not in order to limit the utility model; all any modifications of doing within spirit of the present utility model and principle, be equal to and replace and improvement etc., within all should being included in protection domain of the present utility model.
Claims (8)
1. the main board failure display circuit of soaring, is connected with the mainboard BIOS chip of soaring, it is characterized in that, described in the main board failure display circuit of soaring comprise:
Golden finger connector;
By described golden finger connector with described in the mainboard BIOS chip of soaring be connected, the mainboard BIOS chip of soaring described in reading system start-up course sends to information in the serial ports row decoding of going forward side by side and latchs the decoding latch module of processing and exporting;
Be connected the seven segment numerical display module fault of the described mainboard of soaring being shown according to the output signal of described decoding latch module with the output terminal of described decoding latch module.
2. the main board failure display circuit of soaring as claimed in claim 1, is characterized in that, described in the main board failure display circuit of soaring also comprise:
Be connected the indicating module that described duty of soaring main board failure display circuit is indicated with the 3V voltage output end of the described mainboard BIOS chip of soaring;
Power end is connected with the power end of described decoding latch module, the filtration module that carries out filtering to inputting the voltage of described decoding latch module.
3. the main board failure display circuit of soaring as claimed in claim 1, it is characterized in that, the voltage input end of described golden finger connector with described in the soar 3V voltage output end of mainboard BIOS chip be connected, the data receiver of described golden finger connector with described in the soar signal output part of mainboard BIOS chip be connected, the data sending terminal of described golden finger connector is connected with the data receiver of described decoding latch module.
4. the main board failure display circuit of soaring as claimed in claim 3, is characterized in that, described decoding latch module comprises:
Chip is latched in the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, quadrielectron R4, the first capacitor C 1 and decoding;
The power end of chip is latched in described decoding and the voltage output end of described golden finger connector is connected, the high position that chip is latched in described decoding shows that output terminal shows that with high-order in described seven segment numerical display module control end is connected by described the first resistance R 1, the low level that chip is latched in described decoding shows that output terminal shows that by described the second resistance R 2 and low level in described seven segment numerical display module control end is connected, the reset terminal that chip is latched in described decoding is connected with the voltage output end of described golden finger connector by described the 3rd resistance R 3, described the first capacitor C 1 is connected to described decoding and latchs between the reset terminal and ground of chip, the data receiver of chip is latched in described decoding and the data sending terminal of described golden finger connector is connected, the data output end of chip is latched in described decoding and the data receiver of described golden finger connector is connected, the first to the 7th digital display tube pin that chip is latched in described decoding is connected with described seven segment numerical display module, the earth terminal ground connection of chip is latched in described decoding.
5. the main board failure display circuit of soaring as claimed in claim 4, is characterized in that, described seven segment numerical display module comprises the first seven segment numerical display tube and the second seven segment numerical display tube;
Described the first seven segment numerical display tube is high-order digital display tube, described the second seven segment numerical display tube is low level digital display tube, the first pin to the seven pin of described the first seven segment numerical display tube are connected with the first pin to the seven pin of described the second seven segment numerical display tube respectively, the octal of described the first seven segment numerical display tube and the 9th pin are connected to the described high-order control end that shows, the octal of described the second seven segment numerical display tube and the 9th pin are connected to described low level and show control end, the first pin of described the first seven segment numerical display tube, crus secunda, the 6th pin and the 7th pin latch respectively the first digital display tube pin of chip with described decoding, the second digital display tube pin, the 6th digital display tube pin and the 7th digital display tube pin connect, the tripod of described the first seven segment numerical display tube, the 4th pin and the 5th pin latch respectively the 3rd digital display tube pin of chip with described decoding, the 4th digital display tube pin and the 5th digital display tube pin connect.
6. the main board failure display circuit of soaring as claimed in claim 2, is characterized in that, described indicating module comprises the 4th resistance R 4 and light emitting diode D1;
Described in being connected in series in, described the 4th resistance R 4 and described light emitting diode D1 soar between the 3V voltage output end and ground of mainboard BIOS chip.
7. the main board failure display circuit of soaring as claimed in claim 2, is characterized in that, described filtration module comprises:
The second capacitor C 2, the 3rd capacitor C 3 and the 4th capacitor C 4;
Described the second capacitor C 2 and described the 3rd capacitor C 3 and described the 4th capacitor C 4 are connected in parallel between the voltage output end and ground of described golden finger connector.
8. the main board failure display card of soaring, is characterized in that, described in the main board failure display card of soaring comprise the main board failure display circuit of soaring as described in as arbitrary in claim 1-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320686337.3U CN203520383U (en) | 2013-10-31 | 2013-10-31 | Fitec mainboard fault display circuit and display card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320686337.3U CN203520383U (en) | 2013-10-31 | 2013-10-31 | Fitec mainboard fault display circuit and display card |
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| Publication Number | Publication Date |
|---|---|
| CN203520383U true CN203520383U (en) | 2014-04-02 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320686337.3U Expired - Lifetime CN203520383U (en) | 2013-10-31 | 2013-10-31 | Fitec mainboard fault display circuit and display card |
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| Country | Link |
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| CN (1) | CN203520383U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104155597A (en) * | 2014-07-11 | 2014-11-19 | 苏州市职业大学 | Fault detector for computer main board |
| CN104200756A (en) * | 2014-09-18 | 2014-12-10 | 浪潮电子信息产业股份有限公司 | Design method of Debug indicator lamp capable of saving mainboard space |
-
2013
- 2013-10-31 CN CN201320686337.3U patent/CN203520383U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104155597A (en) * | 2014-07-11 | 2014-11-19 | 苏州市职业大学 | Fault detector for computer main board |
| CN104200756A (en) * | 2014-09-18 | 2014-12-10 | 浪潮电子信息产业股份有限公司 | Design method of Debug indicator lamp capable of saving mainboard space |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 518057 computer building of the Great Wall, Nanshan District science and Technology Park, Shenzhen, Guangdong Patentee after: CHINA GREAT WALL TECHNOLOGY GROUP Co.,Ltd. Address before: 518057 computer building of the Great Wall, Nanshan District science and Technology Park, Shenzhen, Guangdong Patentee before: CHINA GREATWALL COMPUTER SHENZHEN Co.,Ltd. |
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| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20210728 Address after: 300450 building 7, Binhai science and Technology Park, optoelectronics group, No. 335, Jinjiang Road, Tanggu marine science and Technology Park, Binhai New Area, Tianjin Patentee after: Tianjin Changcheng computer system Co.,Ltd. Address before: 518057 computer building of the Great Wall, Nanshan District science and Technology Park, Shenzhen, Guangdong Patentee before: China Great Wall Technology Group Co.,Ltd. |
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| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140402 |