CN202710685U - Capacitive screen integration testing circuit - Google Patents

Capacitive screen integration testing circuit Download PDF

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Publication number
CN202710685U
CN202710685U CN 201220379403 CN201220379403U CN202710685U CN 202710685 U CN202710685 U CN 202710685U CN 201220379403 CN201220379403 CN 201220379403 CN 201220379403 U CN201220379403 U CN 201220379403U CN 202710685 U CN202710685 U CN 202710685U
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China
Prior art keywords
control chip
chip
ctp
usb
firmware
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Expired - Fee Related
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CN 201220379403
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Chinese (zh)
Inventor
赵蓓
陈建忠
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Jiangxi Lianchuang Electronic Co Ltd
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Priority to CN 201220379403 priority Critical patent/CN202710685U/en
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Abstract

The utility model discloses a capacitive screen integration testing circuit. The capacitive screen integration testing circuit comprises a main control chip, a USB-serial port chip, a dial switch, and a switch board. The capacitive screen integration testing circuit is characterized in that an output terminal of the main control chip is respectively connected to input terminals of the USB-serial port communication chip and the dial switch, the main control chip is connected with a capacitive touch screen through the switch board, an output terminal of the USB-serial port communication chip is connected to an input terminal of a computer serial communication port, and the computer serial communication port is connected with a testing software. The capacitive screen integration testing circuit only uses one circuit board device, designs a software algorithm in a firmware of a CTP to be used in cooperation with the firmware, can realize the connecting with CTPs of different interfaces by using just one circuit board device and just one firmware in the research and debug phase, the production testing phase, and the reworking phase of the CTPS, and can carry out the data analysis testing work of different kinds.

Description

A kind of capacitance plate integration test circuit
Technical field
The utility model relates to the capacitance plate measuring technology, particularly a kind of capacitance plate integration test circuit.
Background technology
Research and development and the measurement method in the production run of capacitance plate are usually as follows at present:
(1) in R﹠D process: the testing cassete that normal operation main control chip merchant provides is analyzed and tuning parameter the performance of capacitance plate, and need the CTP(capacitance plate this moment) the control chip burning can outwards export every Sensor(sensitive element) Raw-data(original capacitance influence value) firmware of data.
(2) in process of production: the semi-manufacture to FPCA (flexible print circuit board module) the supplied materials Function detection of CTP, ito glass/film supplied materials Function detection, after fitting detect, and this three link need to be to the Master control chip burning Raw-data firmware of CTP; And finally to the finished product detection of CTP module, need to be to the control chip burning Coordinate firmware of CTP.And need to use expensive professional test instrument.Produce like this line and need to carry out to the control chip of all CTP the action of twice tough burn-recording, both the wasting manpower and material resources caused again more defective products easily.
(3) delivery is to after the client: CTP is bad as occuring, and then still needs the Raw-data data of all Sensor to analyze poor prognostic cause, then must be more again burning can outwards export the firmware of the Raw-data data of every Sensor.
Each link firmware that will use is different like this, and required testing apparatus is also different, has increased cost, has reduced efficient, is unfavorable for cost control.
Existing method of testing, the firmware that each link will be used is different, and required testing apparatus is also different, has increased time cost, and human cost has reduced production efficiency.
The utility model content
Technical problem to be solved in the utility model is, design a kind of circuit board arrangement, and by a kind of software algorithm of design in firmware, both are used, and are implemented in research and development debug phase, production test stage, the stage of reprocessing of CTP, only use the circuit kit panel assembly, only use a kind of firmware, can carry out multiple different types of data analysis test job, thereby save equipment cost, save manpower and time cost, improve research and development and production efficiency.
For above-mentioned purpose, the technical solution adopted in the utility model is, a kind of capacitance plate integration test circuit, comprise: Master control chip, USB turn serial port chip, toggle switch, card extender, it is characterized in that, the output terminal of Master control chip connects respectively the input end that USB turns serial communication chip and toggle switch, Master control chip is connected with capacitive touch screen by card extender, USB turns the input end of the output terminal connection computer COM port of serial communication chip, and the computer COM port is connected with testing software.
The utility model adopts the circuit kit panel assembly, and in the firmware of CTP, designed a kind of software algorithm, both are used, can be implemented in research and development debug phase, production test stage, the stage of reprocessing of CTP, only use the circuit kit panel assembly, only use a kind of firmware, can connect the CTP of various distinct interfaces, carry out multiple different types of data analysis test job.Can save equipment cost, save manpower and time cost, improve research and development and production efficiency.
Description of drawings
Fig. 1 is systematic schematic diagram of the present utility model.
Fig. 2 is the workflow synoptic diagram of testing circuit board Master control chip.
Embodiment
Below in conjunction with drawings and Examples to the utility model with further specifying.Referring to Fig. 1, a kind of capacitance plate integration test circuit comprises: Master control chip (Control IC) 1, USB turn serial port communication chip (USB-to-Serial IC) 2, toggle switch (DIP Switch) 3, card extender 4; The output terminal of Master control chip 1 connects respectively the input end that USB turns serial communication chip 2 and toggle switch 3, Master control chip 1 is connected with capacitive touch screen 5 by card extender 4, USB turns the input end of the output terminal connection computer COM port 6 of serial communication chip 2, and computer COM port 6 is connected with testing software 7.
Master control chip (Control IC) 1: comprise the I2C communication module, the UART communication module; Can be used as I2C Master equipment, by the I2C communication interface, the control chip of CTP is carried out the read-write of data; Simultaneously, also can turn serial port chip with USB and carry out the UART communication.
USB turns serial port communication chip (USB-to-Serial IC) 2: Master control chip 1 has the UART communication module, and the RX port that it and USB turn serial port communication chip 2 communicates, and the data of reading from CTP is sent to USB turn serial port communication chip 2; USB turns serial port communication chip 2 and is sent on the computer by USB bundle of lines data, and can simulate a COM port, and computer can receive data from testing circuit board from this COM port.
Toggle switch (DIP Switch) 3: each dial-up of toggle switch 3 and Master control chip one independently the GPIO mouth be connected; Master control chip 1 is understood the open/close state of real-time scanning toggle switch 3, and notifies CTP to carry out the output of which kind of data layout according to the state of toggle switch 3.
Above Master control chip (Control IC) 1, USB turn serial port communication chip (USB-to-Serial IC) 2 and toggle switch (DIP Switch) 3 all designs on the same circuit board.
Card extender 4 is independently circuit boards, is mainly used in connecting the CTP interface of different model and different styles; The testing software of testing circuit board and CTP and PC end cooperatively interacts, and can realize the analytical test of several data.
The capacitance plate integrated test facility referring to Fig. 2, the steps include:
Step 201: circuit board is powered by USB, and after powering on, Master control chip 1 starts I2C communication module and UART communication module; Confirm with CTP can normal communication after, enter major cycle; In the major cycle, at first read the open/close state of toggle switch 3 each dial-up by the GPIO mouth that links to each other with toggle switch 3.
Step 202: 1 and 2 these two dial-up on the toggle switch 3 describe as example, and 2 dial-ups can represent 4 kinds of states, if more switching demand is arranged, can increase the dial-up number and expand.
Step 203,204: 4 kinds of open/close state combinations of corresponding 2 dial-ups, the agreed address (for example: address [0]) in the I2C register of CTP writes 0x00,0x01,0x02, one of them of these 4 numerical value of 0x03.
Step 205: Master control chip 1 can detect again writes whether success of register, if success then continue, otherwise would return to step 203,204.
Step 206:CTP receives toggle switch 3 state values that Master control chip 1 writes, and switches the kind of output data; Behind the CTP handover success, can change the level state of the interruption GPIO mouth that (draw high or drag down) link to each other with Master control chip 1, Master control chip 1 receives that the level of INT pin changes, and just can remove to read all valid data in the I2C register of CTP; Data of the every transmission of CTP are all by interrupting notifying Master control chip 1 to read, Master control chip 1 is before receiving interrupt notification, can not remove initiatively to read the I2C register of CTP, can guarantee that like this each data that Master control chip 1 is read all are the ready complete and correct data of CTP.
Step 207: because the state of toggle switch 3 is different, Master control chip 1 by I2C from the register read of CTP to data have following several may: singly refer to many finger touch point coordinates and gesture (207a), the Baseline data (207b) of all Sensor, the Diff Value Data (207c) of all Sensor, the Raw-data data (207d) of all Sensor.
Step 208: Master control chip 1 is read after the data, by the UART communication module, sends to I2C and turns serial port chip; After Master control chip (parts 1) is finished above step, enter next time working cycle.
Step 209:I2C turns serial port chip, and (parts 2 send to certain virtual serial PORT COM on the computer to data;
Step 210: then by the supporting debugging software receive data of making on the computer, and carry out further data statistics and analysis.
The utility model has adopted the FPC connector of 9 pins, also can adopt the FPC connector of other specifications.As a standard interface, external one group of Du Pont's line connects card extender with this FPC connector.
Be equipped with multiple common CTP interface on the card extender, can external nearly all style and the CTP of specification.Such design cooperates the flexible socket of Du Pont's line to connect again, can make this testing circuit board be applicable to the CTP of nearly all specification, does not need to be as in the past new testing circuit board of every money CTP design.Even some CTP has very special interface and can't directly use card extender, also can realize by simple wire jumper on card extender.Therefore, this cover testing circuit board has good versatility and expansibility.
The utility model need not use multiple hardwares equipment, only uses the circuit kit panel assembly can be implemented in research and development debug phase, the production test stage of capacitive touch screen, data acquisition and the test analysis in the stage of reprocessing.Do not need the firmware of burning different editions, only use a kind of firmware can satisfy the demand of different types of data layout output in research and development debug phase at capacitive touch screen, production test stage, the stage of reprocessing.Do not need for the CTP interface of different styles and specification and design different testing circuit boards.Yield after can realizing simultaneously FPCA Function detection, ito glass/film Function detection, FPC and ito glass/film adhered in the production phase detects TP module finished product Function detection.The utility model can be saved equipment cost, saves manpower and time cost, improves research and development and production efficiency.
Term explanation in the utility model:
CTP: capacitive touch screen.
ITO: indium tin oxide.
ITO glass/film: indium tin oxide glass or film (main material of capacitive touch screen).
Sensor a: inductive axis of capacitive touch screen.
The original capacitance influence value of every inductive axis of Raw-data:CTP.
The reference capacitance influence value of every inductive axis of Baseline:CTP when stablizing and not being touched.
The difference of the reference value of the influence value of every inductive axis of Diff:CTP when being touched when not being touched.
Firmware: firmware, the program code of burning in the CTP control chip.
Raw-data firmware: the firmware that can outwards export the original sensed data of every inductive axis.
Coordinate firmware: the firmware that can outwards export the finger touch point coordinate data.
Control IC: Master control chip.
USB-to-Serial IC:USB turns the serial communication chip.
DIP Switch: toggle switch.
FPC: flexible printed circuit board.
FPCA: flexible printed circuit board module.
INT: interrupt general input/output port.
Gordian technique of the present utility model is:
1. utilize the switching of toggle switch, the output that notice CTP switches different data format.
2. the design of card extender.
3. circuit board can carry out the I2C communication with CTP, also can carry out the UART data communication with CTP, also can be without Master control chip and the UART data of CTP are directly outputed on the computer, also can be CTP burning Firmware.
4. the handoff algorithms that different data format is exported among the Firmware of CTP.
What more than enumerate only is a specific embodiment of the present utility model.Obviously, the utility model is not limited to above embodiment, and all distortion that those of ordinary skill in the art can directly derive or associate from the disclosed content of the utility model all should be thought the claimed scope of the utility model.

Claims (1)

1. capacitance plate integration test circuit, comprise: Master control chip, USB turn serial port chip, toggle switch, card extender, it is characterized in that, the output terminal of Master control chip connects respectively the input end that USB turns serial communication chip and toggle switch, Master control chip is connected with capacitive touch screen by card extender, USB turns the input end of the output terminal connection computer COM port of serial communication chip, and the computer COM port is connected with testing software.
CN 201220379403 2012-08-02 2012-08-02 Capacitive screen integration testing circuit Expired - Fee Related CN202710685U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201220379403 CN202710685U (en) 2012-08-02 2012-08-02 Capacitive screen integration testing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201220379403 CN202710685U (en) 2012-08-02 2012-08-02 Capacitive screen integration testing circuit

Publications (1)

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CN202710685U true CN202710685U (en) 2013-01-30

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106249130A (en) * 2016-08-30 2016-12-21 欧朗电子科技有限公司 The reading fuse bit test device of Intelligent watermeter
CN110111710A (en) * 2019-04-29 2019-08-09 深圳思凯测试技术有限公司 Display screen test method, device, equipment and computer readable storage medium

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106249130A (en) * 2016-08-30 2016-12-21 欧朗电子科技有限公司 The reading fuse bit test device of Intelligent watermeter
CN110111710A (en) * 2019-04-29 2019-08-09 深圳思凯测试技术有限公司 Display screen test method, device, equipment and computer readable storage medium

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C14 Grant of patent or utility model
GR01 Patent grant
CP01 Change in the name or title of a patent holder

Address after: 330096 Nanchang high tech Development Zone, Jingdong Road, No. 1699, No.

Patentee after: JIANGXI LIANCHUANG ELECTRONICS CO.,LTD.

Address before: 330096 Nanchang high tech Development Zone, Jingdong Road, No. 1699, No.

Patentee before: JIANGXI LIANCHUANG ELECTRONIC Co.,Ltd.

CP01 Change in the name or title of a patent holder
C56 Change in the name or address of the patentee
CP01 Change in the name or title of a patent holder

Address after: 330096 Nanchang high tech Development Zone, Jingdong Road, No. 1699, No.

Patentee after: JIANGXI LIANCHUANG ELECTRONIC Co.,Ltd.

Address before: 330096 Nanchang high tech Development Zone, Jingdong Road, No. 1699, No.

Patentee before: JIANGXI LIANCHUANG ELECTRONICS CO.,LTD.

CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20130130

Termination date: 20210802

CF01 Termination of patent right due to non-payment of annual fee