CN104051026A - SRAM (Static Random Access Memory) instantaneous dosage rate effect testing system and method with combination of full address and single address - Google Patents

Abstract

The invention relates to an SRAM (Static Random Access Memory) instantaneous dosage rate effect testing system and method with the combination of a full address and a single address. A microcontroller chip and an FPGA (Field Programmable Gate Array) are adopted to achieve state control on a tested SRAM, the tested SRAM can work in a single address testing state with a fixed address and work in a full address testing state with full address scanning, meanwhile, testing requirements on instantaneous waveform change of capture data and all address unit data reread are met, and disturbance waveform data at the data radiation moment of a memory unit, the number of all SRAM turning units and the distribution of logic addresses of the units can be obtained. The system supports testing on an SRAM of 8 bit width, 16 bit width or 32 bit width, user-definable voltage grade driving within 5V is provided, and testing requirements on various SRAMs of different bit widths, capacities and voltage grades can be met.

Description

In conjunction with full address and single address SRAM prompt dose rate effect test macro and method

Technical field

The invention belongs to electronic devices and components radiation effect test macro, be specifically related to one and be applicable to SRAM static RAM, combination full address and single address SRAM prompt dose rate effect test macro and the method for the test of Static Random Access Memory prompt dose rate effect.

Background technology

SRAM is one of core devices of electronic system.In practical application, SRAM may meet with transient ionizing radiation environment, produces prompt dose rate effect, and the dose rate effect of SRAM directly affects the radiation resistance of electronic system.SRAM radiation effect measuring technology is correctly to evaluate the gordian technique of its capability of resistance to radiation, its radiation effect rule of scientific research, significant to radiation resistance examination, the radiation tolerance design of SRAM.

SRAM prompt dose rate effect is carried out to a large amount of theories and experimental work abroad, aspect experimental measurement method, external measuring method is generally that after carrying out irradiation, full address is tested, write storage content in predose full address, keep powering state, carry out irradiation, after irradiation, the storage content in all addresses is scanned, measure upset effect, monitor the source current of SRAM simultaneously, measure latch-up.

At home, carrying out SRAM prompt dose rate effect measurement is generally by two kinds of methods, the full address method of testing that the one, SRAM applying unit is taked in the time of Performance Assessment, accesses computer system by storer, by judging whether computer operation situation determine memory overturns.The subject matter of the method is: can not conclude that computer operation mistake is due to storer upset or because computer chip or other parts cause; Can not determine memory be instantaneous upset or forever upset; When the instantaneous upset of storer, can not provide flip-flop transition and the upturned position of storer; Can not form pervasive Experimental Standardization, experimental result does not have directive significance to manufacturer.The method that SRAM production unit is taked is single-address method of testing, it is predose data writing in certain address, when irradiation, measure the storage content of all storage unit in this address or partial memory cell in the response of irradiation moment, this method is mainly measured upset effect and the disturbance effect of storage unit.The subject matter of this method is: in SRAM, the radiometric response of some addresses differs and represents surely the radiation effect of whole storer; Can not provide the regularity of distribution of full address upset; Can not find out effect sensitizing range, to instruct manufacturer to carry out specific aim reinforcing.

Summary of the invention

The technical matters solving

For fear of the deficiencies in the prior art part, the present invention proposes a kind of in conjunction with full address and single address SRAM prompt dose rate effect test macro and method, can test the storage unit upset situation within the scope of SRAM full address, can test again single-address memory cell data at the instantaneous radiometric response of irradiation, successfully realize the combination of full address test and single-address test.

Technical scheme

A kind of in conjunction with full address and single address SRAM prompt dose rate effect test macro, it is characterized in that comprising host computer 1, test board 2, oscillograph 3, stabilized voltage supply 4, irradiation plate 5; Host computer 1 is by USB connecting line connecting test plate 2, and test board shields winding displacement 2 by length and connects irradiation plate 5; The output of irradiation plate 5 connects oscillograph 3 by long coaxial shielded cable, and stabilized voltage supply 4 connects irradiation plate 5 by long coaxial shielded cable; Described host computer, test board and oscillograph are placed in shielding test; Described irradiation plate 5 is placed between irradiation.

Described test board comprises microcontroller chip and FPGA; Be connected by Slave fifo interface with FPGA; FPGA receives from microcontroller data or the instruction that host computer sends, and according to instruction, the tested SRAM on irradiation plate is carried out to corresponding read-write operation and state control, and by FPGA, the operation of microcontroller is returned to test data to host computer.

Described coaxial shielded cable is 50 meters of long coaxial shielded cables.

Described long shielding winding displacement is 50 meters long shielding winding displacements.

A method that adopts described system to measure, is characterized in that step is as follows:

Step 1: the tested SRAM on irradiation plate is powered up, measure source current;

Step 2: write 55H with full address measuring unit in the each storage unit of SRAM, again the content of all storage unit is read out, the read-write capability of guaranteeing SRAM is normal, and the state that afterwards address wire is fixed on to 10101010101, SRAM is set to " read states ";

Step 3: utilize oscillograph to measure the data in address 10101010101, record and preserve measured value, this is storage unit predose storage content;

Step 4: carry out irradiation, the variation of the storage content when recording and preserving irradiation in Unit 10101010101, this irradiation moment effect signal that is this unit storage content;

Step 5: measure the source current of SRAM, as source current does not change, again trigger oscillograph, measure and preserve the storage content in Unit 10101010101, this is the storage content after this unit irradiation; Utilize full address measuring unit to carry out full address scanning to SRAM, measure the storage content in all addresses; Measure again the read-write capability of SRAM; SRAM powers up again, measures read-write capability;

If the source current of SRAM increases after irradiation, and do not recover in official hour, SRAM powers up again, measures source current and read-write capability.

Beneficial effect

The one that the present invention proposes in conjunction with full address and single address SRAM prompt dose rate effect test macro and method advantage is:

1, the present invention has utilized microcontroller chip and FPGA to realize the state control to tested SRAM, make tested SRAM both can be operated in the fixing single-address test mode in address, can be operated in again the full address test mode of full address scanning, meet the testing requirement of all address location data of capture-data transient change waveform and retaking of a year or grade simultaneously, can provide the instantaneous disturbance waveform data of memory cell data radiation, whole SRAM roll-over unit quantity and logical address thereof and distribute.

2, the present invention has designed level shifting circuit for driving tested SRAM, can realize the test of 50 meters of long distances, can make test board away from irradiation zone, avoid transient ionizing radiation and magnetic-pulse induced electricity thereof to introduce strongly disturbing impact, thereby ensure test reliability.

3, the present invention supports the test of 8 bit wides, 16 bit wides and 32 bit wide SRAM, provides in 5V and can customize electric pressure driving, can meet the test request of the various SRAM of different bit wides, capacity, electric pressure.

Brief description of the drawings

Fig. 1, test system hardware form

Fig. 2, test plate structure composition

Pin is controlled in Fig. 3, FPGA output

Fig. 4, level shifting circuit form

Fig. 5, SRAM prompt dose rate effect testing process

Embodiment

Now in conjunction with the embodiments, the invention will be further described for accompanying drawing:

The present embodiment ingredient comprises host computer 1, test board 2, oscillograph 3, desk-top stabilized voltage supply 4, irradiation plate 5, and wherein host computer, test board, oscillograph are positioned between shielding test, and irradiation plate is positioned between irradiation.

Host computer 1 is connected, carries out instruction issuing and data transmission with test board 2 by USB connecting line 6, test board 2 is connected with irradiation plate 5, the tested SRAM on irradiation plate 5 is carried out to read-write operation and state control by the shielding winding displacement 7 of 50 meters long; Desk-top stabilized voltage supply 4 is powered to the tested SRAM on irradiation plate 5 by the coaxial shielded cable 8 of 50 meters long, and oscillograph 3 is connected to FPDP, the capture-data waveform of irradiation plate 5 by the coaxial shielded cable 9 of 50 meters long.

Test board chief component comprises microcontroller chip, FPGA field programmable gate array, Field Programmable Gate Array, FPGA receives from microcontroller data or the instruction that host computer sends, according to instruction, the tested SRAM on irradiation plate is carried out to corresponding read-write operation and state control, and by FPGA, the operation of microcontroller is returned to test data to host computer.

FPGA drives the tested SRAM on irradiation plate by level shifting circuit, level shifting circuit under different voltage bias drive different electric pressures tested SRAM, realize the test to different electric pressure SRAM, level shifting circuit improves the driving force of FPGA, the long distance that realizes 50 meters drives.

Under single-address test mode, FPGA output signal makes tested SRAM under the read states that sheet selects effectively, address is fixing, and the storage content that this fixed address is corresponding outputs to oscillograph test lead by FPDP; Under the test mode of full address, FPGA is to tested SRAM output read operation clock signal, the all address locations of sequential scanning, are uploaded to host computer by the storage data of reading back by microcontroller chip and by host computer processing obtain overturning figure place and counterlogic address thereof.

Test macro data line bit wide 32bit, address wire bit wide 24bit, chip select line bit wide 8bit, supports the test of 8,16 and 32 SRAM, the highest 32 bit wides or the 32 128Mbit capacity 8 bit wide SRAM on-line testing simultaneously of supporting 8 512Mbit capacity.

Test board functional description and its implementation:

Test board is that test macro is realized the core component that full address test, single-address test and test mode are switched, and its major function is realized by a slice microcontroller and a slice FPGA, as shown in Figure 2.That in invention, microcontroller adopts is the EZ-USB FX2 family chip CY7C68013A of Cypress company, and that FPGA adopts is the Spartan-3 of Xilinx company family chip XC3S400.Microcontroller and host computer carry out data transmission and command reception by usb communication D+ and D-signal, are connected by Slave fifo interface with FPGA.The inner integrated USB transceiver of microcontroller is connected to D+ and the D-of usb bus; Serial interface engine SIE carries out decoding, coding, error correcting and position and fills, the required signal level of conversion USB; Finally, transmit and receive data from USB interface.Microcontroller in invention has adopted Slave

FIFO mode of operation, the FIFO of microcontroller inside, by outside primary controller in the present invention for FPGA controls, makes FPGA to receive or to send data from microcontroller.

Microcontroller is after reset, and its I/O pin configuration is in " port " pattern, instead of Slave fifo mode.For being Slave fifo mode by Pin locations, the IFCFG1:0 of IFCONFIG register is set to 11, Slave fifo interface pin and is considered to the FPGA of external piloting control device processed in inventing.Fpga logic connects FIFO through 16 bit data bus FD, and this data bus is two-way, can be by SLOE pin control output.FIFOADR1:0 pin selects in 4 FIFO to be connected with FD bus.Under asynchronous system IFCONFIG.3=1, SLRD and SLWR are read/write gating signals.Under method of synchronization IFCONFIG.3=0, SLRD and SLWR are as the enable signal of IFCLK clock pin.By the control to Slave FIFO read-write, FPGA receives or sends data from host computer.

FPGA indoor design Data Analysis circuit module, the data that receive of judgement are instruction or general data.While receiving host computer instruction, FPGA analysis instruction and make inner state machine enter corresponding duty as write SRAM, read SRAM, that SRAM sheet is selected is invalid etc., and related register is configured and comprises address register, data register etc., finally under the control of state machine, export control signal at FPGA output pin according to the SRAM time sequential routine, realize the reading and writing to SRAM and go to enable.While receiving general data, FPGA is write internal data register, waits for and writing in SRAM.

As shown in Figure 3, FPGA output mainly comprises chip selection signal SRAM_CS0～SRAM_CS7, data-signal SRAM_D0～SRAM_D31, address signal SRAM_A0～SRAM_A23 for controlling the signal of SRAM operation, read to enable SRAM_OE, write and enable SRAM_WE, exports corresponding signal realize the operation to SRAM on these pins according to the SRAM time sequential routine.

When host computer carries out single-address test to the test instruction of microcontroller transmission single-address as the 0x317H address location data to No. 3 SRAM, first FPGA parses the information such as device number, address location 0x317H from instruction, then SRAM_CS3 is set low, other chip selection signals set high, make SRAM_A23～SRAM_A0 output 0x317H, SRAM_OE set low, SRAM_WE sets high, now the data bus port of SRAM is exported this device assigned address cell data, and is gathered by oscillograph.

When host computer sends full address test instruction and reads to test as No. 3 SRAM carried out to full address to microcontroller, first FPGA parses device number from instruction, the information such as address realm, then SRAM_CS3 is set low, other chip selection signals set high, SRAM_OE sets low, SRAM_WE sets high, carry out full address scanning at address port simultaneously, start order from lowest order address and be incremented to highest addresses, in scanning process from FPDP readback data and write readback data by the Slave fifo interface to microcontroller and realize test data returning to host computer, thereby complete full address test.

Level shifting circuit

In order to adapt to testing requirement and the requirement of 50 meters of long line driving forces of different electric pressure SRAM, design level shifting circuit.As shown in Figure 4, adopted 9 MAX30028 channel levels conversion chips that the data transmission capabilities between FPGA3.3V and tested SRAM multi-voltage grade is provided.This circuit can provide the bidirectional data transfers speed of 20Mbps, the self-defined voltage data transmission from 1.2V to 5.5V, makes system possess the power of test to different electric pressure SRAM.

SRAM prompt dose rate effect testing process

[1] in the data that write in predose SRAM and single-address test, memory address chooses

Predose writes the data at " 0 " and " 1 " interval in all storage unit of SRAM, is generally 55H or AAH.If there is the priori test figure of SRAM, select a certain address in the lower region of radiation damage threshold value, carry out single-address test; If there is no the priori test figure of SRAM, can choose arbitrarily an address, carry out single-address test.

The content that selection writes is 0101010155H, and selecting the address of single-address test is 10101010101.

[2] experimental procedure

A) power up to SRAM, measure source current;

B) in the each storage unit of SRAM, write 55H with full address measuring unit, again the content of all storage unit is read out, the read-write capability of guaranteeing SRAM is normal, and the state that afterwards address wire is fixed on to 10101010101, SRAM is set to " read states ";

C) utilize oscillograph to measure the data in address 10101010101, record and preserve measured value, this is storage unit predose storage content;

D) carry out irradiation, the variation of the storage content when recording and preserving irradiation in Unit 10101010101, this irradiation moment effect signal that is this unit storage content;

E) source current of measurement SRAM, as source current does not change, triggers oscillograph again, measures and preserve the storage content in Unit 10101010101, and this is the storage content after this unit irradiation; Utilize full address measuring unit to carry out full address scanning to SRAM, measure the storage content in all addresses; Measure again the read-write capability of SRAM; SRAM powers up again, measures read-write capability.

If the source current of SRAM increases after irradiation, and do not recover in official hour, SRAM powers up again, measures source current and read-write capability.

[3] Data Processing in Experiment

After a irradiation, source current is not significantly increased, and full address is not stored content in measuring and changed, and after irradiation, read-write capability is normal, and radiation effect is disturbance, and the disturbance time can extract from single-address measurement data;

After b irradiation, source current is not significantly increased, and full address has storage content to change in measuring, and after irradiation, read-write capability is normal, and radiation effect is upset, and upset number obtains from the measurement result of full address;

After c irradiation, source current obviously increases, and again powers up rear read-write capability and source current and recovers normal, and radiation effect is breech lock;

After d irradiation, source current obviously increases, and again powers up rear read-write capability undesired, and it is normal or still undesired that source current recovers, and radiation effect is for burning.

Claims (5)

1. in conjunction with full address and a single address SRAM prompt dose rate effect test macro, it is characterized in that comprising host computer (1), test board (2), oscillograph (3), stabilized voltage supply (4), irradiation plate (5); Host computer (1) is by USB connecting line connecting test plate (2), and test board shields winding displacement (2) by length and connects irradiation plate (5); The output of irradiation plate (5) connects oscillograph (3) by long coaxial shielded cable, and stabilized voltage supply (4) connects irradiation plate (5) by long coaxial shielded cable; Described host computer, test board and oscillograph are placed in shielding test; Described irradiation plate (5) is placed between irradiation.

2. according to claim 1 in conjunction with full address and single address SRAM prompt dose rate effect test macro, it is characterized in that: described test board comprises microcontroller chip and FPGA; Be connected by Slave fifo interface with FPGA; FPGA receives from microcontroller data or the instruction that host computer sends, and according to instruction, the tested SRAM on irradiation plate is carried out to corresponding read-write operation and state control, and by FPGA, the operation of microcontroller is returned to test data to host computer.

3. according to claim 1 in conjunction with full address and single address SRAM prompt dose rate effect test macro, it is characterized in that: described coaxial shielded cable is 50 meters of long coaxial shielded cables.

4. according to claim 1 in conjunction with full address and single address SRAM prompt dose rate effect test macro, it is characterized in that: described long shielding winding displacement is 50 meters long shielding winding displacements.

5. adopt the method that any one system is measured described in claim 1～4, it is characterized in that step is as follows:

Step 1: the tested SRAM on irradiation plate is powered up, measure source current;

Step 2: write 55H with full address measuring unit in the each storage unit of SRAM, again the content of all storage unit is read out, the read-write capability of guaranteeing SRAM is normal, and the state that afterwards address wire is fixed on to 10101010101, SRAM is set to " read states ";

Step 3: utilize oscillograph to measure the data in address 10101010101, record and preserve measured value, this is storage unit predose storage content;

Step 4: carry out irradiation, the variation of the storage content when recording and preserving irradiation in Unit 10101010101, this irradiation moment effect signal that is this unit storage content;

Step 5: measure the source current of SRAM, as source current does not change, again trigger oscillograph, measure and preserve the storage content in Unit 10101010101, this is the storage content after this unit irradiation; Utilize full address measuring unit to carry out full address scanning to SRAM, measure the storage content in all addresses; Measure again the read-write capability of SRAM; SRAM powers up again, measures read-write capability;

If the source current of SRAM increases after irradiation, and do not recover in official hour, SRAM powers up again, measures source current and read-write capability.