CN102508749B

CN102508749B - Method for testing dual inline memory modules (DIMM)

Info

Publication number: CN102508749B
Application number: CN 201110318440
Authority: CN
Inventors: 姜凯; 于治楼; 沈忱
Original assignee: Inspur Group Co Ltd
Current assignee: Yantai Inspur Cloud Computing Co ltd
Priority date: 2011-10-19
Filing date: 2011-10-19
Publication date: 2013-08-14
Anticipated expiration: 2031-10-19
Also published as: CN102508749A

Abstract

The invention provides a method for testing dual inline memory modules (DIMM). The method comprises the following steps of: connecting a field programmable gate array (FPGA) chip with a control chip, a high-speed interface and DIMM logic interfaces of a plurality of channels, wherein a DIMM verification system consists of the FPGA chip, the control chip, the high-speed interface and the DIMM logic interfaces, and an electronic disk is formed in the verification system; sending a read-write instruction of a master equipment end to the system by virtue of the high-speed interface; and resolving the instruction by the control chip, and reading and writing the DIMM to be tested by controlling a DIMM logic so as to implement the DIMM test. Compared with the prior art, the method for testing the DIMM is high in test speed, high in test efficiency, high in read-write speed and high in popularization and use value.

Description

A kind of method that realizes the DIMM test

Technical field

The present invention relates to a kind of microelectronics technology, specifically a kind of method of testing that improves the testing efficiency of DIMM.

Background technology

DIMM(Dual Inline Memory Modules, dual inline type memory module), i.e. the common memory bar of saying.Specifically be divided into UDIMM(Unbuffered DIMM, do not have buffering dual inline type memory module, be generally used for common commercial/family's main frame) and RDIMM(Registered DIMM, register dual inline type memory module is generally used for server).

Common memory test is by computer motherboard, utilizes special software to carry out readwrite tests.Be subject to general computer motherboard and do not support RDIMM, the server master board price is high, while dimm socket limited amount on mainboard, and also special test software test speed is slow partially.This has brought inconvenience for the new-product development of DIMM.

Summary of the invention

Technical assignment of the present invention is in the deficiencies in the prior art, and the method for testing of the testing efficiency of a kind of DIMM of raising is provided.

Technical scheme of the present invention realizes in the following manner, this a kind of method that realizes the DIMM test, and its specific implementation step is:

The dual inline type memory module DIMM logic interfacing that at first the on-site programmable gate array FPGA chip is connected control chip, high-speed interface and a plurality of passages, form the DIMM verification system by fpga chip, control chip, high-speed interface, DIMM logic interfacing, this verification system forms an electric board; Send to system by the read write command of high-speed interface with the main equipment end then; Be responsible for the instruction parsing and come DIMM to be tested is carried out read-write operation realization DIMM test by control DIMM logic by control chip at last.

Described DIMM logic interfacing comprises UDIMM logic interfacing and RDIMM logic interfacing.

Described high-speed interface refers to the SATA interface.

Described control chip refers to the ARM chip.

Described fpga chip inside comprises that ahb bus, DIMM select to store on logic, clock/control signal buffering logic, DIMM steering logic, bus matrix, DMA, SATA steering logic and the sheet, after system powers on, system is according to the DIMM signal, select the moderator control selector switch of logic to select the path of DIMM control and clock signal by DIMM: as then directly inserting the DIMM steering logic for UDIMM, as be that RDIMM then passes through clock/control signal and cushions logic access DIMM steering logic.

Described bus matrix provides the independent bus line of each passage for the DIMM of a plurality of passages.

Described DMA supports to read and write at a high speed data transmission.

The beneficial effect that the present invention compared with prior art produces is:

A kind of method of testing that improves the testing efficiency of DIMM of the present invention is utilized the FPGA flexibility of programming, realizes the DIMM logic, and possesses the UDIMM of support and RDIMM, and test speed is fast, and the testing efficiency height can be read and write at a high speed, has good value for applications.

Description of drawings

Accompanying drawing 1 is the structured flowchart of implementation method of the present invention.

Accompanying drawing 2 is structured flowcharts of DIMM logic in the fpga chip of the present invention.

Embodiment

Below in conjunction with accompanying drawing a kind of method of DIMM test that realizes provided by the present invention is done following detailed description the in detail.

For improving the DIMM testing efficiency, realize telling read-write.As shown in Figure 1, provide a kind of method of the DIMM of realization test now, its specific implementation step is:

The dual inline type memory module DIMM logic interfacing that at first the on-site programmable gate array FPGA chip is connected control chip, high-speed interface and a plurality of passages, form the DIMM verification system by fpga chip, control chip, high-speed interface, DIMM logic interfacing, this verification system forms an electric board; Send to system by the read write command of high-speed interface with the main equipment end then; Be responsible for the instruction parsing and come DIMM to be tested is carried out read-write operation realization DIMM test by control DIMM logic by control chip at last; Described DIMM logic interfacing comprises UDIMM logic interfacing and RDIMM logic interfacing; Described high-speed interface refers to the SATA interface; Described control chip refers to the ARM chip.

As shown in Figure 2, described fpga chip inside comprises that ahb bus, DIMM select to store on logic, clock/control signal buffering logic, DIMM steering logic, bus matrix, DMA, SATA steering logic and the sheet, after system powers on, system is according to the DIMM signal, select the moderator control selector switch of logic to select the path of DIMM control and clock signal by DIMM: as then directly inserting the DIMM steering logic for UDIMM, as be that RDIMM then passes through clock/control signal and cushions logic access DIMM steering logic; Described bus matrix provides the independent bus line of each passage for the DIMM of a plurality of passages; Described DMA supports to read and write at a high speed data transmission.

Because the fpga chip flexibility of programming realizes the DIMM logic, and possesses compatible UDIMM and RDIMM.

Adopt the ARM7 test chip with control chip below, the DIMM of 10 passages is example, does following detailed description:

Form the FPGA platform by fpga chip, ARM7 chip, SATA logic, DIMM logic, this platform forms an electric board, the Host end sends read write command by high-speed interface to system, and the ARM7 chip is responsible for the instruction parsing and is come DIMM to be tested is carried out read-write operation by control DIMM logic.

So just can reach RDIMM or the UDIMM of compatible 10 passages, and can read and write at a high speed by a test board, thus the testing efficiency of raising DIMM.

Except the described technical characterictic of instructions, be the known technology of those skilled in the art.

Claims

1. method that realizes DIMM test, it is characterized in that its specific implementation step is: the dual inline type memory module DIMM logic interfacing that at first the on-site programmable gate array FPGA chip is connected control chip, high-speed interface and a plurality of passages, form the DIMM verification system by fpga chip, control chip, high-speed interface, DIMM logic interfacing, this verification system forms an electric board; Send to system by the read write command of high-speed interface with the main equipment end then; Being responsible for the instruction parsing by control chip at last reaches by control DIMM logic to come DIMM to be tested is carried out read-write operation, realize the DIMM test, above-mentioned fpga chip inside comprises ahb bus, DIMM selects logic, clock/control signal buffering logic, the DIMM steering logic, bus matrix, DMA, store on SATA steering logic and the sheet, after system powers on, system is according to the DIMM signal, select the moderator control selector switch of logic to select the path of DIMM control and clock signal by DIMM: as then directly inserting the DIMM steering logic for UDIMM, as be that RDIMM then passes through clock/control signal and cushions logic access DIMM steering logic; Described bus matrix provides the independent bus line of each passage for the DIMM of a plurality of passages; Described DMA supports to read and write at a high speed data transmission.

2. a kind of method that realizes the DIMM test according to claim 1 is characterized in that described DIMM logic interfacing comprises UDIMM logic interfacing and RDIMM logic interfacing.

3. a kind of method that realizes the DIMM test according to claim 1 is characterized in that described high-speed interface refers to the SATA interface.

4. a kind of method that realizes the DIMM test according to claim 1 is characterized in that described control chip refers to the ARM chip.