CN1282098C - DIMM chip set controlling circuit - Google Patents
DIMM chip set controlling circuit Download PDFInfo
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- CN1282098C CN1282098C CN 200410064197 CN200410064197A CN1282098C CN 1282098 C CN1282098 C CN 1282098C CN 200410064197 CN200410064197 CN 200410064197 CN 200410064197 A CN200410064197 A CN 200410064197A CN 1282098 C CN1282098 C CN 1282098C
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Abstract
The present invention provides a control circuit which can use no-buffer dual in-Line memory modules (DIMM) in a system of a chip group which only supports registering DIMM. The present invention is arranged on a host machine board which at least comprises a central processor, a chip group for supporting registering DIMM, a memory module slot and a basic input/output system. The control circuit comprises a buffer module and a control module, and selects different address signals and control signals to be outputted to the memory module slot under the control of identification signals so as to meet the different usages of the DIMM. The present invention is flexible and convenient in application and low in use cost.
Description
The application is for application number is 00123784.5, the applying date is on September 6th, 2000, denomination of invention is divided an application for the application of " DIMM chip group control circuit ".
Technical field
The present invention relates to a kind of DIMM chip group control circuit, particularly a kind ofly in the system of the chipset of only supporting to deposit (registered) dual inline memory modules, use the control circuit that does not have the buffering dual inline memory modules.
Background technology
Current in personal workstation or the computer system at servomechanism, its primary memory generally is to adopt the memory module with industrial standard architectures.These memory modules generally comprise a plurality of dynamic RAM (Dynamic Random Access Memory, DRAM) chip, these dynamic RAM are to be fixed on the minitype circuit board, and this minitype circuit board can combine with memory module slot.The industrial standard modular structure comprise signle in-line memory module SIMM (Single In-Line Memory Module, SIMM) and dual inline memory modules DIMM (Dual In-Line Memory Module, DIMM).The PC primary memory is if use DIMM now, and be to use does not have buffering (unbuffered) DIMM more, but for the higher computer system of main memory capacity demand, is server system for example, and DIMM is deposited in then more use.
Figure 1 shows that the central processing unit in the existing common computer system connects the block diagram of no buffered DIMM.No buffered DIMM 113 comprises synchronous DRAM SDRAM (SynchronousDRAM, SDRAM) there are detection SPD (Serial PresenceDetect in module 115 and sequence, SPD) storer 117, SPD storer 117 is the relevant settings that are used for storing no buffered DIMM 113, comprising the sequential (timing) of SDRAM module 115.When system boot, (Basic Input Output System, what BIOS) (mark not in the drawings) can learn from SPD storer 117 that primary memory in the system uses is no buffered DIMM 113 to basic input/output BIOS.Central processing unit 101 is connected with chipset (chipset) 105 by Front Side Bus (front side bus) 103.And this chipset 105 is a chipset of only supporting no buffered DIMM.Chipset 105 is connected with memory module slot 119 by address bus (address bus) 107, control bus (control bus) 109 and data bus (databus) 111, is to be plugged on the memory module slot 119 and there is not buffered DIMM 113.No buffered DIMM more than 113 uses in the system of PC or workstation.Than the system of large memories, be servo-drive system for example if desired, then can use and deposit DIMM.
The central processing unit that Figure 2 shows that existing general computer system is connected with the block diagram of depositing DIMM.There is register DIMM 213 to comprise SDRAM 215, SPD storer 217, register module (registers) 219 and clock buffer (clock buffer) 221.SPD storer 217 is in order to the related setting of storage register 213, comprising the sequential of SDRAM 215.When system boot, by BIOS from SPD storer 217, the primary memory that can learn present use is for there being register DIMM213, and register module 219 and clock buffer 221 are to be used for driving the signal that (drive) and amplification (amplify) are imported, and outputs to SDRAM 215.Central processing unit 201 by Front Side Bus 203 with only support that deposit DIMM chipset 205 is connected.Only support that the chipset 205 of depositing DIMM is connected with memory module slot 223 with address bus 207, control bus 209 and data bus 211, be plugged on the memory module slot 223 and deposit DIMM 213.Wherein, the signal that transmitted of data bus 211 directly enters among the SDRAM215.And after the driving and amplification of the signal that address bus 207 and control bus 209 are produced through register module 219 and clock buffer 221, enter again among the SDRAM 215.
And deposit in the system of DIMM chipset 205 only supporting, can only use and deposit DIMM215.If when will not have buffered DIMM and insert the memory module slot of this computer system,, will cause the system can't operate as normal because it is different with the sequential of depositing DIMM not have buffered DIMM.Therefore, significant limitation is arranged in the use.And, in the system of servomechanism, the systems that use only support to deposit DIMM chipset 205 more.But because it is higher to deposit the cost of DIMM, if in each districts and cities' scope of system applies, can the lower no buffered DIMM of use cost.To help to reduce application cost.
Summary of the invention
The object of the present invention is to provide a kind of control circuit, make that the user not only can assign and deposit DIMM, also can select to use no buffered DIMM in the system of the chipset of only supporting to deposit DIMM.Like this,, can select to use that a kind of memory module according to its actual needs for the user, quite flexible and convenient, can also reduce cost.
The present invention proposes a kind of DIMM chip group control circuit, can use no buffered DIMM only supporting to deposit in the system of DIMM chipset, deposit one first address signal and one first control signal of the output of DIMM chipset in order to receive this support, this control circuit also receives in order to discern an identification signal of a DIMM type, this identification signal is from basic input/output, wherein this DIMM places a memory module slot, and this control circuit comprises:
One buffer module, in order to receiving this first address signal and first control signal respectively via an address bus and a control bus, and exportable one second letter location signal and one second control signal;
Wherein, this control circuit is under the control of this identification signal, and selection exports this first address signal and first control signal or this second address signal, second control signal to this memory module slot.
Described control circuit, wherein this buffer module also comprises a register module (registers) and a clock impact damper (clock buffer).
Described control circuit, wherein this support is deposited the DIMM chipset and is also exported a data-signal to this memory module slot.
Described control circuit, wherein this data-signal system exports this memory module slot to via a data bus.
Described control circuit, wherein when this DIMM be when depositing DIMM, will export this first address signal and first by the control of this identification signal and control signal to this memory module slot.Wherein, when this DIMM is a no buffered DIMM, will exports this second address signal and second by the control of this identification signal and control signal to this memory module slot.
Described control circuit, also comprise a control module, comprise a first input end, one second input end and a control input end, wherein this first input end is in order to receive this first address signal and first control signal, this second input end is in order to receive this second address signal and second control signal, this control input end is in order to receive this identification signal, this control module is under the control of this identification signal, and selection exports this first address signal and first control signal or this second address signal and second control to this memory module slot.
Described control circuit also comprises:
One channel module, in order to receive this first address signal and first control signal, this channel module more comprises one first control input end, and whether it exports this first address signal and this first with decision and control signal to this memory module slot in order to receive this identification signal;
Wherein, this buffer module also comprises one second control input end, and it is in order to receive this identification signal to determine that whether exporting one second address signal and one second controls signal to this memory module slot.
The present invention also proposes a kind of DIMM chip group control circuit, can use no buffered DIMM only supporting to deposit to provide in the system of DIMM chipset, and in order to be installed on the motherboard, wherein this motherboard comprises at least: a central processing unit; One supports to deposit the DIMM chipset, and it is connected with this central processing unit with a Front Side Bus, and via an address bus and a control bus, exports one first address signal and one first control signal respectively; One memory module slot, it is in order to combine with a biserial in-line memory module, and wherein, this DIMM includes a sequence and has the detection of stored device, and it is in order to store the pattern of this DIMM; And a basic input/output, it reads this sequence and has the pattern of this stored DIMM of detection of stored device and export an identification signal when start;
This control circuit comprises: a buffer module, receive this first address signal and first control signal respectively via an address bus and a control bus, and exportable one second address signal and one second control signal; Wherein, this control circuit is under the control of this identification signal, and selection exports this first address signal and first control signal or this second address signal and second control signal to this memory module slot.
Described control circuit, wherein this buffer module also comprises a register module and a clock impact damper.
Described control circuit, also comprise a control module, comprise a first input end, one second input end and a control input end, wherein this first input end is in order to receive this first address signal and first control signal, this second input end is in order to receive this second address signal and second control signal, this control input end is in order to receive this identification signal, this control module is under the control of this identification signal, and selection exports this first address signal and first control signal or this second address signal and second control signal to this memory module slot.
Described control circuit, wherein when this DIMM be when depositing DIMM, this identification signal is controlled this control module and is exported this first address signal and first and control signal to this memory module slot.
Described control circuit, wherein when this DIMM is a no buffered DIMM, this identification signal is controlled this control module and is exported this second address signal and second and control signal to this memory module slot.
Described control circuit, also comprise: a channel module, be used to receive this first address signal and first control signal, this channel module also comprises one first control input end, and whether it exports this first address signal and this first with decision and control signal to this memory module slot in order to receive this identification signal; Wherein, this buffer module also comprises one second control input end, and it is in order to receive this identification signal to determine that whether exporting one second address signal and one second controls signal to this memory module slot.
Described control circuit, wherein when this DIMM be when depositing DIMM, this identification signal is closed this buffer module and is controlled this channel module and export this first address signal and first and control signal to this memory module slot.
Described control circuit, wherein when this DIMM is a no buffered DIMM, this identification signal is closed this channel module and is controlled this buffer module and export this second address signal and second and control signal to this memory module slot.
The control circuit that uses no buffered DIMM in the system of the chipset of only supporting to have register DIMM proposed by the invention, its advantage person of being to use can select use register DIMM to be arranged or do not have buffered DIMM.Concerning the user, can consider to use the sort of DIMM according to the actual requirements like this, very flexible and convenient, and can reduce use cost.
Below in conjunction with accompanying drawing the control circuit that the present invention proposes is described in further detail.
Description of drawings
Fig. 1 is that the central processing unit of general computer system connects the block diagram of not having the buffering dual inline memory modules;
Fig. 2 connects the block diagram of depositing dual inline memory modules for the central processing unit of general computer system;
Fig. 3 is for only supporting to deposit the block diagram that the control circuit that can use no buffered DIMM is provided in the system of DIMM chipset in the embodiment of the invention one;
Fig. 4 is for only supporting to deposit the block diagram that the control circuit that can use no buffered DIMM is provided in the system of DIMM chipset in the embodiment of the invention two.
Embodiment
Shown in Figure 3 is a preferred embodiment of the present invention, and the block diagram of the control circuit that can use no buffered DIMM is provided in the system of the chipset of only supporting to deposit DIMM.According to shown in Figure 3, memory module slot 413 is in order to the position that allows dual inline memory modules DIMM 417 insert motherboards, and DIMM 417 can to deposit DIMM also can be no buffered DIMM.Central processing unit 401 is connected with only supporting the chipset 405 of depositing DIMM by Front Side Bus 403.And chipset 405 is exported the first address signal ADD1, the first control signal CTL1 and data-signal DATA respectively by address bus 407, control bus 409 and data bus 411.Wherein, only support that depositing DIMM chipset 405 is connected with memory module slot 413 through data bus 411, can directly receive data-signal DATA by memory module slot 413.
Control circuit of the present invention comprises channel module 435 and buffer module 430.The first above-mentioned address signal ADD1 and the first control signal CTL1 can directly be received by channel module 435, and whether decision wants open channel that signal is exported.In addition, the first address signal ADD1 and the first control signal CTL1 also can be received by buffer module 430 and be kept in, and export the second address signal ADD2 and the second control signal CTL2.And buffer module 430 comprises register module 431 and clock buffer 433.In channel module 435 and buffer module 430, all there are a control input end CTI and CT2 to be used for receiving basic input/output (Basic Input Output System respectively, BIOS) the identification signal REC of 415 outputs, channel module 435 and buffer module 433 are under the control of identification signal REC, whether select with first group of input signal ADD1, CTL1 or second group of output signal ADD2, CTL2 outputs to memory module slot 413.
Basic input/output 415 is electrically connected to the control input end CT1 and the CT2 of channel module 435 and buffer module 430.During because of system boot, there are the data that detect (SPD) storer in the sequence that BIOS 415 can read among the DIMM 417 that assigns on the memory module slot 413, belongs to no buffered DIMM or deposits DIMM so can learn the DIMM 417 that is inserted.Next, BIOS415 will export an identification signal REC to control input end CT1 and the CT2 of channel module 435 with buffer module 430.According to this identification signal, whether channel module 435 can determine to open to export the signal of the memory module that is fit to insertion with buffer module 430.So when the DIMM 417 that inserts is when depositing DIMM, channel module 435 will be opened, and the first address signal ADD1 and the first control signal CTL1 are outputed to memory module slot 413.If what the user inserted is no buffered DIMM, buffer module 430 will be opened, and will output to memory module slot 413 through the second address signal ADD2 and the second control signal CTL2 that deposits buffering.So, though what plug is no buffered DIMM, also can be synchronous with the sequential of only supporting to deposit DIMM chipset 405, system still can operate as normal.So utilize this control circuit, can reach in the system of the chipset 405 of only supporting to deposit DIMM, select to use and deposit DIMM or do not have buffered DIMM.
Shown in Figure 4 is a preferred embodiment of the present invention, the block diagram of the control circuit that can use no buffered DIMM is provided in the system of the chipset of only supporting to deposit DIMM, according to shown in Figure 4, memory module slot 313 is in order to the position that allows dual inline memory modules DIMM 317 insert motherboard, and DIMM 317 deposits DIMM or do not have buffered DIMM.Central processing unit 301 is connected with only supporting the chipset 305 of depositing DIMM by Front Side Bus 303.And chipset 305 is exported the first address signal ADD1, the first control signal CTL1 and data-signal DATA respectively through address bus 307, control bus 309 and data bus 311.Wherein, chipset 305 is connected with memory module slot 313 by data bus 311, can directly receive data-signal DATA by memory module slot 313.
Control circuit of the present invention comprises multichannel (multiplexing) device 335 and buffer module 330.And buffer module 330 comprises register module 331 and clock buffer 333.The first above-mentioned address signal ADD1 and the first control signal CLT1 can be received by the first input end RS1 of multichannel (multiplexing) device 335, and this is first group of input signal.In addition, the first address signal ADD1 and the first control signal CTL1 also can be received by buffer module 330, and export the second address signal ADD2 and the second control signal CTL2.Next second input end RS2 by multichannel (multiplexing) device receives the second address signal ADD2 and the second control signal CTL2, and this is second group of input signal.In addition, the control input end CT of multichannel (multiplexing) device 335 receives the identification signal REC of basic input/output BIOS 315 outputs, Port Multiplier 335 is under the control of identification signal REC, selection is with first group of input signal ADD1, CTL1 or second group of input signal ADD2, CTL2 outputs to memory module slot 313.
Basic input/output 315 is electrically connected to the control input end CT of multichannel (multiplexing) device 335.When system boot, there are the data of detection of stored device SPD in the sequence that BIOS 315 can read among the DIMM 317 that assigns on the memory module slot 313, is no buffered DIMM or deposits DIMM so can learn the DIMM317 that is inserted.Then, BIOS 315 will export the control input end CT of an identification signal REC to multichannel (multiplexing) device 335.And according to this identification signal, multichannel (multiplexing) device 335 can be exported the signal of the DIMM317 type that meets insertion.So when the DIMM317 that inserts is when depositing DIMM, multichannel (multiplexing) device 335 is about to the first address signal ADD1 and the first control signal CTL1 outputs to memory module slot 313.If what the user inserted is no buffered DIMM, multichannel (multiplexing) device 335 is about to the second address signal ADD2 and the second control signal CTL2 outputs to memory module slot 313.Like this, though what plug is no buffered DIMM, also can be synchronous with the sequential of the chipset 305 of only supporting to deposit DIMM, system still can operate as normal.So utilize this control circuit, can reach only supporting and deposit in the system of DIMM chipset 305, selecting to use has register DIMM or does not have buffered DIMM.
In sum; though the present invention discloses as above with preferred embodiment; yet; it is not in order to limit the present invention; any those of ordinary skill in the art, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations; what therefore, protection scope of the present invention should be defined with appended claim scope is as the criterion.
Claims (7)
1. DIMM chip group control circuit can use no buffered DIMM only supporting to deposit to provide in the system of DIMM chipset,, it is characterized in that this motherboard comprises at least in order to be installed on the motherboard:
One central processing unit;
One supports to deposit the DIMM chipset, and it is connected with this central processing unit with a Front Side Bus, and via an address bus and a control bus, exports one first address signal and one first control signal respectively;
One memory module slot, it is in order to combine with a biserial in-line memory module, and wherein, this DIMM includes a sequence and has the detection of stored device, and it is in order to store the pattern of this DIMM; And
One basic input/output, it reads this sequence and has the pattern of this stored DIMM of detection of stored device and export an identification signal when start;
This control circuit comprises:
One buffer module, it comprises a register module and a clock impact damper, this buffer module receives this first address signal and first control signal respectively via an address bus and a control bus, and exportable one second address signal and one second control signal;
Wherein, this control circuit is under the control of this identification signal, and selection exports this first address signal and first control signal or this second address signal and second control signal to this memory module slot.
2. control circuit as claimed in claim 1, it is characterized in that, also comprise a control module, comprise a first input end, one second input end and a control input end, wherein this first input end is in order to receive this first address signal and first control signal, this second input end is in order to receive this second address signal and second control signal, this control input end is in order to receive this identification signal, this control module is under the control of this identification signal, and selection exports this first address signal and first control signal or this second address signal and second control signal to this memory module slot.
3. control circuit as claimed in claim 2 is characterized in that, when this DIMM is when depositing DIMM, this identification signal is controlled this control module and exported this first address signal and first and control signal to this memory module slot.
4. control circuit as claimed in claim 2 is characterized in that, when this DIMM was a no buffered DIMM, this identification signal was controlled this control module and exported this second address signal and second and control signal to this memory module slot.
5. control circuit as claimed in claim 1 is characterized in that, also comprises:
One channel module, be used to receive this first address signal and first control signal, this channel module also comprises one first control input end, and whether it exports this first address signal and this first with decision and control signal to this memory module slot in order to receive this identification signal;
Wherein, this buffer module also comprises one second control input end, and it is in order to receive this identification signal to determine that whether exporting this second address signal and second controls signal to this memory module slot.
6. control circuit as claimed in claim 5 is characterized in that, when this DIMM is when depositing DIMM, this identification signal is closed this buffer module and controlled this channel module and export this first address signal and first and control signal to this memory module slot.
7. control circuit as claimed in claim 5 is characterized in that, when this DIMM was a no buffered DIMM, this identification signal was closed this channel module and controlled this buffer module and export this second address signal and second and control signal to this memory module slot.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410064197 CN1282098C (en) | 2000-09-06 | 2000-09-06 | DIMM chip set controlling circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410064197 CN1282098C (en) | 2000-09-06 | 2000-09-06 | DIMM chip set controlling circuit |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 00123784 Division CN1249589C (en) | 2000-09-06 | 2000-09-06 | DIMM chip group control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1591476A CN1591476A (en) | 2005-03-09 |
| CN1282098C true CN1282098C (en) | 2006-10-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200410064197 Expired - Lifetime CN1282098C (en) | 2000-09-06 | 2000-09-06 | DIMM chip set controlling circuit |
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| Country | Link |
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| CN (1) | CN1282098C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102289400B (en) * | 2011-09-05 | 2013-07-31 | 浪潮电子信息产业股份有限公司 | Method for increasing DIMM (Double Inline Memory Module) testing efficiency |
| CN102508749B (en) * | 2011-10-19 | 2013-08-14 | 浪潮集团有限公司 | Method for testing dual inline memory modules (DIMM) |
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- 2000-09-06 CN CN 200410064197 patent/CN1282098C/en not_active Expired - Lifetime
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| CN1591476A (en) | 2005-03-09 |
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