CN203053403U

CN203053403U - A single-FPGA-based position measuring and displaying device supporting multiple grating rulers

Info

Publication number: CN203053403U
Application number: CN 201220740389
Authority: CN
Inventors: 廖文高
Original assignee: Guangzhou Numerical Control Equipment Co Ltd
Current assignee: Guangzhou Numerical Control Equipment Co Ltd
Priority date: 2012-12-28
Filing date: 2012-12-28
Publication date: 2013-07-10
Anticipated expiration: 2022-12-28

Abstract

The utility model discloses a single-FPGA-based position measuring and displaying device supporting multiple grating rulers. The position measuring and displaying device comprises a PHY Ethernet module connected with an Ethernet through an Ethernet interface, a RS485 & 26LS32 module connected with multiple grating rulers through a grating ruler interface, a FPGA internally equipped with a soft core CPU, a RS485 & RS232 module, a LCD display module, a FLASH memory, and a SDRAM memory. The PHY Ethernet module, the RS485 & 26LS32 module, the RS485 & RS232 module, the LCD display module, the FLASH memory, and the SDRAM memory are connected with the FPGA. By using a grating ruler communication module in the FPGA and using high-precision absolute grating rulers, the position measuring and displaying device achieves high-synchronization, high-speed, and high-precision communication of the multiple grating rulers.

Description

Support the position of a plurality of grating chis to survey based on monolithic FPGA and show device

Technical field

The utility model relates to a kind of position and surveys apparent device, and especially a kind of apparent device of position survey of supporting a plurality of grating chis based on monolithic FPGA belongs to motion control and field of measuring technique.

Background technology

At present, in motion control and field of measuring technique, traditional three-dimensional or the synchronism of multidimensional measure and precision aspect are all poor, and transmitted data rates is slow.Traditional position is surveyed apparent device and is generally adopted MCU to communicate or pulse collection, but the peripheral communication interface limited amount that MCU carries and not necessarily meet the communication protocol of grating chi, the peripheral hardware pulse collection interface quantity that MCU carries is also limited, generally has only 2 interfaces.MCU is also poor aspect synchronous transmitting data, can only order executive communication program.

Show in the field in modern observing and controlling or survey, the requirement of the synchronization accuracy of three-dimensional or multidimensional measure is more and more higher, not only require topworks's linear electric motors of motion control and motion control mechanism is high-accuracy, high-performance, and require grating chi high resolving power, high precision, more require survey apparent device in grating chi position to have high synchronous high-speed degree and gather a plurality of grating chi position datas and very short communication cycle.Therefore, traditional position survey show device be difficult to satisfy high synchronously, the requirement of high precision and two-forty, design is high synchronously, the position of high precision and two-forty is surveyed and shown device and become demand too impatient to wait.

The utility model content

The purpose of this utility model is in order to solve the defective of above-mentioned prior art, provide a kind of high synchronously, high precision and two-forty support the position of a plurality of grating chis to survey based on monolithic FPGA to show device.

The purpose of this utility model can reach by taking following technical scheme:

Supporting the position of a plurality of grating chis to survey based on monolithic FPGA shows device, it is characterized in that: comprise

The PHY ethernet module that is connected with Ethernet by Ethernet interface;

The RS485﹠amp that is connected with a plurality of grating chis by grating chi interface; The 26LS32 module;

Inside is provided with soft nucleus CPU and is used for and grating chi, Ethernet and RS485﹠amp; The FPGA that the RS232 module communicates;

Be used for realizing that RS485 communicates by letter and the RS485﹠amp of the electric driving of RS232 serial communication; The RS232 module;

Be used for the LCD display interface that matches and be connected with the electric driving interface of LCD display;

The FLASH storer that is used for logic, gate circuit and the soft nucleus CPU code of storage FPGA;

And the SDRAM storer that is used for storage running soft nucleus CPU code and temporary grating chi position and Ethernet data;

Described PHY ethernet module, RS485﹠amp; 26LS32 module, RS485﹠amp; RS232 module, LCD display interface, FLASH storer and SDRAM storer are connected with FPGA respectively.

As a kind of preferred version, comprise that also described active crystal oscillator is connected with FPGA respectively with jtag interface be used to providing clock to the active crystal oscillator of FPGA and being used for debugging and the jtag interface of download FPGA software.

As a kind of preferred version, described FPGA inside also is provided with RS485 communication module, RS232 communication module, LCD display logic module, PLL module, ethernet data-link module, grating chi communication module, quadrature decoder counting module, FLASH logic module and SDRAM module.

As a kind of preferred version, described PHY ethernet module is made up of PHY chip and peripheral circuit.

As a kind of preferred version, described RS485﹠amp; The 26LS32 module is made up of 485 chips, 26LS32 chip and peripheral circuit.

As a kind of preferred version, described RS485﹠amp; The RS232 module is made up of 485 chips, 232 chips and location circuit.

As a kind of preferred version, described LCD display interface is made up of electric driving chip and peripheral circuit.

The utility model has following beneficial effect with respect to prior art:

Apparent device is surveyed in 1 position of the present utility model can carry out the grating chi of orthogonal coding interface the P-pulse counting by FPGA, also can communicate position data and other information of reading with the grating chi of various communication protocols, can realize carrying out communicating by letter of high-speed real-time with host computer (comprising kinetic control system, measuring system etc.), also can carry out simple point-to-point communication with PC, can realize the RS485 communication up to 20Mbps, can carry out high-speed communication with the host computer that does not have Ethernet, also realize serial communication.

2, position of the present utility model is surveyed to show and can be made a plurality of grating chis data that receive orders simultaneously, and while sampling grating chi is in the position data of this this position of moment, reach height and obtained the requirement of grating chi position data synchronously, owing to adopt the grating chi communication module of FPGA inside, select high-precision absolute type grating chi simultaneously for use, can realize and synchronous, high-speed and high-precision communication of a plurality of grating chi height.

3, the apparent device of position survey of the present utility model passes through RS485﹠amp; The 26LS32 module can realize nearly 12 tunnel RS485 passage and the orthogonal coding differential signal channel that reaches 18 tunnel, communicates by letter when can realize at least with 6 grating chis by grating chi interface.

Description of drawings

Fig. 1 surveys the structured flowchart that shows device for the utility model position;

Fig. 2 is the utility model FPGA inner structure block diagram.

Embodiment

Embodiment 1:

As shown in Figure 1, the survey of the position of present embodiment shows device and comprises FPGA, PHY ethernet module, RS485﹠amp; 26LS32 module, RS485﹠amp; RS232 module, LCD display interface, active crystal oscillator, jtag interface, FLASH storer and SDRAM storer, described PHY ethernet module, RS485﹠amp; 26LS32 module, RS485﹠amp; RS232 module, LCD display interface, active crystal oscillator, jtag interface, FLASH storer and SDRAM storer are connected with FPGA respectively.

FPGA is used for and grating chi, Ethernet and RS485﹠amp; The RS232 module communicates, concrete function is as follows: the grating chi of orthogonal coding interface can be carried out the P-pulse counting, also can communicate position data and other information (as communication protocols such as EnDat, BISS, FeaDat, SSI and TAMAGAWA) of reading with the grating chi of various communication protocols; Can realize data link layer and the application layer of ethernet communication, can realize carrying out communicating by letter of high-speed real-time with host computer (comprising kinetic control system, measuring system etc.), also can carry out simple point-to-point communication with PC, can realize the RS485 communication up to 20Mbps, can carry out high-speed communication with the host computer that does not have Ethernet, also realized serial communication, and the position data of grating chi and other information are exactly by ethernet module or RS485﹠amp; The RS232 module is transferred to host computer; In addition, also realized the driving that LCD shows, can show the position data of 6 grating chis simultaneously, and shown and can reach behind the radix point 3, real-time online shown the residing position of grating chi.

The PHY ethernet module, be made up of PHY chip and peripheral circuit, be used for realizing the physical layer protocol of Ethernet, its peripheral circuit is the same substantially with common Ethernet, peripheral circuit has disposed some parameters of PHY chip, has just entered normal communication state after making the PHY chip power.

RS485﹠amp; The 26LS32 module, formed by 485 chips, 26LS32 chip and peripheral circuit, be used for to realize RS485 communication and to the quadrature code differential pulse carry out level conversion, this module realizes nearly 12 tunnel RS485 passage, with the orthogonal coding differential signal channel that reaches 18 tunnel, communicate by letter when can realize at least with 6 grating chis by grating chi interface.

RS485﹠amp; The RS232 module is made up of 485 chips, 232 chips and location circuit, is used for realizing the electric driving of RS485 communication and RS232 serial communication.

The LCD display interface is made up of electric driving chip and peripheral circuit, is connected for matching with the electric driving interface of LCD display.

Active crystal oscillator provides clock to FPGA, and the frequency of the clock that provides because of active crystal oscillator is lower, needs FPGA inside to carry out PLL module frequency multiplication and just can meet the demands.

Jtag interface is used for debugging and downloads FPGA software.

The FLASH storer is used for the logic gates of storage FPGA and the code of soft nucleus CPU, plays the non-volatile memory action of power down; The SDRAM storer is used for code and temporary grating chi position data, Ethernet data and other information of operation soft nucleus CPU, after powering on, the data that FPGA just will be stored in the FLASH storer import to FPGA inside respectively and are loaded into the SDRAM storer, what import to FPGA inside has just formed Digital Logic and gate circuit, and what be loaded into the SDRAM storer is the code of operation soft nucleus CPU.

As shown in Figure 2, described FPGA inside is provided with soft nucleus CPU, RS485 communication module, RS232 communication module, LCD display logic module, PLL module, ethernet data-link module, grating chi communication module, quadrature decoder computing module, FLASH logic module and SDRAM module.

Soft nucleus CPU is used for control and coordinates each module, and communication data is handled, and which kind of communication protocol, bsp driver and application layer program are selected in the transmitting-receiving of control communication data, finish LCD display driving software and position menu display routine.

Grating chi communication module (comprising communication protocol modules such as EnDat commonly used, BISS, FeaDat, SSI and TAMAGAWA), be used for communicating with the grating chi of each communication protocol, which kind of communication protocol soft nucleus CPU can select communicate with corresponding grating chi by corresponding various types of grating chi communicating protocol parameters of prior setting, this each agreement submodule is write by hardware description language and by SDK (Software Development Kit) comp comprehensive layout wiring, with FPGA internal logic unit (LE) and gate circuit by the function composition that links together.

The quadrature decoder counting module, be used for the quadrature coding pulse signal that the grating chi the is sent back counting of decoding, from system power on back meter to data be exactly the measured position data of grating chi, it is clear 0 also can to carry out step-by-step counting by the Z signal, and this module forms with the same the description by hardware description language of grating chi communication module.

LCD display logic module, for generation of controling and data signal the digital logic hardware to LCD, its demonstration data and menu are controlled by soft nucleus CPU, and this module is described by hardware description language and is formed.

The PLL(phaselocked loop) module, be used for the external crystal-controlled oscillation clock multiplier to higher clock frequency reaching soft nucleus CPU and each touches piece operation and fast state, this module can directly be called and arrange the IP that FPGA carries and finish.

Position data and other information that RS485 communication module and RS232 communication module can be used for the transmission grids chi read to host computer, are applicable to the occasion of low speed transmissions data, and this module is described by hardware description language and formed.

FLASH logic module and SDRAM logic module are used for finishing control and read and write outside FLASH storer and SDRAM storer, its each free FPGA internal digital logical block and gate circuit produce output control, sheet choosing, read-write, address and data-signal, and these two modules can directly be called and arrange the IP that FPGA carries and finish.

The above; it only is the utility model preferred embodiment; but protection domain of the present utility model is not limited thereto; anyly be familiar with those skilled in the art in scope disclosed in the utility model; be equal to replacement or change according to the technical solution of the utility model and utility model design thereof, all belonged to protection domain of the present utility model.

Claims

1. supporting the position of a plurality of grating chis to survey based on monolithic FPGA shows device, it is characterized in that: comprise

The PHY ethernet module that is connected with Ethernet by Ethernet interface;

The FLASH storer that is used for the code of the logic gates of storage FPGA and soft nucleus CPU;

And the SDRAM storer that is used for the code of storage running soft nucleus CPU, temporary grating chi position data and Ethernet data;

2. according to claim 1ly support the position of a plurality of grating chis survey to show device based on monolithic FPGA, it is characterized in that: comprise that also described active crystal oscillator is connected with FPGA respectively with jtag interface be used to providing clock to the active crystal oscillator of FPGA and being used for debugging and the jtag interface of download FPGA software.

3. according to claim 1ly support the position of a plurality of grating chis survey to show device based on monolithic FPGA, it is characterized in that: described FPGA inside also is provided with RS485 communication module, RS232 communication module, LCD display logic module, PLL module, ethernet data-link module, grating chi communication module, quadrature decoder computing module, FLASH logic module and SDRAM module.

4. each describedly supports the position of a plurality of grating chis survey to show device based on monolithic FPGA according to claim 1-3, and it is characterized in that: described PHY ethernet module is made up of PHY chip and peripheral circuit.

5. according to each described apparent device of position survey of supporting a plurality of grating chis based on monolithic FPGA of claim 1-3, it is characterized in that: described RS485﹠amp; The 26LS32 module is made up of 485 chips, 26LS32 chip and peripheral circuit.

6. according to each described apparent device of position survey of supporting a plurality of grating chis based on monolithic FPGA of claim 1-3, it is characterized in that: described RS485﹠amp; The RS232 module is made up of 485 chips, 232 chips and location circuit.

7. each describedly supports the position of a plurality of grating chis survey to show device based on monolithic FPGA according to claim 1-3, and it is characterized in that: described LCD display interface is made up of electric driving chip and peripheral circuit.