CN203672902U - Information collection system for photoelectric encoder - Google Patents
Information collection system for photoelectric encoder Download PDFInfo
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- CN203672902U CN203672902U CN201320711412.7U CN201320711412U CN203672902U CN 203672902 U CN203672902 U CN 203672902U CN 201320711412 U CN201320711412 U CN 201320711412U CN 203672902 U CN203672902 U CN 203672902U
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- 238000002955 isolation Methods 0.000 claims abstract description 23
- 230000005622 photoelectricity Effects 0.000 claims description 19
- 238000001914 filtration Methods 0.000 claims description 18
- 238000006243 chemical reaction Methods 0.000 abstract description 7
- 230000010354 integration Effects 0.000 abstract 1
- 230000005693 optoelectronics Effects 0.000 description 8
- 230000002441 reversible effect Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 230000007613 environmental effect Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
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Abstract
The utility model discloses an information collection system for a photoelectric encoder, and the system comprises a photoelectric encoder unit, a collection card, a field-programmable gate array, and an optoelectronic-isolation input/output circuit. The interior of the field-programmable gate array is provided with a filter circuit, a forward-backward counter, a speed-calculating circuit and a digital-analog conversion module in an integrated manner, wherein the filter circuit, the forward-backward counter, the speed-calculating circuit and the digital-analog conversion module are sequentially connected together. The input end of the collection card is connected with the photoelectric encoder unit, and the output end of the collection card is connected with the signal input end of an input circuit of the optoelectronic-isolation input/output circuit. The signal output end of the input circuit of the optoelectronic-isolation input/output circuit is connected with the input end of the filter circuit. The output end of the digital-analog conversion module is connected with an output circuit of the optoelectronic-isolation input/output circuit. The system provided by the utility model is small in size, is high in degree of integration, is good in transplantability, is high in precision, and is suitable for a three-axis stable platform, a four-axis nacelle, and other multi-axis servo products. Moreover, the output function of the digital-analog conversion module is in favor of the subsequent development of the system.
Description
Technical field
The utility model relates to servocontrol field, is specifically related to a kind of photoelectric code disk information acquisition system for photoelectric tracking table servo system.
Background technology
Photoelectric encoder is a kind of sensor that by opto-electronic conversion, the geometry of machinery displacement on output shaft is converted to pulse or digital quantity.In high precision photoelectric tracking table servocontrol, photoelectric encoder is the measuring element playing a crucial role.Photoelectric tracking turntable only collects high-precision photoelectric code disk information, can realize electro-optical tracking device the accurate aiming of maneuvering target is followed the tracks of.
Fig. 1 shows the structural representation of existing photoelectric code disk information acquisition system.As shown in Figure 1, existing photoelectric code disk information acquisition system comprises code-disc (for the digital encoder of measured angular displacement), capture card, photoelectricity Isolation input circuit, PC104 main frame board, FPGA(Field-Programmable Gate Array, field programmable gate array) and analog-to-digital conversion device.Capture card gathers the code-disc information of code-disc, be sent to PC104 main frame board through photoelectricity Isolation input circuit, in PC104 main frame board, be provided with filtering circuit, code-disc information inputs to FPGA after filtering circuit is processed, to code-disc information quadruple, decoding obtains positional information through up-down counter to FPGA, then positional information is carried out obtaining rotary speed information after difference processing.Rotary speed information is realized the simulation output of rotating speed through digital-to-analogue converter.
In the time that photoelectric code disk information acquisition system carries out photoelectric code disk information acquisition, above-mentioned each parts are indispensable, and the separate setting of above-mentioned each parts of existing photoelectric code disk information acquisition system.Due to all parts need separately design or buy after row assembling again, thereby make photoelectric code disk information acquisition system there is the drawback large such as volume, integrated level is low, cost is higher.And because filtering circuit, FPGA, D/A converter module in existing photoelectric code disk information acquisition system are separated from one another, therefore also there is portable poor shortcoming.
Utility model content
The purpose of this utility model has been to provide the photoelectric code disk information acquisition system that a kind of volume is little, integrated level is high, portability is good.
According to embodiment of the present utility model, photoelectric code disk information acquisition system is provided, comprise photoelectric encoder, capture card and on-site programmable gate array FPGA, photoelectricity Isolation input output circuit,
In described FPGA, be integrated with the filtering circuit, up-down counter, speed counting circuit and the D/A converter module that connect successively;
The input end of capture card is connected with photoelectric encoder, and its output terminal is connected with the signal input part of input circuit in photoelectricity Isolation input output circuit;
In photoelectricity Isolation input output circuit, the signal output part of input circuit and the input end of described filtering circuit are connected;
The output terminal of described D/A converter module is connected with the output circuit in photoelectricity Isolation input output circuit.
Wherein, described up-down counter comprises 8 up-down counters of at least 4 serially concatenateds.
Preferably, described up-down counter comprises 8 up-down counters of 4 serially concatenateds.
As another preferred version, described up-down counter comprises 64 up-down counters of 8 up-down counters of 8 serially concatenateds.
Wherein, described up-down counter comprises and code-disc orthogonal signal is carried out to the quadruple decoding circuit of quadruple decoding and for improving the sensing circuit of up-down counter antijamming capability;
The output terminal of described quadruple decoding circuit is connected with up-down counter, and output terminal is connected with the input end of sensing circuit;
The output terminal of described sensing circuit is connected with the input end of described speed counting circuit.
Further, photoelectric code disk information acquisition system also comprises:
For the PC104 motherboard card interface being connected with PC104 motherboard card, it is connected with the output terminal of described up-down counter.
Preferably, in described filtering circuit, be provided with the d type flip flop of setting the code-disc value in the clock period for recording.
Further, photoelectric code disk information acquisition system also comprises:
Be arranged at FPGA inside and mole state machine for generation of D/A converter module output timing, its input end is connected with D/A converter module.
As shown from the above technical solution, the utlity model has that volume is little, integrated level is high and portable good feature.
Brief description of the drawings
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, below will the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described.Apparently, the accompanying drawing in below describing is only embodiment more of the present utility model, for those of ordinary skills, can also obtain according to these accompanying drawing illustrated embodiments other embodiment and accompanying drawing thereof.
Fig. 1 shows the structural representation of existing photoelectric code disk information acquisition system;
Fig. 2 shows the structural representation of photoelectric code disk information acquisition system in the utility model.
Embodiment
For making the purpose of this utility model, technical scheme and advantage clearer, referring to accompanying drawing and enumerate preferred embodiment, the utility model is further described.But, it should be noted that, many details of listing in instructions are only used to make reader to have a thorough understanding to one or more aspects of the present utility model, even if do not have these specific details also can realize these aspects of the present utility model.
The terms such as " module " used in this application, " system " are intended to comprise the entity relevant to computing machine, such as but not limited to hardware, firmware, combination thereof, software or executory software.For example, module can be, but be not limited in: thread, program and/or the computing machine of the process moved on processor, processor, object, executable program, execution.
Fig. 2 shows the structural representation of photoelectric code disk information acquisition system in the utility model.As shown in Figure 2, photoelectric code disk information acquisition system comprises capture card 1, photoelectricity Isolation input output circuit 2 and field programmable gate array (writing a Chinese character in simplified form below FPGA).
In field programmable gate array, be integrated with the filtering circuit 3, up-down counter 4, speed counting circuit 5 and the D/A converter module 6 that connect successively.
The input end of capture card 1 is connected with photoelectric encoder and for gathering photoelectric encoder code-disc information, its output terminal is connected with the signal input part of input circuit in photoelectricity Isolation input output circuit 2.
In photoelectricity Isolation input output circuit 2, the signal output part of input circuit is connected with the input end of described filtering circuit 3.In filtering circuit, be provided with the d type flip flop of setting the code-disc value in the clock period for recording.
The output terminal of D/A converter module 6 is connected with the output circuit in photoelectricity Isolation input output circuit 2.
Up-down counter 4 in the present embodiment comprises 8 up-down counters 4 of at least 4 serially concatenateds.As the preferred embodiment in each embodiment, the up-down counter in the present embodiment comprises 8 up-down counters of 4 serially concatenateds, and 48 up-down counter cascaded carries cascades realize 32 reversible countings.For single 16 up-down counters, in the time carrying out logical operation, 16 meter digitals all calculate, and therefore can take more logical block.The utility model adopts 48 up-down counter cascaded carries cascades, and first up-down counter utilizes 8 up-down counters to calculate in the time carrying out logical calculated, when full backward upper one 8 the up-down counter carries of 8 up-down counter meters.In the time that 4 up-down counters all calculate, just can realize 32 reversible countings.Hence one can see that, and compared to the up-down counter of the photoelectric code disk information acquisition systems of 16, the up-down counter in the utility model takies less logical block in the time that identical figure place is calculated, and can ensure the computational accuracy of 32.
As another preferred version, the up-down counter in embodiment also can utilize 88 up-down counter cascaded carries cascades to realize 64 reversible countings, thereby realizes the more high precision of photoelectric code disk information acquisition system in the utility model.
Further, in FPGA, in up-down counter, also comprise and debating to circuit (not shown), for can steady operation under the normal condition of input at two phase input signals of code-disc information, under the state of two phase input signal input errors, its output signal can not change, and has improved the antijamming capability of up-down counter.
The digital value of the rotating speed that digital-to-analogue conversion module obtains speed counting circuit 5 is exported after being converted to the rotating speed analogue value.
Preferably, in FPGA inside, be also provided with a mole state machine (not shown), be connected with D/A converter module 6, for generation of the output timing of D/A converter module 6.
Further, the photoelectric code disk information acquisition system in the utility model also comprises PC104 motherboard card interface, and PC104 motherboard card interface is connected with the output terminal of up-down counter.PC104 motherboard card interface is for being connected with PC104 motherboard card 7.
Below the principle of work of photoelectric code disk information acquisition system in the utility model is described in detail.
Produce noise signal because scrambler is also easily subject to environmental interference in actual measurement process, as environmental interference noise and/or mechanical vibration noise, thereby make the mistake counting, reduce the precision of whole control system.Therefore code disc optoelectronic signal is carried out to interference source and is subject to after interference sections isolates, needing the filtering circuit 3 in FPGA to carry out filtering to code disc optoelectronic signal at photoelectricity Isolation input circuit imput output circuit.
Wherein, filtering principle is: general noise signal width is very narrow, and in the situation that clock frequency is higher, while being 40MHz as hardware components input clock frequency, noise signal generally maintains 1 to 2 clock width.By to the interpretation of code-disc signal delay, judge the clock period that whether its state changes and this variation maintains.Filtering circuit 3, after code-disc signal input, uses d type flip flop to store the code-disc value of current code-disc value and first 10 times.If the state of signal occurred change and maintain 10 clock period or more than, think that variation has occurred signal, otherwise think noise signal, by its filtering.
In order to eliminate the mechanical vibration noise producing and the positioning precision that improves scrambler, the up-down counter in FPGA comprises quadruple decoding circuit and sensing circuit.The output terminal of quadruple decoding circuit is connected with up-down counter, and output terminal is connected with the input end of sensing circuit; The output terminal of sensing circuit is connected with the input end of described speed counting circuit.
Code-disc orthogonal signal are carried out quadruple decoding by quadruple decoding circuit, quadruple decoding circuit adopts state transitions mode to count, sensing circuit not only makes the up-down counter can steady operation under the normal condition of two phase input signals, and under the state of two phase input signal input errors, ensure that output signal does not change, thereby tightness and the antijamming capability of up-down counter are improved.
FPGA inside is provided with a mole state machine, and the output terminal of mole state machine is connected with D/A converter module, for generation of the output timing of D/A converter module.
For generation of the output timing of relevant D/A converter module 6, the analogue value of output speed signal.The output logic of building D/A converter module 6 in FPGA sheet is realized the simulation output of speed, for the expansion of system provides possibility, has removed from and has purchased or redesign D/A converter module output board.
For reducing the taking of PC104 address, the utility model adopts inquiry mode reading speed information.By to a fixed address data writing, by the judgement of data writing is transmitted to data to PC104 main frame board again, reduced like this taking PC104 main frame board address.
In the utility model, filtering circuit and D/A converter module are all integrated in FPGA, only need to be by the code-disc information of photoelectric encoder through photoelectricity Isolation input output circuit input code-disc information, fpga chip can calculate rotating speed and export through photoelectricity Isolation input output circuit, therefore the utility model is in the time being connected with other photoelectric encoders, do not need other equipment can carry out calculating and the numerical value output of rotating speed, it is portable good therefore to have advantages of.
From above technical scheme, the utlity model has that volume is little, integrated level is high and portable good feature.In addition, the utility model utilizes 8 up-down counter cascades to realize 32 and above reversible counting, when minimizing logical block takies, greatly improves the precision of acquisition system, is applicable to the multiple-axis servo product such as three-axle steady platform or four axle gondolas.
The foregoing is only preferred embodiment of the present utility model, not for limiting protection domain of the present utility model.All within spirit of the present utility model and principle, any amendment of doing, be equal to and replace and improvement etc., within all should being included in protection domain of the present utility model.
Claims (8)
1. a photoelectric code disk information acquisition system, comprises photoelectric encoder, capture card and on-site programmable gate array FPGA, it is characterized in that, also comprises photoelectricity Isolation input output circuit,
In described FPGA, be integrated with the filtering circuit, up-down counter, speed counting circuit and the D/A converter module that connect successively;
The input end of capture card is connected with photoelectric encoder, and the output terminal of capture card is connected with the signal input part of input circuit in photoelectricity Isolation input output circuit;
In photoelectricity Isolation input output circuit, the signal output part of input circuit and the input end of described filtering circuit are connected;
The output terminal of described D/A converter module is connected with the output circuit in photoelectricity Isolation input output circuit.
2. photoelectric code disk information acquisition system according to claim 1, is characterized in that, described up-down counter comprises 8 up-down counters of at least 4 serially concatenateds.
3. photoelectric code disk information acquisition system according to claim 2, is characterized in that, described up-down counter comprises 8 up-down counters of 4 serially concatenateds.
4. photoelectric code disk information acquisition system according to claim 2, is characterized in that, described up-down counter comprises 8 up-down counters of 8 serially concatenateds.
5. according to arbitrary described photoelectric code disk information acquisition system in claim 1 to 4, it is characterized in that, described up-down counter comprises and code-disc orthogonal signal is carried out to the quadruple decoding circuit of quadruple decoding and for improving the sensing circuit of up-down counter antijamming capability;
The input end of described quadruple decoding circuit is connected with up-down counter, and output terminal is connected with the input end of sensing circuit;
The output terminal of described sensing circuit is connected with the input end of described speed counting circuit.
6. according to arbitrary described photoelectric code disk information acquisition system in claim 1 to 4, it is characterized in that, also comprise:
For the PC104 motherboard card interface being connected with PC104 motherboard card, it is connected with the output terminal of described up-down counter.
7. according to arbitrary described photoelectric code disk information acquisition system in claim 1 to 4, it is characterized in that, in described filtering circuit, be provided with the d type flip flop of setting the code-disc value in the clock period for recording.
8. photoelectric code disk information acquisition system according to claim 1, is characterized in that, also comprises:
Be arranged at FPGA inside and mole state machine for generation of D/A converter module output timing, its input end is connected with D/A converter module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320711412.7U CN203672902U (en) | 2013-11-12 | 2013-11-12 | Information collection system for photoelectric encoder |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320711412.7U CN203672902U (en) | 2013-11-12 | 2013-11-12 | Information collection system for photoelectric encoder |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203672902U true CN203672902U (en) | 2014-06-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320711412.7U Expired - Lifetime CN203672902U (en) | 2013-11-12 | 2013-11-12 | Information collection system for photoelectric encoder |
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| Country | Link |
|---|---|
| CN (1) | CN203672902U (en) |
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2013
- 2013-11-12 CN CN201320711412.7U patent/CN203672902U/en not_active Expired - Lifetime
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Granted publication date: 20140625 |
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| CX01 | Expiry of patent term |