CN114726383A - High-throughput parallel cyclic redundancy check method based on CRC-16 - Google Patents

High-throughput parallel cyclic redundancy check method based on CRC-16 Download PDF

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CN114726383A
CN114726383A CN202210381920.7A CN202210381920A CN114726383A CN 114726383 A CN114726383 A CN 114726383A CN 202210381920 A CN202210381920 A CN 202210381920A CN 114726383 A CN114726383 A CN 114726383A
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crc
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赵良斌
王菲菲
代贤乐
李建国
卜祥元
安建平
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Beijing Institute of Technology BIT
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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Abstract

The invention discloses a high-throughput parallel cyclic redundancy check method based on CRC-16, and belongs to the technical field of terahertz communication. The implementation method of the invention comprises the following steps: calculating the relation between the high-throughput parallel CRC code and the input information code sequence by adopting a polynomial division method, calculating the relation between a multi-byte high-throughput parallel CRC code and a single-byte high-throughput parallel CRC code by utilizing a generator polynomial of the CRC codes to obtain a multi-path parallel high-throughput cyclic redundancy check code, namely, the throughput of the cyclic redundancy check code is improved through a parallel framework so as to adapt to high-speed data transmission of a terahertz frequency band; by adding the cyclic redundancy check code, the anti-interference capability of the terahertz communication system is improved. The invention can effectively solve the influence of the system caused by non-ideal channel transmission characteristics and white Gaussian noise, can obtain the high-throughput CRC code relation of 16-path parallel calculation, and effectively improves the throughput of the CRC code, thereby being suitable for the transmission requirement of a terahertz frequency band of tens of Gbps.

Description

High-throughput parallel cyclic redundancy check method based on CRC-16
Technical Field
The invention relates to a high-throughput parallel cyclic redundancy check method based on CRC-16, and belongs to the technical field of terahertz communication.
Technical Field
With the development of communication technology, terahertz communication is receiving attention due to its advantages such as high transmission rate and large capacity, and is a research hotspot in recent years. While the advantages of large bandwidth transmission are achieved, many technical challenges are also created. The transmission rate of the terahertz communication system is extremely high, and the traditional serial architecture cannot meet the increasing rate requirement, so that a parallel architecture needs to be adopted in the terahertz communication system. In practical applications, a terahertz communication system generally needs to achieve throughput of tens of gigabits (Gbps), and there is a great necessity to increase the number of parallel processing paths of an algorithm.
On the other hand, in the terahertz communication system, due to the influence of non-ideal channel transmission characteristics and white gaussian noise, interference resistance becomes one of the difficulties in system data transmission. The problem is also aggravated by the use of higher order modulation techniques, since the distance between constellation points is reduced and the interference immunity is greatly reduced due to the increase of the number of constellation points. Cyclic Redundancy Check (CRC) codes are simple to implement, have a strong error detection capability, are widely used in communication systems, and can effectively resist random interference and burst interference. The research on the high-throughput parallel cyclic redundancy check algorithm applicable to the terahertz communication transmission system is of great necessity.
Disclosure of Invention
The invention mainly aims to provide a high-throughput parallel cyclic redundancy check method based on CRC-16, which comprises the steps of calculating the relation between a high-throughput parallel CRC code and an input information code sequence by adopting a polynomial division method, calculating the relation between a multi-byte high-throughput parallel CRC code and a single-byte high-throughput parallel CRC code by utilizing a generator polynomial of the CRC code, and obtaining a multi-path parallel high-throughput cyclic redundancy check code, namely, improving the throughput of the cyclic redundancy check code through a parallel framework so as to adapt to high-speed data transmission of a terahertz frequency band; by adding the cyclic redundancy check code, the anti-interference capability of the terahertz communication system is improved.
The purpose of the invention is realized by the following technical scheme.
The invention discloses a high-throughput parallel cyclic redundancy check method based on CRC-16, which comprises the following steps:
step 1, according to the channel condition applicable to the terahertz communication system, determining to adopt a CRC-CCITT check code, and determining a polynomial for generating the CRC-CCITT check code.
According to the channel condition applicable to the terahertz communication system, determining to adopt the CRC-CCITT check code, and then generating a polynomial G (x):
G(x)＝x16+x12+x5+1
wherein: x is used only for polynomial expression and has no practical meaning here.
And 2, according to the transmission requirement of the terahertz communication system, data is transmitted in a parallel manner of parr (16 paths), the information code to be checked has n bits, and a polynomial expression of data transmission at the transmitting end at the ith moment is obtained.
According to the transmission requirement of the terahertz communication system, data is transmitted in a parallel manner of parr-16 paths, and a polynomial D for the transmission data of the transmitting end at the ith momenti(x) To show that, if the information code to be checked has n bits, the polynomial corresponding to the information code is expressed as follows:
Di(x)＝Ci(n-1)xn-1+Ci(n-2)xn-2+…+Ci(1)x1+Ci(0)
wherein C isiAnd (n) represents the nth input information code sequence at the ith time, in the parallel architecture, the value range of n is determined by the number of parallel paths, and n is par.
And 3, calculating the relation between the high-throughput parallel CRC code and the input information code sequence by adopting a polynomial division method according to the generating polynomial G (x) determined in the step 1 and the parallel path number determined in the step 2 and the CRC principle.
Step 3.1, determining to adopt CRC-CCITT code as correctionThe check code has the highest power of polynomial k and is multiplied by x at both ends of the information code to be checkedk：
xkDi(x)＝Ci(n-1)xk+n-1+Ci(n-2)xk+n-2+…+Ci(1)xk+1+Ci(0)xk
Step 3.2, xkDi(x) Dividing the model 2 by the generator polynomial G (x) to obtain a polynomial Q corresponding to the quotient at the ith momenti(x) The remainder polynomial at the ith time is Ri(x) The result of the crc is a remainder polynomial expressed as follows:
xkDi(x)+Ri(x)＝Qi(x)G(x)
wherein, the remainder polynomial R at the ith timei(x) Can be expressed as:
Ri(x)＝ri(n-1)xn-1+ri(n-2)xn-2+…+ri(1)x1+ri(0)
step 3.3, in binary calculation, division is equivalent to performing modulo-2 operation, and according to the previous step, the relationship between the 16 parallel CRC codes and the input information code sequence can be obtained by the following formula:
Ri(x)＝xk*Di(x)ModG(x)
where Mod represents modulo-2 operation. Remainder polynomial R at the ith timei(x) And the information code D to be checked at the ith momenti(x) Respectively as follows:
Figure BDA0003592165990000021
Figure BDA0003592165990000031
and 4, in the parallel architecture, the cyclic redundancy check result at the current moment is not only related to the input of the current byte, but also related to the cyclic redundancy check result at the previous moment. And (2) according to the polynomial of the CRC-CCITT check code generated in the step (1), calculating the relation between the multi-byte high-throughput parallel CRC code and the single-byte high-throughput parallel CRC code by using the polynomial of the CRC code.
Step 4.1, according to a generating polynomial G (x) of the CRC-CCITT check code, obtaining the relation between the multi-byte high throughput parallel CRC code and the single-byte high throughput parallel CRC code as follows:
Figure BDA0003592165990000032
Figure BDA0003592165990000033
the value of the j-th register after shifting d times is shown, wherein j is 0,1, …, k-1, and d is 1,2, …, n. m isjThe coefficients representing the generator polynomial having values determined by the generator polynomial G (x), i.e. mj＝1,j＝0,5,12,16。
Step 4.2, gd-1Indicating the present state of the register, i.e. the not shifted state. gdThe secondary state of the register, namely the state after shifting by par, is represented, and for the parallel architecture, par shifting is completed through one calculation. Order:
Figure BDA0003592165990000034
and 4.3, calculating the relation between the multi-byte high throughput parallel CRC code and the single-byte high throughput parallel CRC code according to the derivation formula in the step 4.1 and the specification in the step 4.2.
And step 5, obtaining a multi-path parallel high throughput cyclic redundancy check code according to the relation between the high throughput parallel CRC code obtained in the step 3 and the input information code sequence and the relation between the multi-byte high throughput parallel CRC code obtained in the step 4 and the single-byte high throughput parallel CRC code.
Initializing the parallel CRC check code, and recording as D _ nexti(n) known high throughput parallel CRC code and input information code sequence Ci(n) relationships, multiwordsThe relation between the high-throughput parallel CRC code and the single-byte high-throughput parallel CRC code, and the formula for obtaining the parallel high-throughput CRC code with par being 16 paths is as follows:
Figure BDA0003592165990000035
wherein n has a value in the range of 0,1 … 15,
Figure BDA0003592165990000036
and
Figure BDA0003592165990000037
the relationship between the two is determined by the relationship between the multi-byte high throughput parallel CRC code and the one-byte high throughput parallel CRC code obtained in step 4, i.e., by
Figure BDA0003592165990000038
And gd-1The relationship in (1) is obtained.
And step 6, calculating the relation between the single-byte high-throughput parallel CRC code and the input information code sequence by a polynomial division method based on the steps 1 to 5, and calculating the relation between the multi-byte high-throughput parallel CRC code and the single-byte high-throughput parallel CRC code by using a generating polynomial of the cyclic redundancy check code, so as to obtain the parallel cyclic redundancy check code. The throughput of the cyclic redundancy check code is improved through a parallel architecture so as to adapt to high-speed data transmission of a terahertz frequency band; and the anti-interference capability of the system is improved by adding the cyclic redundancy check code.
Has the advantages that:
1. the invention discloses a high throughput parallel cyclic redundancy check method based on CRC-16, which adds a CRC code in a terahertz system, wherein the CRC code has the advantages of simple realization and strong error detection capability, can effectively solve the influence of the system caused by non-ideal channel transmission characteristics and Gaussian white noise, and effectively improves the anti-interference capability of the system.
2. The invention discloses a high throughput parallel cyclic redundancy check method based on CRC-16, which utilizes a full parallel framework and adopts a polynomial division method to establish the relation between a high throughput parallel CRC code and an input information code sequence according to a CRC principle; establishing a relation between a multi-byte high throughput parallel CRC code and a single-byte high throughput parallel CRC code by using a generating polynomial of the CRC code according to the generated polynomial of the CRC-CCITT check code; by calculating the relation between the parallel CRC codes and the input information code sequence and the relation between the multi-byte high-throughput parallel information codes and the single-byte high-throughput parallel information codes, the relation between 16 paths of parallel calculation to obtain the high-throughput CRC check codes is obtained, the throughput of the CRC codes is effectively improved, and the transmission requirement of a terahertz frequency band of tens of Gbps is met.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a flow chart of a high throughput parallel cyclic redundancy check method based on CRC-16 of the present invention;
FIG. 2 is a block diagram of a CRC-16 based high throughput parallel cyclic redundancy check method according to the present invention;
FIG. 3 is a schematic diagram of the logic for generating CRC16 CCITT;
FIG. 4 is a diagram of data comparison after CRC and CRC of an input information code rate sequence.
Detailed Description
For a better understanding of the objects and advantages of the present invention, reference should be made to the following detailed description taken in conjunction with the accompanying drawings and examples.
Example 1:
as shown in fig. 1, the method for high throughput parallel cyclic redundancy check based on CRC-16 disclosed in this embodiment includes the following specific steps:
step 1, according to the channel condition applicable to the terahertz communication system, determining to adopt a CRC-CCITT check code, and determining a polynomial for generating the CRC-CCITT check code.
According to the channel condition applicable to the terahertz communication system, determining to adopt the CRC-CCITT check code, and then generating a polynomial G (x):
G(x)＝x16+x12+x5+1
wherein: x is used only for polynomial expression and has no practical meaning here.
And 2, according to the transmission requirement of the terahertz communication system, data is transmitted in a parallel manner of parr (16 paths), and the information code to be checked has n (16 bits), so that a polynomial expression of data transmitted by the transmitting end at the ith moment is obtained.
According to the system transmission requirement, adopting parr-16-path parallel mode to transmit data, and using polynomial D for transmitting data of i-th time transmitting endi(x) To show that, if the information code to be checked has n-16 bits, the polynomial corresponding to the information code is expressed as follows:
Di(x)＝Ci(n-1)xn-1+Ci(n-2)xn-2+…+Ci(1)x1+Ci(0)
wherein C isiAnd (n) represents an input information code sequence at the ith time, in the parallel architecture, the value range of n is determined by the number of parallel paths, and n is equal to par and equal to 16.
Fig. 2 is a computation block diagram of a high-throughput parallel cyclic redundancy check method based on CRC-16, which completes computation according to the computation flow in the process.
And 3, calculating the relation between the high-throughput parallel CRC code and the input information code sequence by adopting a polynomial division method according to the generating polynomial G (x) determined in the step 1 and the parallel path number determined in the step 2 and the CRC principle.
Step 3.1, determining to adopt the CRC-CCITT code as the check code, wherein the highest power of the generating polynomial is k-16, and multiplying x at two ends of the information code to be checked16：
x16Di(x)＝Ci(n-1)x16+n-1+Ci(n-2)x16+n-2+…+Ci(1)x16+1+Ci(0)x16
Step 3.2, x16Di(x) Dividing the model 2 by the generator polynomial G (x) to obtain a polynomial Q corresponding to the quotient at the ith momenti(x) The remainder polynomial at the ith time is Ri(x) The result of the crc is a remainder polynomial expressed as follows:
x16Di(x)+Ri(x)＝Qi(x)G(x)
wherein, the remainder polynomial R at the ith timei(x) Can be expressed as:
Ri(x)＝ri(n-1)xn-1+ri(n-2)xn-2+…+ri(1)x1+ri(0)
step 3.3, in binary calculation, division is equivalent to performing modulo-2 operation, and according to the previous step, the relationship between the 16 parallel CRC codes and the input information code sequence can be obtained by the following formula:
Ri(x)＝x16*Di(x)ModG(x)
where Mod represents a modulo-2 operation. Due to the remainder polynomial R at the ith timei(x) And the information code D to be checked at the ith momenti(x) Respectively as follows:
Figure BDA0003592165990000061
Figure BDA0003592165990000062
polynomial R of remainderi(x) And the information code D to be checkedi(x) Into formula Ri(x)＝x16*Di(x) Mod G (x) yields that the relationship between the 16-way parallel CRC code and the input information code sequence is:
Figure BDA0003592165990000063
Figure BDA0003592165990000064
Figure BDA0003592165990000065
Figure BDA0003592165990000066
Figure BDA0003592165990000067
Figure BDA0003592165990000068
Figure BDA0003592165990000069
Figure BDA00035921659900000610
Figure BDA00035921659900000611
Figure BDA00035921659900000612
Figure BDA00035921659900000613
Figure BDA00035921659900000614
Figure BDA00035921659900000615
Figure BDA00035921659900000616
Figure BDA00035921659900000617
Figure BDA00035921659900000618
and 4, in the parallel architecture, the cyclic redundancy check result at the current moment is not only related to the input of the current byte, but also related to the cyclic redundancy check result at the previous moment. And (2) according to the polynomial of the CRC-CCITT check code generated in the step (1), calculating the relation between the multi-byte high-throughput parallel CRC code and the single-byte high-throughput parallel CRC code by using the polynomial of the CRC code.
Step 4.1, according to the generator polynomial G (x) of the CRC1-CCITT check code, obtaining the relation between the multi-byte high throughput parallel CRC code and the single-byte high throughput parallel CRC code as follows:
Figure BDA0003592165990000071
Figure BDA0003592165990000072
the value of the j-th register after shifting d times is shown, j is 0,1, … k, -1, d is 1,2, …, n. m isjThe coefficients representing the generator polynomial having values determined by the generator polynomial G (x), i.e. mj＝1,j＝0,5,12,16。
FIG. 3 is a schematic diagram of the CRC-CCITT generation logic, where mjIs 1, the switch is closed.
Step 4.2, gd-1Indicating the present state of the register, i.e. the not shifted state. gdThe secondary state of the register, namely the state after shifting by par, is represented, and for the parallel architecture, par shifting is completed through one calculation. Order:
Figure BDA0003592165990000073
and 4.3, calculating the relation between the multi-byte high-throughput parallel CRC code and the single-byte high-throughput parallel CRC code according to the formula deduced in the step 4.1 and the regulation in the step 4.2.
Figure BDA0003592165990000074
Figure BDA0003592165990000075
Figure BDA0003592165990000076
Figure BDA0003592165990000077
Figure BDA0003592165990000078
Figure BDA0003592165990000079
Figure BDA00035921659900000710
Figure BDA00035921659900000711
Figure BDA00035921659900000712
Figure BDA00035921659900000713
Figure BDA00035921659900000714
Figure BDA00035921659900000715
Figure BDA0003592165990000081
Figure BDA0003592165990000082
Figure BDA0003592165990000083
Figure BDA0003592165990000084
And step 5, obtaining a multi-path parallel high throughput cyclic redundancy check code according to the relation between the high throughput parallel CRC code obtained in the step 3 and the input information code sequence and the relation between the multi-byte high throughput parallel CRC code obtained in the step 4 and the single-byte high throughput parallel CRC code.
Initialization of the parallelized CRC check codes, noted
Figure BDA0003592165990000085
Figure BDA0003592165990000086
Known high throughput parallel CRC code and input information code sequence Ci(n) and a relation between the multi-byte high throughput parallel CRC code and the single-byte high throughput parallel CRC code, and the formula for obtaining the 16-way parallel high throughput CRC code is:
Figure BDA0003592165990000087
wherein n has a value in the range of 0,1 … 15,
Figure BDA0003592165990000088
and
Figure BDA0003592165990000089
the relationship between the two is determined by the relationship between the multi-byte high throughput parallel CRC code and the one-byte high throughput parallel CRC code obtained in step 4, i.e., by
Figure BDA00035921659900000810
And gd-1The relationship in (1) is obtained.
Figure BDA00035921659900000811
Figure BDA00035921659900000812
Figure BDA00035921659900000813
Figure BDA00035921659900000814
Figure BDA0003592165990000091
Figure BDA0003592165990000092
Figure BDA0003592165990000093
Figure BDA0003592165990000094
Figure BDA0003592165990000095
Figure BDA0003592165990000096
Figure BDA0003592165990000097
Figure BDA0003592165990000098
Figure BDA0003592165990000101
Figure BDA0003592165990000102
Figure BDA0003592165990000103
Figure BDA0003592165990000104
As shown in fig. 4, the comparison result between the input information code sequence and the input information code sequence is equal after 16-way high throughput parallel CRC encoding is performed on the input information code sequence and after 16-way parallel decoding is performed on the input information code sequence, and the number of different codes is zero. It can thus be shown that this algorithm is efficient.
The above detailed description is further intended to illustrate the objects, technical solutions and advantages of the present invention, and it should be understood that the above detailed description is only an example of the present invention and should not be used to limit the scope of the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (7)

1. A high throughput parallel cyclic redundancy check method based on CRC-16 is characterized in that: comprises the following steps of (a) carrying out,
step 1, determining to adopt a CRC-CCITT check code according to the channel condition applicable to the terahertz communication system, and determining a polynomial for generating the CRC-CCITT check code;
step 2, according to the transmission requirement of the terahertz communication system, data is transmitted in a parallel manner of parr being 16 paths, the information code to be checked has n bits, and a polynomial expression of data transmission of the transmitting end at the ith moment is obtained;
step 3, according to the polynomial G (x) determined in the step 1 and the parallel path number determined in the step 2, calculating by adopting a polynomial division method according to a CRC principle to obtain a relation between a high-throughput parallel CRC code and an input information code sequence;
step 4, in the parallel framework, the cyclic redundancy check result at the current moment is not only related to the input of the current byte, but also related to the cyclic redundancy check result at the previous moment; according to the polynomial of the CRC-CCITT check code generated in the step 1, calculating the relation between the multi-byte high throughput parallel CRC code and the single-byte high throughput parallel CRC code by using the polynomial of the CRC code;
and step 5, obtaining a multi-path parallel high throughput cyclic redundancy check code according to the relation between the high throughput parallel CRC code obtained in the step 3 and the input information code sequence and the relation between the multi-byte high throughput parallel CRC code obtained in the step 4 and the single-byte high throughput parallel CRC code.
2. A method for high throughput parallel cyclic redundancy check based on CRC-16 as claimed in claim 1 wherein: step 6, calculating the relation between the single-byte high throughput parallel CRC code and the input information code sequence by a polynomial division method based on the steps 1 to 5, and calculating the relation between the multi-byte high throughput parallel CRC code and the single-byte high throughput parallel CRC code by using a generating polynomial of the cyclic redundancy check code, wherein the cyclic redundancy check code is parallel; the throughput of the cyclic redundancy check code is improved through a parallel architecture so as to adapt to high-speed data transmission of a terahertz frequency band; and the anti-interference capability of the system is improved by adding the cyclic redundancy check code.
3. A method for high throughput parallel cyclic redundancy check based on CRC-16 according to claim 1 or 2, characterized by: the step 1 is realized by the method that,
according to the channel condition applicable to the terahertz communication system, determining to adopt the CRC-CCITT check code, and then generating a polynomial G (x):
G(x)＝x16+x12+x5+1
wherein: x is used only for polynomial expression and has no practical meaning here.
4. A method for high throughput parallel cyclic redundancy check based on CRC-16 as claimed in claim 3 wherein: the step 2 is realized by the method that,
according to the transmission requirement of the terahertz communication system, data is transmitted in a parr-16-channel parallel modePolynomial D for transmission data of i moment transmitting endi(x) To show that, if the information code to be checked has n bits, the polynomial corresponding to the information code is expressed as follows:
Di(x)＝Ci(n-1)xn-1+Ci(n-2)xn-2+…+Ci(1)x1+Ci(0)
wherein C isiAnd (n) represents the nth input information code sequence at the ith time, in the parallel architecture, the value range of n is determined by the number of parallel paths, and n is par.
5. A method for high throughput parallel cyclic redundancy check based on CRC-16 as claimed in claim 4 wherein: the step 3 is realized by the method that,
step 3.1, determining to adopt CRC-CCITT code as check code, the highest power of the generating polynomial is k, and multiplying x at two ends of the information code to be checkedk：
xkDi(x)＝Ci(n-1)xk+n-1+Ci(n-2)xk+n-2+…+Ci(1)xk+1+Ci(0)xk
Step 3.2, xkDi(x) Dividing the model 2 by the generator polynomial G (x) to obtain a polynomial Q corresponding to the quotient at the ith momenti(x) The remainder polynomial at the ith time is Ri(x) The result of the crc is a remainder polynomial expressed as follows:
xkDi(x)+Ri(x)＝Qi(x)G(x)
wherein, the remainder polynomial R at the ith timei(x) Can be expressed as:
Ri(x)＝ri(n-1)xn-1+ri(n-2)xn-2+…+ri(1)x1+ri(0)
step 3.3, in binary calculation, division is equivalent to performing modulo-2 operation, and according to the previous step, the relationship between the 16 parallel CRC codes and the input information code sequence can be obtained by the following formula:
Ri(x)＝xk*Di(x)Mod G(x)
wherein, Mod represents modulo-2 arithmetic; remainder polynomial R at the ith timei(x) And the information code D to be checked at the ith momenti(x) Respectively as follows:
Figure FDA0003592165980000021
Figure FDA0003592165980000022
6. a method for high throughput parallel cyclic redundancy check based on CRC-16 as claimed in claim 5 wherein: step 4, the method is realized by the following steps,
step 4.1, according to a generating polynomial G (x) of the CRC-CCITT check code, obtaining the relation between the multi-byte high throughput parallel CRC code and the single-byte high throughput parallel CRC code as follows:
Figure FDA0003592165980000023
Figure FDA0003592165980000024
represents the value of j-th register after shifting d times, j is 0,1, …, k-1, d is 1,2, …, n; m isjThe coefficients representing the generator polynomial having values determined by the generator polynomial G (x), i.e. mj＝1，j＝0，5，12，16；
Step 4.2, gd-1Represents the present state of the register, i.e. the unshifted state; g is a radical of formuladRepresenting the secondary state of the register, namely the state after shifting par times, and finishing par times of shifting by one time of calculation for the parallel architecture; order:
Figure FDA0003592165980000031
and 4.3, calculating the relation between the multi-byte high throughput parallel CRC code and the single-byte high throughput parallel CRC code according to the derivation formula in the step 4.1 and the specification in the step 4.2.
7. A method for high throughput parallel cyclic redundancy check based on CRC-16 as claimed in claim 6 wherein: step 5. in the present method,
initializing the parallel CRC check code, and recording as D _ nexti(n) known high throughput parallel CRC code and input information code sequence Ci(n), the relation between the multi-byte high throughput parallel CRC code and the single-byte high throughput parallel CRC code, and the formula for obtaining the parallel 16-way high throughput CRC code is:
Figure FDA0003592165980000032
wherein n has a value in the range of 0,1 … 15,
Figure FDA0003592165980000033
and
Figure FDA0003592165980000034
the relationship between the two is determined by the relationship between the multi-byte high throughput parallel CRC code and the one-byte high throughput parallel CRC code obtained in step 4, i.e., by
Figure FDA0003592165980000035
And gd-1The relationship in (1) is obtained.
CN202210381920.7A 2022-04-12 2022-04-12 High-throughput parallel cyclic redundancy check method based on CRC-16 Pending CN114726383A (en)

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