KR100291718B1 - Cyclic redundancy check code device - Google Patents

Abstract

PURPOSE: A CRC(Cyclic Redundancy Check Code) device is provided to realize the initial part of CRC generating polynomial expression while executing the CRC operation in a bite unit. CONSTITUTION: The device comprises a latch(11) outputting the data inputted in a bite unit with a delay by one clock, a first CRC processor(12) executing the CRC operation by a CRC generating polynomial expression and calculation by receiving the delayed data from the latch and the present data inputted in a bite unit, a second CRC processor(13) executing the CRC operation by a CRC generating polynomial expression and calculation by receiving the CRC data from the first CRC processor and the new data inputted in a bite unit, a multiplexer(14) selecting and outputting the output of first CRC processor if the CRC data is firstly inputted, and selecting and outputting the output of second CRC processor if the CRC data is not firstly inputted, and a latch(15) outputting the data selected by the multiplexer to the second CRC processor.

Description

Cyclic Redundancy Check Coding Device

The present invention relates to a cyclic redundancy check encoding apparatus applied to an Asynchronous Transmission Mode (ATM) terminal and the like, and more particularly, to a cyclic redundancy check encoding apparatus capable of performing cyclic redundancy check encoding in units of bytes.

In general, the Cyclic Redundancy Check Code (CRC) is a code used in a modified cyclic code for error detection and error correction, and is usually a duplicate code at the end of each data block. By inserting additional characters), you can check whether an error occurred.

In the above-described CRC encoding, conventionally, one bit of data is processed per clock or configured to perform parallel processing on a byte basis.

Therefore, there are many difficulties in practical implementation when applied to a system requiring fast data transfer when 1 bit of data is processed per clock, and CRC that does not break by byte when configured to process in bytes There was a problem that the first part of the generator polynomial could not be implemented.

An object of the present invention is to provide a cyclic redundancy check encoding apparatus capable of implementing even the first part of a CRC-generated polynomial when performing cyclic redundancy check encoding on a byte basis.

In order to achieve the above object, the present invention, a latch unit for delaying the output of the input byte unit by one clock; A first cyclic redundancy check code processor configured to receive data delayed by one clock and data of a byte unit currently input by the latch unit and perform cyclic redundancy check encoding by arithmetic processing with a generated polynomial; A second cyclic redundancy check code processor which receives the cyclic redundancy check coded data and newly input byte data and performs cyclic redundancy check encoding by arithmetic processing with a generated polynomial; When the cyclic redundancy check coded data is input for the first time, the output of the first cyclic redundancy check code processor is selected and output. If the cyclic redundancy check coded data is not the first input, the output of the second cyclic redundancy check code processor is selected. Output multiplexer; And a latch unit for outputting the data selected by the multiplexer to the cyclic redundancy check code processing unit.

Figure is a block diagram of a cyclic redundancy check encoding apparatus according to a preferred embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

11, 15: latch unit 12, 13: cyclic redundancy check code processing unit

14: Multiplexer

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram of a cyclic redundancy check encoding apparatus according to a preferred embodiment of the present invention, including a latch unit 11, a cyclic redundancy check code processing unit 12, a cyclic redundancy check code processing unit 13, a multiplexer 14 and The latch unit 15 is included.

Referring to the figure, the latch unit 11 delays the input 8-bit unit data by one clock, and outputs it to the cyclic redundancy check code processing unit 12, and the cyclic redundancy check processing unit 12 outputs 1 of the latch unit 11. After receiving the clock-delayed 8-bit data and the newly applied 8-bit data, the multiplexer 14 performs arithmetic processing by using a predetermined generation polynomial (G (x)) and an exclusive OR to make the data capable of error detection and error correction. Output to

In this case, the generation polynomial described above is a polynomial used to generate a block check charactor (BCC) in the CRC scheme. An operation processing by an exclusive logical sum divides the input data into a generation polynomial and outputs only the rest.

On the other hand, when the cyclic redundancy check coded data is input for the first time, the multiplexer 14 selects 10 bits of data output from the cyclic redundancy check code processor 12 and outputs the data to the latch unit 15 to the latch unit 15. The latched 10-bit data is output to the output terminal of the cyclic redundancy check encoding apparatus and input to the cyclic redundancy check code processor 13.

Accordingly, the cyclic redundancy check code processor 13 generates a 10-bit data output from the latch unit 15 and a newly generated 8-bit data, and then generates the polynomial used to generate the BCC in the CRC scheme. Divide by (G (x)) and output the remainder to the multiplexer 14.

In addition, the multiplexer 14 selects 10-bit data output from the cyclic redundancy check code processor 13 and outputs it to the latch unit 15 when the input of the cyclic redundancy check coded data is not first. ) Outputs 10-bit data to the output terminal of the cyclic redundancy check encoding apparatus and inputs it to the cyclic redundancy check code processor 13.

Therefore, since the present invention outputs the cyclic redundancy check coding using the 8-bit data currently input and the data immediately preceding the CRC-generated polynomial, even the first part of the CRC-generated polynomial that is not broken by byte unit is guaranteed. There is an effect that can be implemented.

Claims (1)

A latch unit 11 for delaying and outputting the input byte unit data by one clock; A first cyclic redundancy check code processor (12) which receives data delayed by one clock by the latch unit (11) and data of a byte unit currently input and performs cyclic redundancy check coding by arithmetic processing with a generated polynomial; A second cyclic redundancy check code processor (13) which receives the cyclic redundancy check coded data and newly input byte data and performs cyclic redundancy check encoding by arithmetic processing with a generated polynomial; When the cyclic redundancy check coded data is input for the first time, the output of the first cyclic redundancy check code processor 12 is selected and output. If the cyclic redundancy check coded data is not the first input, the second cyclic redundancy check code processor ( A multiplexer 14 which selects and outputs an output of 13); And a latch unit (15) for outputting the data selected by the multiplexer (14) to the cyclic redundancy check code processor (13).