CN101478314B - Reed-solomon coder-decoder and decoding method thereof - Google Patents
Reed-solomon coder-decoder and decoding method thereof Download PDFInfo
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- CN101478314B CN101478314B CN200810055606XA CN200810055606A CN101478314B CN 101478314 B CN101478314 B CN 101478314B CN 200810055606X A CN200810055606X A CN 200810055606XA CN 200810055606 A CN200810055606 A CN 200810055606A CN 101478314 B CN101478314 B CN 101478314B
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Abstract
The invention discloses a Reid-Solomon coder decoder and a decoding method thereof. The Reid-Solomon coder decoder comprises an adjoint polynomial coefficient calculation module, a buffer module, a wrong position and bit error valve calculation module and an error correction module, wherein, the adjoint polynomial coefficient calculation module is used for receiving code words which are needed to be decoded and calculate an adjoint polynomial coefficient; the buffer module is used for buffer-memorizing the received code words needed to be decoded; the wrong position and bit error valve calculation module is used for determining wrong positions and calculating bit error valves; and the error correction module is used for correcting the corresponding code words in the buffer module according to the wrong positions and the bit error valves. A circuit for implementing an IBM iterative algorithm is provided according to the IBM iterative algorithm. The circuit is used for calculating a wrong position polynomial coefficient and an error valve polynomial coefficient during the RS coding process; and the IBM iterative algorithm is adopted, so the finite field inverse operation is not needed, the hardware source consumption is lower, and the computing speed is faster. The Reid-Solomon coding decoding can be carried out in a system with higher running frequency.
Description
Technical field
The present invention relates to communication field, relate in particular to a kind of RS (Reed-Solomon Coder, Reed Solomon Coding) decoder and interpretation method.
Background technology
The RS sign indicating number is one type of BCH (Broad Cast Channel, broadcast channel) sign indicating number with very strong error correcting capability, also is the Algorithms of Algebraic Geometric Codes of a quasi-representative, and it is at first constructed in nineteen sixty by Reed (Reed) and Solomon (Suo Luomeng).In general application, the RS sign indicating number can be used as solid size and uses separately, and in the very abominable application of channel condition; Have like mobile communication, satellite communication etc. in the channel of multipath fading characteristic; Also can be used as outer sign indicating number provides error correcting capability stronger serial concatenation of codes, under the situation that does not increase very high coding and decoding complexity, can obtain high coding gain and the error correcting capability identical with long code like this; Modal a kind of structure be exactly with the RS sign indicating number as outer sign indicating number, convolution code is made the cascaded code of ISN.
As shown in Figure 1, show in the prior art work decoding flow process that realizes Reed Solomon Coding according to the BM iterative algorithm, this flow process comprises:
Among the step S101, ask the associated polynomial coefficient.After the RS decoding system is receiving code word, calculate 2t (for the individual associated polynomial coefficient of RS (n, k) decoding, t=(n-k)/2) by the code character that receives.
Among the step S102, draw errors present and improper value multinomial coefficient by the BM algorithm iteration.The 2t that utilization an is tried to achieve coefficient is tried to achieve error location polynomial and the polynomial coefficient of improper value respectively through the BM iterative algorithm, and two polynomial high order powers all are t.
Among the step S103, by error location polynomial Search Error position.Errors present to code word is searched for, and is about to represent all values substitution error location polynomial of codeword position, if the error location polynomial result is 0 then representes that this position is an error code position.
Among the step S104, by the corresponding improper value of improper value polynomial computation errors present.The corresponding improper value in mistake in computation position after having found error code position.
Among the step S105, at last wrong code word is carried out error correction.The key of above-mentioned RS decode procedure is to find the solution among the step S102 error location polynomial and improper value multinomial coefficient; For this part 1966 Berlekamp (Berlekamp) proposed can be by the polynomial iterative decoding algorithm in syndrome mistake in computation position; This has greatly accelerated to find the solution the speed of error location polynomial; This method is simple and be easy to realize, thereby has solved the problem of RS decoding from engineering, Mei Xi (Massey) relation of line of shortest length property shift register between comprehensively of having pointed out this algorithm and sequence in 1969; And simplify; Therefore, this decoding algorithm just is called BM (Berlekamp Massey, the iterative decoding algorithm of Berlekamp-Mei Xi).
Owing to have the inversion operation of confinement in the above-mentioned BM iterative algorithm; And a large amount of hardware resource arithmetic speed of inversion operation consumption is slow; As if being applied in the BM interative computation, it can cause bigger critical path delay; So developed the IBM algorithm of no inversion operation afterwards; This algorithm is equivalent on the result of original all multinomial coefficient iteration, be multiplied by simultaneously identical coefficient, and this result has improved the performance of decoding system on the basis that does not influence follow-up improper value corresponding by error location polynomial Search Error position and mistake in computation position and error code correction.IBM (Inverse-free Berlekamp Massey; The Berlekamp of no inversion operation-Mei Xi) algorithm is exactly to utilize the satisfied identity of error location polynomial, improper value multinomial and associated polynomial to carry out the process of iteration; After calculating the associated polynomial coefficient; Set initial errors present and improper value multinomial coefficient and begin iteration; Whether in the process of iteration each time, all want first mistake in computation position and the polynomial recruitment of improper value afterwards, be 0 to produce control signal corresponding, the renewal of control errors present and improper value multinomial coefficient according to this recruitment again; In the process of each iteration, all make errors present and the polynomial coefficient of improper value satisfy identity; And polynomial high reps does not subtract after guaranteeing each time iteration, passes through like this after certain iterations, just can obtain errors present and the polynomial coefficient of improper value that high order power meets the demands and meets identity.
Because traditional RS decoder is to decipher according to flow process shown in Figure 1, the key of its whole RS decoding system is that the BM iteration asks errors present, and this link of improper value.So, become the key of the whole RS decoding performance of influence to the implementation of this link.Owing to need complicated finite field inversion operation in the classical BM iterative algorithm, and the inversion operation of finite field consumes hardware resource and arithmetic speed is slow, the critical path time delay of system there is very big influence.Can not satisfy the needs of higher system running frequency.
Can know that to sum up existing Reed Solomon Coding decoding technique on reality is used, obviously exists inconvenience and defective, so be necessary to improve.
Summary of the invention
To above-mentioned defective, the object of the present invention is to provide a kind of Reed Solomon Coding decoder, to carry out Reed Solomon Coding decoding under the system that is implemented in higher running frequency.
To achieve these goals, the present invention provides a kind of Reed Solomon Coding decoder, comprising:
The associated polynomial coefficients calculation block is used to receive the code word of needs decoding, and calculates the associated polynomial coefficient;
Cache module is used for the code word of the needs decoding that buffer memory receives;
Errors present and error code values computing module are used for confirming errors present and calculate error code values;
Correction module is used for according to said errors present and error code values, the code word of correspondence in the said cache module of error correction.
According to Reed Solomon Coding decoder provided by the invention, said errors present and error code values computing module comprise:
The IBM algorithm is asked the error location polynomial coefficient module, is used to receive the input of the associated polynomial coefficient of said associated polynomial coefficients calculation block, mistake in computation position multinomial coefficient;
The IBM algorithm is asked improper value multinomial coefficient module, is used to receive the input of the associated polynomial coefficient of said associated polynomial coefficients calculation block, mistake in computation value multinomial coefficient;
Search Error position and calculating error code values module are used for the search of errors present, and the calculating of corresponding error code values.
According to Reed Solomon Coding decoder provided by the invention, said IBM algorithm is asked the error location polynomial coefficient module, and perhaps the IBM algorithm asks improper value multinomial coefficient module to comprise:
Many group registers are used for storing all kinds of numerical value of IBM iterative algorithm process;
First group of delay circuit, first registers through said many group registers are connected with second group of delay circuit, comprise the multiplier and the input summer more than that are linked in sequence successively;
Second group of delay circuit, first registers through said many group registers are connected with first group of delay circuit, comprise the multiplier and the input summer more than that are linked in sequence successively, and/or another multiplier;
Control circuit is connected with first register of said many group registers, is used for producing control signal according to the value of said first register output, to control the renewal of said many group register value.
According to Reed Solomon Coding decoder provided by the invention, said many group registers comprise:
T+1 shift register is connected with a multiplier of first group of delay circuit, the serial that is used to be shifted input syndrome multinomial coefficient;
T background register is connected with at least one multiplier of second group of delay circuit, is used for storing the intermediate object program that IBM iterative algorithm process is asked the error location polynomial coefficient; Perhaps be used for storing the intermediate object program that IBM iterative algorithm process is asked the improper value multinomial coefficient;
T+1 coefficient register, its two ends are connected with a multiplier of first group of delay circuit and second group of delay circuit respectively, are used to deposit the error location polynomial coefficient, perhaps the improper value multinomial coefficient;
First register, the one of which end is connected with the input summer more than of first group of delay circuit, and the other end is connected with at least one multiplier, second register, the peripheral control circuit of second group of delay circuit respectively; After being used for buffer memory the Reed Solomon Coding decoder carrying out a clock cycle of IBM iteration each time, the multinomial increment that the IBM iterative computation obtains; And
Second register, the one of which end is connected with at least one multiplier of second delay circuit, and the other end is connected with first register, is used to keep or upgrade the multinomial increment of said Reed Solomon Coding decoder;
Wherein, t=(n-k)/2; N represents code length, k representative information position number.
According to Reed Solomon Coding decoder provided by the invention, when said multinomial increment is 0 or when not satisfying the background register update condition, said control circuit produces signal and only makes t background register completion serial right-shift operation; Otherwise said control circuit produces signal upgrades t+1 coefficient register and t background register.
In order to realize above-mentioned another goal of the invention, the invention provides a kind of method of utilizing Reed Solomon Coding decoder provided by the invention to realize decoding, comprising:
The reception of associated polynomial coefficients calculation block needs the code word of decoding, and calculates the associated polynomial coefficient;
The code word of needs that cache module receives decoding is also carried out buffer memory to it;
Errors present and error code values computing module are confirmed errors present and are calculated error code values;
Correction module is according to said errors present and error code values, corresponding code word in the said cache module of error correction.
According to utilizing Reed Solomon Coding decoder provided by the invention to realize the method for decoding, said errors present and error code values computing module confirm that the step of errors present and calculating error code values comprises:
The IBM algorithm asks the error location polynomial coefficient module to receive the input of the associated polynomial coefficient of said associated polynomial coefficients calculation block, mistake in computation position multinomial coefficient;
The IBM algorithm asks improper value multinomial coefficient module to receive the input of the associated polynomial coefficient of said associated polynomial coefficients calculation block, mistake in computation value multinomial coefficient;
Search Error position and calculating error code values module are carried out the search of errors present, and the calculating of corresponding error code values.
Realize the method for decoding according to utilizing Reed Solomon Coding decoder provided by the invention; Said IBM algorithm asks the error location polynomial coefficient module to receive the input of the associated polynomial coefficient of said associated polynomial coefficients calculation block, the step of mistake in computation position multinomial coefficient; Perhaps, the IBM algorithm asks improper value multinomial coefficient module to receive the input of the associated polynomial coefficient of said associated polynomial coefficients calculation block, the step of mistake in computation value multinomial coefficient; Comprise:
(1) the Reed Solomon Coding decoder circuit is carried out initialization;
(2) carry out first clock cycle of IBM iteration at Reed Solomon Coding decoder each time, the said t+1 shift register serial input associated polynomial coefficient that will be shifted;
(3) multiplier and the numerical value in t+1 coefficient register of the associated polynomial coefficient in t+1 shift register through first group of delay circuit multiplies each other; And the adder addition of passing through the input more than of first group of delay circuit; Obtain the multinomial increment, and deposit in said first register;
(4) to carry out second clock cycle of iteration interim when Reed Solomon Coding decoder each time; According to the multinomial increment in said first register; Control circuit produces control signal corresponding, and t background register, a t+1 shift register and t+1 coefficient register are upgraded.
According to utilizing Reed Solomon Coding decoder provided by the invention to realize the method for decoding, said step (1) comprising:
(11) numerical value in the associated polynomial coefficient in initialization t+1 shift register, the numerical value in the t+1 coefficient register and t the background register; And the initial value in said second register is initialized as 1;
Said step (4) comprising:
(41) to carry out second clock cycle of iteration interim when Reed Solomon Coding decoder each time, and according to the multinomial increment in said first register, control circuit produces control signal corresponding:
When the multinomial increment is not equal to 0; And when satisfying the condition of t background register renewal; Control circuit produces control signal; Value in t+1 in the time of the thus coefficient register is upgraded t background register, and the value in t+1 coefficient register is also exported renewal through an adder in second group of delay circuit;
When the multinomial increment equals 0, the value in t the background register is carried out the serial right-shift operation, and lowest order fills out 0, the value in t+1 coefficient register is exported through an adder of second group of delay circuit and is upgraded simultaneously.
Realize the method for decoding according to utilizing Reed Solomon Coding decoder provided by the invention; The said utilization in the process that the Reed Solomon Coding decoder realizes decoding; The IBM iteration repeats to accomplish the IBM iteration 2t time, obtains the error location polynomial coefficient value, perhaps improper value system of polynomials numerical value; T=(n-k)/2 wherein; N represents code length, k representative information position number.
The present invention provides the circuit of realizing the IBM iterative algorithm according to the IBM iterative algorithm.This circuit can be used for carrying out the error location polynomial coefficient in the RS decode procedure; And the calculating of improper value multinomial coefficient; Because adopt the IBM iterative algorithm, so the inversion operation of its no finite field is lower to the consumption of hardware resource; And fast operation does not have influence to the critical path time delay of system.Can be implemented in and carry out Reed Solomon Coding decoding under the higher running frequency system.
Description of drawings
Fig. 1 is a work decoding flow chart of realizing Reed Solomon Coding in the prior art according to the BM iterative algorithm;
The structural representation of the decoder of Fig. 2 Reed Solomon Coding that to be the present invention provide according to the IBM iterative algorithm;
Fig. 3 is the structural representation of the decoder of the Reed Solomon Coding that provides according to the IBM iterative algorithm in the one embodiment of the invention;
Fig. 4 A～Fig. 4 B is that the IBM algorithm in the one embodiment of the invention asks error location polynomial coefficient module and IBM algorithm to ask improper value multinomial coefficient modular structure sketch map:
Fig. 5 is that the IBM algorithm in the one embodiment of the invention asks error location polynomial coefficient module and IBM algorithm to ask the structural representation of improper value multinomial coefficient module,
Fig. 6 utilizes Reed Solomon Coding decoder provided by the present invention to realize the method flow diagram of decoding.
Embodiment
In order to make the object of the invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
Basic thought of the present invention is: according to the IBM iterative algorithm, the circuit of realizing the IBM iterative algorithm is provided, to be implemented in the RS decoding in the upper frequency system.
The structural representation of the decoder of Fig. 2 Reed Solomon Coding that to be the present invention provide according to the IBM iterative algorithm; The decoder 2 of this Reed Solomon Coding has comprised:
Associated polynomial coefficients calculation block 21 is used to receive the code word of needs decoding, and calculates the associated polynomial coefficient;
Errors present and error code values computing module 23 are used for confirming errors present and calculate error code values;
Fig. 3 is the structural representation of the decoder of the Reed Solomon Coding that provides according to the IBM iterative algorithm in the one embodiment of the invention; In this embodiment, errors present and error code values computing module 23 comprise described in the said Reed Solomon Coding decoder 2:
The IBM algorithm is asked error location polynomial coefficient module 231, is used to receive the input of the associated polynomial coefficient of said associated polynomial coefficients calculation block 21, mistake in computation position multinomial coefficient;
The IBM algorithm is asked improper value multinomial coefficient module 232, is used to receive the input of the associated polynomial coefficient of said associated polynomial coefficients calculation block 21, mistake in computation value multinomial coefficient;
Search Error position and calculating error code values module 233 are used for the search of errors present, and the calculating of corresponding error code values.In one embodiment of the invention; Its IBM algorithm asks error location polynomial coefficient module 231 and IBM algorithm to ask improper value multinomial coefficient module 232; Can be designed as a module; Realize its function, the improper value multinomial coefficient of enter code word and improper value multinomial coefficient with equal circuit to calculate.
Fig. 4 A～Fig. 4 B is that the IBM algorithm asks error location polynomial coefficient module and IBM algorithm to ask improper value multinomial coefficient modular structure sketch map in the one embodiment of the invention, and the IBM algorithm asks error location polynomial coefficient module 231 and IBM algorithm to ask improper value multinomial coefficient module 232 to comprise:
Many group registers 2311 are used for storing all kinds of numerical value of IBM iterative algorithm process; In whole decode procedure, need to produce multiclass numerical value.Comprise associated polynomial coefficient, improper value multinomial coefficient, error location polynomial coefficient etc.Many groups register 2311 among the present invention is used for such numerical value is stored.
First group of delay circuit 2312, first registers 23114 through said many group registers 2311 are connected with second group of delay circuit 2313, comprise the multiplier 23121 and the input summer 23122 more than that are linked in sequence successively;
Second group of delay circuit 2313; First register 23114 through said many group registers 2311 is connected with first group of delay circuit 2312; Comprise the multiplier 23131 and the input summer 23132 more than that are linked in sequence successively, and/or another multiplier 23133;
Control circuit 2114 is connected with first register 23114 of said many group registers 2311, is used for producing control signal according to the value of said first register 23114 outputs, to control the renewal of said many group register 2311 numerical value.
Fig. 5 is that the IBM algorithm in the one embodiment of the invention asks error location polynomial coefficient module and IBM algorithm to ask the structural representation of improper value multinomial coefficient module, and wherein said many group registers 2311 comprise:
T+1 shift register 23111 is connected with a multiplier 23121 of first group of delay circuit 2312, the serial that is used to be shifted input syndrome multinomial coefficient;
T+1 coefficient register 23113, its two ends connect with the multiplier (23121,23131) of first group of delay circuit 2312 and second group of delay circuit 2313 respectively, are used to deposit the error location polynomial coefficient, perhaps the improper value multinomial coefficient; Because this circuit can practicality be asked error location polynomial coefficient and improper value multinomial coefficient; Therefore, this t+1 coefficient register 23113 can be stored above-mentioned two kinds of coefficients.
Second register 23115, the one of which end is connected with at least one multiplier 23131 of second delay circuit 2313, and the other end is connected with first register 23114, is used to keep or upgrade the multinomial increment of said Reed Solomon Coding decoder 2; Wherein, t=(n-k)/2; N represents code length, k representative information position number.
In one embodiment of the invention, when said multinomial increment be 0 or when not satisfying background register 23112 update condition, said control circuit 2314 produces signals and only makes t background register 23112 completion serial right-shift operation; Otherwise said control circuit 2314 produces signal upgrades t+1 coefficient register 23113 and t background register 23112.
As shown in Figure 5, in one embodiment of the invention,, the maximum order of error location polynomial σ (x) (, therefore needs t+1 coefficient register 23113 (σ for RS (n, k) decoding, t=(n-k)/2) because being t
0, σ
1... σ
t) coefficient of storage multinomial σ (x) from constant term to high order power.Simultaneously, also need t background register 23112 (B in order to accomplish the IBM algorithm
0To B
T-1) intermediate object program of error location polynomial σ (x) coefficient in the storage iterative process.In addition, also need t+1 shift register 23111 (R
0To R
t) come serial to import the coefficient S of associated polynomial
1To S
2tIn first clock cycle of IBM interative computation each time, successively will be from S
1To S
2tIn coefficient move into the R of shift register group 23111
0To R
t, this moment R
0To R
tIn value and the σ of coefficient register 23112
0, σ
1... σ
tMiddle numerical value multiplies each other through multiplier 23121, and the result has calculated multinomial increment D through the adder 23122 of input more than
j, this increment deposits first register 23114 in.
Afterwards when second clock of each iteration arrives, with multinomial increment D
jOutput from first register 23114, this moment, control circuit 2314 was according to D
jValue judge the generation control signal, work as D
jBe not equal to 0, and satisfy and upgrade t background register 23112 (B
0To B
T-1) condition the time, control circuit 2314 produces control signals, the σ in the time of thus
0, σ
1... σ
tIn value to t background register 23112 (B
0To B
T-1) upgrade.And while σ
0, σ
1... σ
tIn value also upgrade through the output of corresponding adder 23132; Otherwise, to t background register 23112 (B
0To B
T-1) carry out the serial right-shift operation, and lowest order fills out 0, while σ
0, σ
1... σ
tIn value remain unchanged.
In another one embodiment of the present invention, with the error location polynomial factor sigma
tAccomplish and once be updated to example analysis, σ
tCoefficient register multiplies each other via the numerical value in multiplier 23121 and the shift register 23111, and result of calculation obtains multinomial increment D via many input summers 23122
j, multiplying each other through multiplier 23131 or 23133 again, multiplied result is sent σ back to through two input summers 23132
tRegister carries out the renewal of coefficient.
It is thus clear that, on this path, comprising adder 23122 and one two adder of importing 23115 that two multipliers (23121,23131 or 23133) are imported one more, the delay in its path is long.But because the present invention inserted first register 23114 on this critical path, the delay in path has been divided into two parts, a part postpones to comprise input summer 23122 more than, and a multiplier 23121; Another part postpones to comprise a multiplier 23131 or 23133, and the adder 23132 of one two input.Because the delay of the adder 23122 of many inputs is greater than the adder 23132 of two inputs, so make entire I BM realize that the critical path of circuit has become input summer 23122 more than and the combination that multiplier 23121 postpones.Like this, make this circuit under the higher system frequency, to realize decoding to the RS coding codeword.
In the present invention, according to the requirement of related protocol regulation, system supports RS (240,224), RS (240,192), three kinds of decoding modes of RS (240,176), and requires the RS decoder can run to the system frequency of 100MHz at least.If the BM algorithm according in traditional RS decoding designs, the highest frequency of system's operation does not reach requirement, and the present invention adopts the IBM algorithm, can under the higher system running frequency, realize RS decoding.
Fig. 6 utilizes Reed Solomon Coding decoder provided by the present invention to realize the method flow diagram of decoding, and wherein, step S601 and step S602 do not have the branch of precedence, and this flow process comprises the steps:
In step S601,21 receptions of associated polynomial coefficients calculation block need the code word of decoding, and calculate the associated polynomial coefficient.In one embodiment of the invention, when carrying out RS (240,224) decoding, at first utilize enter code word to carry out the calculating of associated polynomial coefficient by associated polynomial coefficients calculation block 21 like system.And when calculating the 16 (coefficient S of the individual associated polynomial of t=(240-224)/2=8) this moment
1To S
2tAfterwards, just with these 16 associated polynomial coefficients from S
1To S
2tDisplacement is input to the IBM algorithm and asks error location polynomial coefficient module 231, and the IBM algorithm is asked in the improper value multinomial coefficient module 232.
In step S602, the code word of needs that cache module 22 receives decoding is also carried out buffer memory to it; Cache module 22 is saved in enter code word in the cache module 22 successively.
In step S603, errors present and error code values computing module 23 are confirmed errors present and are calculated error code values.
In step S604, correction module 24 is according to said errors present and error code values, corresponding code word in the said cache module 22 of error correction.
In one embodiment of the invention; Said step S603 may further comprise the steps: the IBM algorithm is asked the input of the associated polynomial coefficient of the said associated polynomial coefficients calculation block 21 of error location polynomial coefficient module 231 receptions, mistake in computation position multinomial coefficient; The IBM algorithm is asked the input of the associated polynomial coefficient of the said associated polynomial coefficients calculation block 21 of improper value multinomial coefficient module 232 receptions, mistake in computation value multinomial coefficient; Search Error position and calculating error code values module 24 are carried out the search of errors present, and the calculating of corresponding error code values.
In another embodiment of the present invention, said IBM algorithm is asked the input of the associated polynomial coefficient of the said associated polynomial coefficients calculation block 21 of error location polynomial coefficient module 231 receptions, the step of mistake in computation position multinomial coefficient; Perhaps, the IBM algorithm is asked the input of the associated polynomial coefficient of the said associated polynomial coefficients calculation block 21 of improper value multinomial coefficient module 232 receptions, the step of mistake in computation value multinomial coefficient; Comprise:
(1) Reed Solomon Coding decoder 2 circuit is carried out initialization; Code translator is before deciphering, and preliminary examinationization need power on.
(2) carry out first clock cycle of IBM iteration at Reed Solomon Coding decoder 2 each time, a said t+1 shift register 23111 serial input associated polynomial coefficient that will be shifted; RS deciphers the system clock that each iteration needs two cycles, and promptly per two system clocks are with an associated polynomial coefficient S
1To S
16From left to right be displaced to t+1 shift register 23111 (R successively
0, R
1... R
t) in, R in first system clock
0To R
tIn value and t+1 coefficient register 23113 (σ
0, σ
1... σ
t) in value multiply each other through multiplier 23121, the result calculates through the adder 23122 of input more than, just can obtain multinomial increment D
j, this multinomial increment deposits first register 23114 in.
(3) the associated polynomial coefficient in t+1 shift register 23111 multiplies each other through a multiplier 23121 of first group of delay circuit 2312 and numerical value in t+1 the coefficient register 23113; And adder 23122 additions of passing through the input more than of first group of delay circuit 2312, obtain multinomial increment D
j, and deposit in said first register 23114;
(4) to carry out second clock cycle of iteration interim when Reed Solomon Coding decoder 2 each time; According to the multinomial increment in said first register 23114; Control circuit 2314 produces control signal corresponding, and t background register 23112, a t+1 shift register 23111 and t+1 coefficient register 23113 are upgraded.
In another embodiment of the present invention, said step (1) comprising:
(11) numerical value in the associated polynomial coefficient in initialization t+1 shift register 2311, the numerical value in the t+1 coefficient register and t the background register 23121; And the initial value in said second register 23115 is initialized as 1.
In one embodiment of the invention, as shown in Figure 5, at first circuit carries out initialization, t+1 shift register 23111 (R
0To R
t) in content be initialized as (R
0, R
1... R
t)=(S
1, 0 ..., 0), while t+1 coefficient register 23113 (σ
0, σ
1... σ
t) and t background register (B
0To B
T-1) in content be initialized as (σ
0, σ
1... σ
t)=(1,0 ..., 0) and (R
0, R
1... R
t)=(S
1, 0 ..., 0), the content in second register 23115 (γ) is initialized as 1.
Said step (4) comprising:
(41) to carry out second clock cycle of iteration interim when Reed Solomon Coding decoder 2 each time, and according to the multinomial increment in said first register 23114, control circuit 2314 produces control signal corresponding:
When the multinomial increment is not equal to 0; And when satisfying the condition of t background register 23112 renewals; Control circuit 2314 produces control signal; Value in t+1 in the time of the thus coefficient register 23113 is upgraded t background register 23112, and the value in t+1 coefficient register 23113 is also exported renewal through an adder 23132 in second group of delay circuit 2313;
When the multinomial increment equals 0; Value in t the background register 23112 is carried out the serial right-shift operation; And lowest order fills out 0, and the value in while t+1 coefficient register 23113 is exported through an adder 23132 of second group of delay circuit 2313 and upgraded.
When second clock of each iteration arrives, with multinomial increment D
jOutput from first register 23114, this moment, control circuit 2314 was according to D
jValue judge the generation control signal, work as D
jBe not equal to 0, and satisfy and upgrade t background register 23112 (B
0To B
T-1) condition the time, control circuit 23114 produces control signals, the σ in the time of thus
0, σ
1... σ
tIn value to t background register 23112 (B
0To B
T-1) upgrade.And while σ
0, σ
1... σ
tIn value also upgrade through the output of corresponding adder 23132, otherwise, to t background register 23112 (B
0To B
T-1) carry out right-shift operation, and lowest order fills out 0, while σ
0, σ
1... σ
tIn value upgrade through the output of corresponding adder 23121.In two above-mentioned clock cycle, this circuit has been accomplished iterative operation one time.
In above-mentioned a plurality of embodiment, the said Reed Solomon Coding decoder 2 that utilizes realizes that the IBM iteration repeats to accomplish the IBM iteration 2t time in the process of decoding, obtains the error location polynomial coefficient value, perhaps improper value system of polynomials numerical value; T=(n-k)/2 wherein; N represents code length, k representative information position number.
This process repeats under the control of control circuit, up to iteration repeat to accomplish 16 times (algorithm dictates iteration 2t time, this moment t=(240-224)/2=8), this moment, the IBM iterative algorithm stopped, t+1 coefficient register 23113 (σ
0, σ
1..., σ
t) in numerical value be the error location polynomial coefficient value of being asked, perhaps improper value system of polynomials numerical value.
, the IBM iteration just can ask error location polynomial coefficient module 231 and IBM algorithm to ask improper value multinomial coefficient module 232 after finishing by the IBM algorithm with the error location polynomial coefficient that obtains; And the improper value multinomial coefficient is exported to the Search Error position and is calculated error code values module 233; Carry out the search of errors present and the calculating of the corresponding error code values of errors present; When the intact position of every detection whether wrong and calculated the corresponding error value after; The corresponding enter code word that just is stored in the cache module 22 by 24 pairs of correction module carries out error correction; And the code word after the corresponding decoding of output, after all code word error correction are finished, just accomplish whole RS decoded operation.
Above-mentioned scheme can be used for the design of RS decoding system fully, and can realize with FPGA (FieldProgrammable Gate Array, field programmable gate array) hardware, has accomplished the real-time processing of decoding.Any technical staff of this area above-mentionedly provide detailed embodiment to describe, so that can use or utilize the present invention.Embodiment shown in the present invention is not only applicable to here, and be applicable to different mode and the design of RS decoding system that system's running frequency is had relatively high expectations.
In sum, the present invention provides the circuit of realizing the IBM iterative algorithm according to the IBM iterative algorithm.This circuit can be used for carrying out the error location polynomial coefficient in the RS decode procedure; And the calculating of improper value multinomial coefficient; Because adopt the IBM iterative algorithm, so the inversion operation of its no finite field is lower to the consumption of hardware resource; And fast operation does not have influence to the critical path time delay of system.Can be implemented in and carry out Reed Solomon Coding decoding under the higher running frequency system.
Certainly; The present invention also can have other various embodiments; Under the situation that does not deviate from spirit of the present invention and essence thereof; Those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (7)
1. a Reed Solomon Coding decoder is characterized in that, comprising:
The associated polynomial coefficients calculation block is used to receive the code word of needs decoding, and calculates the associated polynomial coefficient;
Cache module is used for the code word of the needs decoding that buffer memory receives;
Errors present and error code values computing module are used for confirming errors present and calculate error code values;
Correction module is used for according to said errors present and error code values, the code word of correspondence in the said cache module of error correction;
Said errors present and error code values computing module comprise:
The IBM algorithm is asked the error location polynomial coefficient module, is used to receive the input of the associated polynomial coefficient of said associated polynomial coefficients calculation block, mistake in computation position multinomial coefficient;
The IBM algorithm is asked improper value multinomial coefficient module, is used to receive the input of the associated polynomial coefficient of said associated polynomial coefficients calculation block, mistake in computation value multinomial coefficient;
Search Error position and calculating error code values module are used for the search of errors present, and the calculating of corresponding error code values;
Said IBM algorithm is asked the error location polynomial coefficient module, and perhaps the IBM algorithm asks improper value multinomial coefficient module to comprise:
Many group registers are used for storing all kinds of numerical value of IBM iterative algorithm process;
First group of delay circuit, first registers through said many group registers are connected with second group of delay circuit, comprise the multiplier and the input summer more than that are linked in sequence successively;
Second group of delay circuit, first registers through said many group registers are connected with first group of delay circuit, comprise the multiplier and the input summer more than that are linked in sequence successively, and/or another multiplier;
Control circuit is connected with first register of said many group registers, is used for producing control signal according to the value of said first register output, to control the renewal of said many group register value;
Wherein, IBM is the Berlekamp-Mei Xi of no inversion operation.
2. Reed Solomon Coding decoder according to claim 1 is characterized in that, said many group registers comprise:
T+1 shift register is connected with a multiplier of first group of delay circuit, the serial that is used to be shifted input syndrome multinomial coefficient;
T background register is connected with at least one multiplier of second group of delay circuit, is used for storing the intermediate object program that IBM iterative algorithm process is asked the error location polynomial coefficient; Perhaps be used for storing the intermediate object program that IBM iterative algorithm process is asked the improper value multinomial coefficient;
T+1 coefficient register, its two ends are connected with a multiplier of first group of delay circuit and second group of delay circuit respectively, are used to deposit the error location polynomial coefficient, perhaps the improper value multinomial coefficient;
First register, the one of which end is connected with the input summer more than of first group of delay circuit, and the other end is connected with at least one multiplier, second register, the peripheral control circuit of second group of delay circuit respectively; After being used for buffer memory Reed one Saloman coder-decoder carrying out a clock cycle of IBM iteration each time, the multinomial increment that the IBM iterative computation obtains; And
Second register, the one of which end is connected with at least one multiplier of second delay circuit, and the other end is connected with first register, is used to keep or upgrade the multinomial increment of said Reed Solomon Coding decoder;
Wherein, t=(n-k)/2; N represents code length, k representative information position number.
3. Reed Solomon Coding decoder according to claim 2 is characterized in that, when said multinomial increment is 0 or when not satisfying the background register update condition, said control circuit produces signal and only makes t background register completion serial right-shift operation; Otherwise said control circuit produces signal upgrades t+1 coefficient register and t background register.
4. a method of utilizing claim 2 or 3 described Reed Solomon Coding decoders to realize decoding is characterized in that, comprising:
The reception of associated polynomial coefficients calculation block needs the code word of decoding, and calculates the associated polynomial coefficient;
The code word of needs that cache module receives decoding is also carried out buffer memory to it;
Errors present and error code values computing module are confirmed errors present and are calculated error code values;
Correction module is according to said errors present and error code values, corresponding code word in the said cache module of error correction;
Said errors present and error code values computing module confirm that the step of errors present and calculating error code values comprises:
The IBM algorithm asks the error location polynomial coefficient module to receive the input of the associated polynomial coefficient of said associated polynomial coefficients calculation block, mistake in computation position multinomial coefficient;
The IBM algorithm asks improper value multinomial coefficient module to receive the input of the associated polynomial coefficient of said associated polynomial coefficients calculation block, mistake in computation value multinomial coefficient;
Search Error position and calculating error code values module are carried out the search of errors present, and the calculating of corresponding error code values;
Said IBM algorithm asks the error location polynomial coefficient module to receive the input of the associated polynomial coefficient of said associated polynomial coefficients calculation block; The step of mistake in computation position multinomial coefficient; Perhaps; The IBM algorithm asks improper value multinomial coefficient module to receive the input of the associated polynomial coefficient of said associated polynomial coefficients calculation block, and the step of mistake in computation value multinomial coefficient comprises:
(1) the Reed Solomon Coding decoder circuit is carried out initialization;
(2) carry out first clock cycle of IBM iteration at Reed Solomon Coding decoder each time, t+1 shift register serial input associated polynomial coefficient that will be shifted;
(3) multiplier and the numerical value in t+1 coefficient register of the associated polynomial coefficient in t+1 shift register through first group of delay circuit multiplies each other; And the adder addition of passing through the input more than of first group of delay circuit; Obtain the multinomial increment, and deposit in said first register;
(4) to carry out second clock cycle of iteration interim when Reed Solomon Coding decoder each time; According to the multinomial increment in said first register; Control circuit produces control signal corresponding, and t background register, a t+1 shift register and t+1 coefficient register are upgraded;
Wherein, t=(n-k)/2; N represents code length, k representative information position number.
5. Reed Solomon Coding decoder according to claim 4 is realized the method for decoding, it is characterized in that said step (1) comprising:
(11) numerical value in the associated polynomial coefficient in initialization t+1 shift register, the numerical value in the t+1 coefficient register and t the background register; And the initial value in said second register is initialized as 1;
Said step (4) comprising:
(41) to carry out second clock cycle of iteration interim when Reed Solomon Coding decoder each time, and according to the multinomial increment in said first register, control circuit produces control signal corresponding:
When the multinomial increment is not equal to 0; And when satisfying the condition of t background register renewal; Control circuit produces control signal; Value in t+1 in the time of the thus coefficient register is upgraded t background register, and the value in t+1 coefficient register is exported renewal through an adder in second group of delay circuit;
When the multinomial increment equals 0, the value in t the background register is carried out the serial right-shift operation, and lowest order fills out 0, the value in t+1 coefficient register is exported renewal through an adder of second group of delay circuit simultaneously.
6. Reed Solomon Coding decoder according to claim 5 is realized the method for decoding; It is characterized in that; The said utilization in the process that the Reed Solomon Coding decoder realizes decoding; The IBM iteration repeats to accomplish the IBM iteration 2t time, obtains the error location polynomial coefficient value, perhaps improper value system of polynomials numerical value.
7. a method of utilizing the described Reed Solomon Coding decoder of claim 1 to realize decoding is characterized in that, comprising:
The reception of associated polynomial coefficients calculation block needs the code word of decoding, and calculates the associated polynomial coefficient;
The code word of needs that cache module receives decoding is also carried out buffer memory to it;
Errors present and error code values computing module are confirmed errors present and are calculated error code values;
Correction module is according to said errors present and error code values, corresponding code word in the said cache module of error correction;
Said errors present and error code values computing module confirm that the step of errors present and calculating error code values comprises:
The IBM algorithm asks the error location polynomial coefficient module to receive the input of the associated polynomial coefficient of said associated polynomial coefficients calculation block, mistake in computation position multinomial coefficient;
The IBM algorithm asks improper value multinomial coefficient module to receive the input of the associated polynomial coefficient of said associated polynomial coefficients calculation block, mistake in computation value multinomial coefficient;
Search Error position and calculating error code values module are carried out the search of errors present, and the calculating of corresponding error code values;
Said IBM algorithm asks the error location polynomial coefficient module to receive the input of the associated polynomial coefficient of said associated polynomial coefficients calculation block; The step of mistake in computation position multinomial coefficient; Perhaps; The IBM algorithm asks improper value multinomial coefficient module to receive the input of the associated polynomial coefficient of said associated polynomial coefficients calculation block, and the step of mistake in computation value multinomial coefficient comprises:
(1) the Reed Solomon Coding decoder circuit is carried out initialization;
(2) carry out first clock cycle of IBM iteration at Reed Solomon Coding decoder each time, t+1 shift register serial input associated polynomial coefficient that will be shifted;
(3) multiplier and the numerical value in t+1 coefficient register of the associated polynomial coefficient in t+1 shift register through first group of delay circuit multiplies each other; And the adder addition of passing through the input more than of first group of delay circuit; Obtain the multinomial increment, and deposit in said first register;
(4) to carry out second clock cycle of iteration interim when Reed Solomon Coding decoder each time; According to the multinomial increment in said first register; Control circuit produces control signal corresponding, and t background register, a t+1 shift register and t+1 coefficient register are upgraded;
Wherein, t=(n-k)/2; N represents code length, k representative information position number.
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| CN101695002B (en) * | 2009-10-13 | 2013-07-10 | 苏州国芯科技有限公司 | Coding circuit based on Reed-Solomon code |
| CN101697490B (en) * | 2009-10-16 | 2013-09-25 | 苏州国芯科技有限公司 | Decoding method applied to Reed-Solomon code-based ECC module |
| CN101695015B (en) * | 2009-10-30 | 2013-01-16 | 烽火通信科技股份有限公司 | RS decoder and decoding method for EPON system |
| CN102323913B (en) * | 2011-09-01 | 2014-08-20 | 记忆科技(深圳)有限公司 | Data readout method and system for solid state disk |
| CN103023517B (en) * | 2012-12-28 | 2016-06-08 | 北京格林伟迪科技股份有限公司 | A kind of Reed-Solomon code decoding scheme |
| CN107017962B (en) | 2016-01-28 | 2020-01-21 | 华为技术有限公司 | Coding method and coder-decoder for dynamic power consumption control |
| US10459783B2 (en) * | 2016-08-30 | 2019-10-29 | Marvell World Trade Ltd. | Low-latency decoder for Reed Solomon codes |
| CN106961282A (en) * | 2017-03-31 | 2017-07-18 | 山东超越数控电子有限公司 | A kind of Hardware Implementation of the High Speed I BM algorithm structures based on binary BCH code |
| CN109412746B (en) | 2017-08-15 | 2021-01-05 | 深圳市海思半导体有限公司 | Data processing method and related device |
| CN107565981A (en) * | 2017-09-26 | 2018-01-09 | 天津光电通信技术有限公司 | A kind of RS coder implementation methods based on FPGA |
| CN111162799B (en) * | 2019-12-27 | 2023-08-29 | 北京时代民芯科技有限公司 | Anti-radiation RS code decoding circuit |
| CN113395137B (en) * | 2021-06-08 | 2023-04-25 | 龙迅半导体（合肥）股份有限公司 | FEC coding and decoding module |
| CN116961823A (en) * | 2022-04-19 | 2023-10-27 | 华为技术有限公司 | Data processing method and device |
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