CN108564983A - A kind of LDPC test platforms for NAND FLASH - Google Patents
A kind of LDPC test platforms for NAND FLASH Download PDFInfo
- Publication number
- CN108564983A CN108564983A CN201810315076.1A CN201810315076A CN108564983A CN 108564983 A CN108564983 A CN 108564983A CN 201810315076 A CN201810315076 A CN 201810315076A CN 108564983 A CN108564983 A CN 108564983A
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- nand flash
- information
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- ldpc
- check
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- 239000011159 matrix material Substances 0.000 claims description 7
- 238000001514 detection method Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/20—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits using counters or linear-feedback shift registers [LFSR]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56008—Error analysis, representation of errors
Abstract
The invention discloses a kind of LDPC test platforms for NAND FLASH, which first generates the random number of certain length, and FLASH is written in random number and check information, then reads FLASH and be sent into decoder for decoding, last mistake of statistics information.
Description
Technical field
The invention belongs to IC design field, the test of specifically a kind of LDPC for NAND FLASH is flat
Platform.
Background technology
With the progress of NAND FLASH techniques, more and more NAND FLASH need LDPC to carry out error correction.However
LDPC for NAND FLASH does not have the check matrix of standard and its corresponding generator matrix, and the structure of check matrix
It makes there are many kinds of methods, how to verify the performance of each matrix, it is necessary to a test platform.
Invention content
Present invention aim to address the test problems of the LDPC for NAND FLASH, provide a kind of for NAND
The test platform of the LDPC of FLASH.
In order to solve the above technical problems, the present invention provides a kind of test platform of the LDPC for NAND FLASH, packet
It includes
Random-number-generating module, message length as needed generation random number,
Coding module, according to the message length of input and matrix generate check information,
NAND FLASH control modules, for carrying out data exchange with NAND FLASH, NAND FLASH controllers are letter
Cease position and check bit write-in FLASH,
Decoding module translates the hard information and soft information data feeding read from FLASH
For code device into row decoding, input is hard information and soft information, output the result is that hard
Information and
Error code detection module is used for mistake of statistics information, compares the data of the data and random generator after decoding, statistics
The bit error rate.
The random-number-generating module uses LFSR structures, including several registers, and the initial value of the register is 0
Or 1.
The random-number-generating module obtains the random number for the period being 128.
The coding module includes shift register and summation circuit using SARR structures.
The NAND FLASH control modules include hard information and the soft information FLASH
It reads out and is sent into decoding module into the write-in of the reading control section of row decoding, the information bit that coding module is sent into and check bit
The erasing control section of NAND FLASH write control section and realize the block erasing to NAND FLASH.
The decoding module includes input module, output module, storage unit, variable node calculating list using NMS decodings
Member and check node calculation unit, variable node computing unit are responsible for the update of variable node, and check node calculation unit is responsible for
The intermediate result of the update of check-node, each iteration is stored in memory cell.
Error code detection module includes comparator and UART modules, the comparator be responsible for comparing the data of randomizer and
Decoded data, and number of errors is counted, UART is responsible for the information of number of errors to be sent to the ends PC.
Description of the drawings
Fig. 1 is the module map of the present invention；
Fig. 2 is LFSR structure charts；
Fig. 3 is SARR structure charts；
Fig. 4 is NAND FLASH controller schematic diagrames；
Fig. 5 is decoder architecture figure；
Fig. 6 is error detection structural schematic diagram.
Specific implementation mode
The present invention is further described below in conjunction with the accompanying drawings.
The present invention provides a kind of LDPC test platforms for NAND FLASH, which first generates certain length
Random number, FLASH is written in random number and check information, then read FLASH and be sent into decoder for decoding, last mistake of statistics letter
Breath.
The implementation of the invention specifically includes following steps：
Step 1, the generation of random number.Random number, which generates, uses LFSR structures shown in Fig. 2, message length as needed
Random number is generated, the initial value of each register can be 0 or 1, obtain the random number that the period is 128.
Step 2, it encodes.Encoder uses SARR shown in Fig. 3 (shift-register-adder-accumulator)
Structure, SARR circuits are that core realizes vector and multiplication of matrices using shift register and summation circuit, are considerably reduced
Operand and resource consumption are conducive to the hardware realization of encoder.Check information is generated according to the message length of input and matrix.
Step 3 and the data exchange of NAND FLASH.Information bit and check bit is written in NAND FLASH controllers
The controller of FLASH, NAND FLASH read control section, write control section and erasing control section as shown in figure 4, being divided into.
The characteristic of NAND FLASH determines must carry out erasing operation before writing.It is exactly the hard FLASH to read control section
Information and soft information, which are read out, is sent into decoder into row decoding.Control section is wiped to realize to NAND
The block of FLASH is wiped.It is exactly the information bit that encoder is sent into and check bit write-in NAND FLASH to write control section.
Step 4, it decodes.Hard information and soft the information data read from FLASH are sent into
Decoder is into row decoding.Decoder uses the coding/decoding method of NMS.The structure chart of decoding is defeated as shown in figure 5, include input module
Go out module, storage unit, variable node computing unit and check node calculation unit.Variable node computing unit is responsible for variable section
The update of point, check node calculation unit are responsible for the update of check-node.The intermediate result of each iteration is stored in memory cell
In.Input is hard information and soft information, output the result is that hard information.
Step 5, mistake of statistics.Compare the data of the data and random generator after decoding, counts the bit error rate, can pass through
Data are sent to the ends PC by UART.Structure chart is as shown in fig. 6, include a comparator and a UART module.Comparator is responsible for ratio
The data of more random number generator and decoded data, and count number of errors.UART is responsible for the letter number of errors
Breath is sent to the ends PC.
Claims (7)
1. the test platform of LDPC for NAND FLASH a kind of, it is characterised in that：Including
Random-number-generating module, message length as needed generation random number,
Coding module, according to the message length of input and matrix generate check information,
NAND FLASH control modules, for carrying out data exchange with NAND FLASH, NAND FLASH controllers are information bit
With check bit write-in FLASH,
Hard information and soft the information data read from FLASH are sent into decoder by decoding module
Into row decoding, input is hard information and soft information, output the result is that hard
Information and
Error code detection module is used for mistake of statistics information, compares the data of the data and random generator after decoding, counts error code
Rate.
2. the test platform of LDPC for NAND FLASH according to claim 1 a kind of, it is characterised in that：It is described with
Machine number generation module uses LFSR structures, including several registers, and the initial value of the register is 0 or 1.
3. the test platform of LDPC for NAND FLASH according to claim 1 or 2 a kind of, it is characterised in that：Institute
It states random-number-generating module and obtains the random number that the period is 128.
4. the test platform of LDPC for NAND FLASH according to claim 1 a kind of, it is characterised in that：The volume
Code module includes shift register and summation circuit using SARR structures.
5. the test platform of LDPC for NAND FLASH according to claim 1 a kind of, it is characterised in that：It is described
NAND FLASH control modules include that hard information and the soft information of FLASH is read out feeding to translate
Code module writes control into the reading control section of row decoding, information bit and check bit write-in the NAND FLASH that coding module is sent into
System part and the erasing control section for realizing the block erasing to NAND FLASH.
6. the test platform of LDPC for NAND FLASH according to claim 1 a kind of, it is characterised in that：It is described to translate
Code module includes input module, output module, storage unit, variable node computing unit and check-node meter using NMS decodings
Unit is calculated, variable node computing unit is responsible for the update of variable node, and check node calculation unit is responsible for the update of check-node,
The intermediate result of each iteration is stored in memory cell.
7. the test platform of LDPC for NAND FLASH according to claim 1 a kind of, it is characterised in that：Error code is examined
It includes comparator and UART modules to survey module, which is responsible for comparing the data of randomizer and decoded data,
And number of errors is counted, UART is responsible for the information of number of errors to be sent to the ends PC.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810315076.1A CN108564983A (en) | 2018-04-10 | 2018-04-10 | A kind of LDPC test platforms for NAND FLASH |
| PCT/CN2018/103043 WO2019196316A1 (en) | 2018-04-10 | 2018-08-29 | Ldpc testing platform for nand flash |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810315076.1A CN108564983A (en) | 2018-04-10 | 2018-04-10 | A kind of LDPC test platforms for NAND FLASH |
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| CN108564983A true CN108564983A (en) | 2018-09-21 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201810315076.1A Pending CN108564983A (en) | 2018-04-10 | 2018-04-10 | A kind of LDPC test platforms for NAND FLASH |
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| CN (1) | CN108564983A (en) |
| WO (1) | WO2019196316A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111192624A (en) * | 2019-12-30 | 2020-05-22 | 深圳市芯天下技术有限公司 | System and method for testing performance of BCH (broadcast channel) error correcting code |
| CN112382335A (en) * | 2020-11-16 | 2021-02-19 | 武汉新芯集成电路制造有限公司 | Memory test system and method |
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| KR20160140514A (en) * | 2015-05-29 | 2016-12-07 | 주식회사 쏠리드 | Device for decoding low density parity check code |
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- 2018-08-29 WO PCT/CN2018/103043 patent/WO2019196316A1/en active Application Filing
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| CN101131710A (en) * | 2007-09-13 | 2008-02-27 | 南京大学 | Low-density odd-even checking codec hardware simulation system based on programmable gate array |
| CN101789794A (en) * | 2009-01-23 | 2010-07-28 | 雷凌科技股份有限公司 | Decoding method of low-density parity check code and circuit thereof |
| KR20160140514A (en) * | 2015-05-29 | 2016-12-07 | 주식회사 쏠리드 | Device for decoding low density parity check code |
| CN105185413A (en) * | 2015-09-24 | 2015-12-23 | 中国航天科技集团公司第九研究院第七七一研究所 | Automatic verification platform and method for on-chip memory management unit fault-tolerant structure |
| CN208298556U (en) * | 2018-04-10 | 2018-12-28 | 南京扬贺扬微电子科技有限公司 | A kind of LDPC test platform for NAND FLASH |
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| CN111192624A (en) * | 2019-12-30 | 2020-05-22 | 深圳市芯天下技术有限公司 | System and method for testing performance of BCH (broadcast channel) error correcting code |
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| WO2019196316A1 (en) | 2019-10-17 |
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Country or region after: China Address after: Building 63, Jinghui Science and Technology Innovation Park, 123 Jinghui West Road, Xinwu District, Wuxi City, Jiangsu Province, 214000 Applicant after: Jiangsu Yangheyang Microelectronics Technology Co.,Ltd. Address before: 211800, Building 12-80, No. 20 Buyue Road, Pukou District, Nanjing City, Jiangsu Province Applicant before: NANJING HEYANGTEK Co.,Ltd. Country or region before: China |