CN108564983A - A kind of LDPC test platforms for NAND FLASH - Google Patents

Abstract

The invention discloses an LDPC test platform for NAND FLASH. The test platform first generates a random number of a certain length, writes the random number and verification information into the FLASH, reads the FLASH and sends it to a decoder for decoding, and finally Statistics error message.

Description

A LDPC test platform for NAND FLASH

technical field

The invention belongs to the field of integrated circuit design, in particular to an LDPC test platform for NAND FLASH.

Background technique

With the advancement of NAND FLASH technology, more and more NAND FLASH needs LDPC for error correction. However, LDPC for NAND FLASH does not have a standard check matrix and its corresponding generation matrix, and there are many methods for constructing the check matrix. How to verify the performance of each matrix requires a test platform.

Contents of the invention

The purpose of the invention is to solve the test problem of LDPC used for NAND FLASH, and provide a kind of test platform for LDPC used for NAND FLASH.

In order to solve the problems of the technologies described above, the invention provides a test platform for LDPC of NAND FLASH, including

The random number generation module generates random numbers according to the required information length,

The encoding module generates verification information according to the input information length and matrix,

NAND FLASH control module, used for data exchange with NAND FLASH, NAND FLASH controller writes information bits and check bits into FLASH,

The decoding module sends the hard information and soft information data read from the FLASH into the decoder for decoding. The input is hard information and soft information, and the output results are hard information, and

The bit error detection module is used for counting error information, comparing the decoded data with the data of the random generator, and counting the bit error rate.

The random number generation module adopts LFSR structure and includes several registers, and the initial value of the registers is 0 or 1.

The random number generating module obtains a random number with a period of 128.

The encoding module adopts a SARR structure and includes a shift register and an accumulation circuit.

The NAND FLASH control module includes the read control part that reads the hard information and soft information of the FLASH and sends them to the decoding module for decoding, and writes the information bits and check digits sent by the coding module into the NAND FLASH write control part And realize the erase control part of block erase to NAND FLASH.

The decoding module adopts NMS decoding and includes an input module, an output module, a storage unit, a variable node calculation unit and a check node calculation unit, the variable node calculation unit is responsible for the update of the variable node, and the check node calculation unit is responsible for the update of the check node , the intermediate results of each iteration are stored in the storage unit.

The error detection module includes a comparator and a UART module. The comparator is responsible for comparing the data of the random number generator and the decoded data, and counts the number of errors. The UART is responsible for sending the information of the number of errors to the PC.

Description of drawings

Fig. 1 is a block diagram of the present invention;

Figure 2 is a structural diagram of the LFSR;

Figure 3 is a SARR structure diagram;

Fig. 4 is a schematic diagram of a NAND FLASH controller;

Fig. 5 is a structural diagram of a decoder;

Fig. 6 is a schematic diagram of the structure of bit error detection.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings.

The invention provides an LDPC test platform for NAND FLASH. The test platform first generates a random number of a certain length, writes the random number and verification information into the FLASH, reads the FLASH and sends it to a decoder for decoding, and finally Statistics error message.

The implementation of this invention specifically comprises the following steps:

Step 1, random number generation. Random number generation adopts the LFSR structure shown in Figure 2, and generates random numbers according to the required information length. The initial value of each register can be 0 or 1, and a random number with a period of 128 is obtained.

Step 2, encoding. The encoder adopts the SARR (shift-register-adder-accumulator) structure shown in Figure 3. The SARR circuit uses the shift register and the accumulation circuit as the core to realize the multiplication of vectors and matrices, which greatly reduces the amount of calculation and resource consumption, which is beneficial to The hardware implementation of the encoder. Generate verification information according to the input information length and matrix.

Step 3, data exchange with NAND FLASH. The NAND FLASH controller writes information bits and parity bits into the FLASH, and the NAND FLASH controller is shown in Figure 4, which is divided into a read control part, a write control part and an erase control part. The characteristics of NAND FLASH determine that an erase operation must be performed before writing. The read control part is to read out the hard information and soft information of FLASH and send them to the decoder for decoding. The erasure control part realizes the block erasure of NANDFLASH. The write control part is to write the information bit and check bit sent by the encoder into NAND FLASH.

Step 4, decoding. Send the hard information and soft information data read from FLASH to the decoder for decoding. The decoder adopts the decoding method of NMS. The decoding structure diagram is shown in Figure 5, including an input module, an output module, a storage unit, a variable node calculation unit and a check node calculation unit. The variable node calculation unit is responsible for updating the variable nodes, and the check node calculation unit is responsible for updating the check nodes. The intermediate results of each iteration are stored in the storage unit. The input is hard information and soft information, and the output result is hard information.

Step 5, statistics errors. Compare the decoded data with the data of the random generator, count the bit error rate, and send the data to the PC through UART. The block diagram is shown in Figure 6, including a comparator and a UART module. The comparator is responsible for comparing the data of the random number generator and the decoded data, and counting the number of errors. UART is responsible for sending the wrong number of information to the PC.

Claims (7)

1. a test platform for LDPC of NAND FLASH, is characterized in that: comprise The random number generation module generates random numbers according to the required information length, The encoding module generates verification information according to the input information length and matrix, NAND FLASH control module, used for data exchange with NAND FLASH, NAND FLASH controller writes information bits and check bits into FLASH, The decoding module sends the hard information and soft information data read from the FLASH into the decoder for decoding. The input is hard information and soft information, and the output results are hard information, and The bit error detection module is used for counting error information, comparing the decoded data with the data of the random generator, and counting the bit error rate. 2. a kind of test platform for the LDPC of NAND FLASH according to claim 1, is characterized in that: described random number generation module adopts LFSR structure, comprises some registers, and the initial value of described registers is 0 or 1. 3. a kind of test platform for the LDPC of NAND FLASH according to claim 1 and 2, is characterized in that: described random number generating module obtains the random number that period is 128. 4. a kind of test platform for the LDPC of NAND FLASH according to claim 1 is characterized in that: described encoding module adopts SARR structure to comprise shift register and accumulation circuit. 5. A kind of test platform for the LDPC of NAND FLASH according to claim 1, it is characterized in that: described NAND FLASH control module comprises that the hard information and soft information of FLASH are read out and sent into decoding module and decode The read control part, the write control part that writes the information bits and check bits sent by the encoding module into NAND FLASH, and the erase control part that realizes block erasure of NAND FLASH. 6. A kind of test platform for the LDPC of NAND FLASH according to claim 1, it is characterized in that: described decoding module adopts NMS decoding to comprise input module, output module, storage unit, variable node computing unit and checking The node calculation unit, the variable node calculation unit is responsible for the update of variable nodes, the check node calculation unit is responsible for the update of check nodes, and the intermediate results of each iteration are stored in the storage unit. 7. the test platform of a kind of LDPC that is used for NAND FLASH according to claim 1 is characterized in that: the bit error detection module comprises comparator and UART module, and this comparator is responsible for comparing the data of random number generator and after decoding The data, and count the number of errors, UART is responsible for sending the information of the number of errors to the PC.