CN103295634A - Method, memory controller and system for reading data stored in flash memory - Google Patents

Abstract

According to an embodiment of the present invention, a method for reading data stored in a flash memory is disclosed, the method comprising: controlling the flash memory to execute a read operation on a first memory page of the flash memory; obtaining a first codeword of the first memory page; obtaining a first set of likelihood ratio corresponding values of the first codeword according to a first likelihood ratio corresponding rule; performing an error correction operation according to the first set of corresponding values of the approximate ratio; if the error correction operation indicates an uncorrectable result according to the first set of likelihood ratio corresponding values, obtaining a second set of likelihood ratio corresponding values of the first codeword according to a second likelihood ratio corresponding rule; and performing the error correction operation according to the second set of corresponding values of the approximate ratio.

Description

Read method, Memory Controller and the system of data stored in the flash memory

[technical field]

The present invention is relevant for reading stored data in the flash memory (flash memory), refers to that especially a kind of binary digit distribution character (binary digit distribution characteristic) by the bit sequence (bit sequence) of reading with reference to the storage unit (memory cell) of flash memory reads method and the Memory Controller of data stored in the flash memory.

[background technology]

Flash memory can store to carry out data with writing/stylize (program) by erase (erase) of electronic type, and is widely used in storage card (memory card), solid state hard disc (solid-state drive) and portable multimedia player etc.Because flash memory is non-volatile (non-volatile) storer, therefore, do not need additional power to keep the stored information of flash memory, in addition, the fast data that can provide flash memory reads and preferable shock resistance, and these characteristics have also illustrated the reason why flash memory can so be popularized.

Flash memory can be divided into NOR type flash memory and NAND type flash memory.For NAND type flash memory, it has erasing and write time and the less chip area of each memory cell needs of lacking, thereby compared to NOR type flash memory, NAND type flash memory can allow higher storage density and lower each to store the cost of bit.In general, flash memory comes storage data in the mode of memory cell array, and memory cell is to do in fact by a floating grid transistor (floating-gate transistor), and each memory cell can by the electric charge number on the floating grid of suitably controlling floating grid transistor set this floating grid transistor of conducting the required critical voltage of real this memory cell of doing, and then store information or the above information of bit of single bit, thus, put on when one or more predetermined control grid voltage floating grid transistor the control grid on, then the conducting state of floating grid transistor just can indicate one or more stored in floating grid transistor binary digit (binary digit).

Yet, because some factor, the number of the electric charge that stores originally in the flash memory cells may be affected/upset, for instance, existing interference may come from and writes interference (write/program disturbance), reads interference (read disturbance) and/or keep to disturb (retention disturbance) in the flash memory.Be example with NAND type flash memory with the memory cell that stores an information more than the bit separately, entity stores device paging (physical page) can comprise a plurality of logical storage pagings (logical page), and each logical storage paging adopts one or more control gate pole tension to read.For instance, for a flash memory cells in order to the information that stores 3 bits, this flash memory cells can have one of them of 8 kinds of states (that is electric charge position standard) of corresponding different electric charge numbers (that is different critical voltage) respectively, yet, owing to write/erase number of times (program/erase count, P/E count) and/or the cause of data retention time (retention time), the critical voltage distribution (threshold voltage distribution) of the memory cell in the flash memory cells just can change to some extent, therefore, use control gate pole tension setting (that is critical voltage setting) is originally read information stored in the memory cell and may and can't correctly be obtained stored information because of the critical transformation distribution after changing.

Utilizing different control gate pole tensions to set to read flash memory may have higher chance to obtain correct storage information.Yet, store all and utilize the obtained information of different control gate pole tensions settings may need more storage space.In addition, utilize different control gate pole tensions to set to read flash memory and may cause long reading the time, therefore, need more efficient reading or decoding program.

[summary of the invention]

Therefore, one of purpose of the present invention is to provide a kind of method, Memory Controller and device that reads data stored in the flash memory, to address the above problem.Read method, Memory Controller and the device of data stored in the flash memory.

According to one embodiment of the invention, a kind ofly disclosed in order to the method that reads the data that are stored in a flash memory, this method comprises: control this flash memory and one first memory paging of this flash memory is carried out one read running; Obtain one first code word of this first memory paging; General general seemingly than respective value like obtain this first code word than corresponding rule one first group according to one first; General like carry out error correction running than respective value according to this first group; If it is generally indicate a result that can not correct like carry out this error correction running than respective value according to this first group, then generally general seemingly than respective value like obtain this first code word than corresponding rule one second group according to one second; And it is general like carry out this error correction running than respective value according to this second group.

According to another embodiment of the present invention, disclosed a kind of in order to read the Memory Controller of the data that are stored in a flash memory, this Memory Controller comprises: a control logic circuit, read running to obtain one first code word of this first memory paging in order to control this flash memory to the first memory paging execution one of this flash memory; Without exception seemingly than corresponding unit, in order to general general seemingly than respective value like obtain this first code word than corresponding rule one first group according to one first; An and decoding circuit, in order to general like carry out error correction running than respective value according to this first group, wherein if according to this first group general like carry out than respective value that this error correction running indication one can not correct as a result the time, then should be general like more be used for than corresponding unit according to one second general like obtain this first code word than corresponding rule one second group general like than respective value, and that this decoding circuit more is used for according to this second group is general like carry out this error correction running than respective value.

According to another embodiment of the present invention, disclosed a kind of in order to read the accumulator system of the data that are stored in a flash memory, this accumulator system comprises: a control logic circuit, read running to obtain one first code word of this first memory paging in order to control this flash memory to the first memory paging execution one of this flash memory; Without exception seemingly than corresponding unit, in order to general general seemingly than respective value like obtain this first code word than corresponding rule one first group according to one first; An and decoding circuit, in order to general like carry out error correction running than respective value according to this first group, wherein if according to this first group general like carry out than respective value that this error correction running indication one can not correct as a result the time, then should be general like more be used for than corresponding unit according to one second general like obtain this first code word than corresponding rule one second group general like than respective value, and that this decoding circuit more is used for according to this second group is general like carry out this error correction running than respective value.

[description of drawings]

Fig. 1 is the synoptic diagram of first embodiment of accumulator system of the present invention.

The synoptic diagram that Fig. 2 distributes for first kind of critical voltage of the entity stores device paging P_0 that will be read.

The synoptic diagram that Fig. 3 distributes for second kind of critical voltage of the entity stores device paging P_0 that will be read.

Fig. 4 is the synoptic diagram that reads the least significant bit (LSB) unit read operation of a soft bit from one of flash memory 1100 memory cell.

Fig. 5 is shown in the calcspar of the scrambler 1223 of Fig. 1.

The synoptic diagram of Fig. 6 explanation to reading to encode from the binary digit of flash memory cells.

Fig. 7 explanation is to reading to encode to obtain from the binary digit of flash memory cells the synoptic diagram of correct data.

Fig. 8 explanation is to reading to encode to obtain from the binary digit of flash memory cells the synoptic diagram of correct data.

Fig. 9 explanation is to reading to encode to obtain from the binary digit of flash memory cells the synoptic diagram of correct data.

Figure 10 illustrates the synoptic diagram of the corresponding relation of code word and memory cell.

Figure 11 is in order to illustrate the calcspar of decoding unit 1228.

The process flow diagram of the program of the data that are stored in flash memory is read in Figure 12 explanation.

Figure 13 illustrates the synoptic diagram that the critical voltage of target entity memory paging distributes.

[main element symbol description]

1000～accumulator system;

1100～flash memory;

1110～memory cell;

1200～Memory Controller;

1210～control logic circuit;

1220～error correction circuit;

1222～error correction decoding device;

1223～scrambler;

1224～comparing unit;

1225～judging unit;

1227～storage device;

1228～decoding unit;

1229～error correction scrambler;

12280～general seemingly than training unit;

12282～general seemingly than corresponding unit;

12284～decoding circuit;

200～214～step.

[embodiment]

In the middle of instructions and follow-up claim, used some vocabulary to censure specific element.The person with usual knowledge in their respective areas should understand, and same element may be called with different nouns by manufacturer.This instructions and follow-up claim are not used as the mode of distinct elements with the difference of title, but the benchmark that is used as distinguishing with the difference of element on function.Be an open term mentioned " comprising " in the middle of instructions and the follow-up request item in the whole text, so should be construed to " comprise but be not limited to ".In addition, " couple " word and comprise any indirect means that are electrically connected that directly reach at this.Therefore, be electrically connected at one second device if describe one first device in the literary composition, then represent this first device and can be directly connected in this second device, or be connected to this second device indirectly by other devices or connection means.

Note that, the stored a plurality of bits of memory cell that read in the entity stores device paging of NAND type flash memory only are as an embodiment, so that technical characterictic of the present invention to be described, yet, no matter flash memory is NAND type flash memory or the flash memory with other type (for example NOR type flash memory), be encoded into code word to carry out error correction running, all spirit according to the invention so long as will read binary digit obtained the running from difference.

See also Fig. 1, it is the synoptic diagram of first embodiment of accumulator system of the present invention.Accumulator system 1000 includes a flash memory 1100 and a Memory Controller (memory controller) 1200, in present embodiment, flash memory 1100 can be to comprise a plurality of entity stores device paging P_0, P_1, P_2, the NAND type flash memory of P_N, wherein each the entity stores device paging among entity stores device paging P_0～P_N includes a plurality of memory cells (for example floating grid transistor) 1110, for instance, for one of being read target entity memory paging P_0, it includes memory cell M_0～M_K.For stored data among the memory cell M_0～M_K that reads target entity memory paging P_0, control gate pole tension VG_0～VG_N just should suitably set, for example, control gate pole tension VG_0～VG_N should set suitably to guarantee that memory cells (floating gate memory) 103 all among entity stores device paging P_1～P_N all is in conducting state.If each memory cell 103 is in order to (for example to store N bit, comprise (the least significant bit of least significant bit (LSB) unit, LSB), middle effectively bit (central significant bit, CSB) with (the most signifi cant bit of highest significant position unit, MSB) 3 bits), then flash memory 102 can be set at (2 with control gate pole tension VG_0 ^N-1) individual voltage quasi position is in order to pick out N bit of each memory cell 103 among the target entity memory paging P_0.

See also Fig. 2, the synoptic diagram that it distributes for first kind of critical voltage of the entity stores device paging P_0 that will be read.Memory cell M_0～M_K of entity stores device paging P_0 can include and has floating grid and stylized (programmed) for having electric charge position accurate L0 (that is (MSB, CSB, LSB)=(1,1,1) memory cell), having floating grid is turned to by formula and has electric charge position accurate L1 (that is (MSB, CSB, LSB)=(0,1,1) memory cell), having floating grid is turned to by formula and has electric charge position accurate L2 (that is (MSB, CSB, LSB)=(0,0,1) memory cell), having floating grid is turned to by formula and has electric charge position accurate L3 (that is (MSB, CSB, LSB)=(1,0,1) memory cell), have floating grid turned to and have the accurate L4 in electric charge position by formula (that is (MSB, CSB, LSB)=(1,0,0) memory cell), have floating grid turned to and have the accurate L5 in electric charge position by formula (that is (MSB, CSB, LSB)=(0,0,0) memory cell), have floating grid turned to and have the accurate L6 in electric charge position by formula (that is (MSB, CSB, LSB)=(0,1,0) memory cell) and have floating grid turned to and have the accurate L7 in electric charge position by formula (that is (MSB, CSB, LSB)=(1,1,0) memory cell).

In order to pick out the least significant bit (LSB) unit of memory cell M_0～M_K, flash memory 102 just is set at critical voltage VT_4 shown in Figure 2 with control gate pole tension VG_0, then, the conducting state of each memory cell just can indicate the least significant bit (LSB) unit that this memory cell has and is among the entity stores device paging P_0 " 0 " or " 1 ".In present embodiment, when memory cell one of among the entity stores device paging P_0 was applied in the critical voltage VT_4 institute conducting of its control grid, flash memory 1100 will be exported and represent the individual binary digit of one of its least significant bit (LSB) unit " 1 "; Otherwise flash memory 1100 will be exported another binary digit that represents its least significant bit (LSB) unit " 0 ".

For the effective bit in the centre that picks out memory cell M_0～M_K, flash memory 1100 just is set at critical voltage VT_2 and VT_6 shown in Figure 2 respectively with control gate pole tension VG_0, similarly, the conducting state of each memory cell just can indicate the effective bit in centre that this memory cell has and is among the entity stores device paging P_0 " 0 " or " 1 ".In present embodiment, when a memory cell can be applied in the critical voltage VT_2 of its control grid with any institute conducting among the VT_6, flash memory 1100 will be exported and represent the individual binary digit of one of its centre significance bit unit " 1 "; Can not be applied in the critical voltage VT_2 institute conducting of its control grid when this memory cell, but in the time of but can being applied in the critical voltage VT_6 institute conducting of its control grid, flash memory 102 will be exported and represent the individual binary digit of one of significance bit unit in the middle of it " 0 "; And work as this memory cell except not being applied in the critical voltage VT_2 institute conducting of its control grid, in the time of also can not being applied in the critical voltage VT_6 institute conducting of its control grid, flash memory 1100 will be exported and represent the individual binary digit of one of significance bit unit in the middle of it " 1 ".

In order to pick out the highest significant position unit of memory cell M_0～M_K, flash memory 1100 just is set at critical voltage VT_1, VT_3, VT_5 and VT_7 shown in Figure 2 respectively with control gate pole tension VG_0, similarly, the conducting state of each memory cell just can indicate the highest significant position unit that this memory cell has and is among the entity stores device paging P_0 " 0 " or " 1 ".In present embodiment, when a memory cell can be applied in any institute conducting among critical voltage VT_1, VT_3, VT_5 and VT_7 of its control grid, flash memory 1100 will be exported and represent the individual binary digit of one of its highest significant position unit " 1 "; Can not be applied in the critical voltage VT_1 institute conducting of its control grid when this memory cell, but in the time of but can being applied in critical voltage VT_3, the VT_5 of its control grid with any institute conducting among the VT_7, flash memory 1100 will be exported and represent the individual binary digit of one of its highest significant position unit " 0 "; When this memory cell can not be applied in the critical voltage VT_1 of its control grid and any the institute's conducting among the VT_3, but in the time of but can being applied in the critical voltage VT_5 of its control grid with any institute conducting among the VT_7, flash memory 1100 will be exported and represent the individual binary digit of one of its highest significant position unit " 1 "; When this memory cell can not be applied in critical voltage VT_1, the VT_3 of its control grid and any the institute's conducting among the VT_5, but in the time of but can being applied in the critical voltage VT_7 institute conducting of its control grid, flash memory 1100 will be exported and represent the individual binary digit of one of its highest significant position unit " 0 "; And when this memory cell can not be applied in any institute conducting among critical voltage VT_1, VT_3, VT_5 and VT_7 of its control grid, flash memory 1100 will be exported and represent the individual binary digit of one of its highest significant position unit " 1 ".

Yet, critical voltage shown in Figure 2 distributes and may change into another critical voltage because of the influence of some factor increase of reading times and/or data retention time (for example write /) and distribute, for instance, the distribution that corresponds to the circular standing shape of each electric charge position standard may broaden and/or produce skew.See also Fig. 3, the synoptic diagram that it distributes for second kind of critical voltage of the entity stores device paging P_0 that will be read.Can be learnt that by Fig. 3 critical voltage distributes and is different from critical voltage distribution shown in Figure 2.Control gate pole tension VG_0 is set at the least significant bit (LSB) unit that above-mentioned critical voltage VT_1～VT_7 can't correctly obtain memory cell M_0～M_K of target entity memory paging P_0, middle effectively bit and highest significant position unit are furthermore, when memory cell M_0～M_K has critical voltage distribution shown in Figure 3, should adopt new critical voltage VT_1 '～VT_7 ' in order to correctly obtain stored information, otherwise, (error correction code, ECC) operation just can can't successful operation because of correcting (uncorrectable) mistake in the code word to put on the error correction of the code word (codeword) that memory cell M_0～M_K reads.In present embodiment, Memory Controller 1200 is that the code word that design is read memory cell M_0～M_K is adaptively carried out soft decoding to strengthen decoding capability.Details describes in detail in the back.

Please consult Fig. 1 again.Memory Controller 104 is in order to the access of controlling flash memory 102 (read/write), and include (but being not limited to) control logic circuit 1210 and an error correction circuit (ECC circuit, it has an error correction decoding device 1222, an error correction scrambler 1229 and a critical voltage tracing unit 1230).Note that Fig. 1 only shows the element relevant with technical characterictic of the present invention, that is Memory Controller 104 also can comprise extra element and support other function.In general, in receiving at target entity memory paging P_0 during the request of reading (read request) of one of stored data of memory cell M_0～M_K, control logic circuit 1210 can control flash memory 1100 reads desired data (requested data) in response to this request of reading, then, when flash memory 102 successfully picks out stored all bits of each memory cell among memory cell M_0～M_K, include the reading information and just can be received circuit 1210 and receive of the bit that has picked out of memory cell M_0～M_K.Known to skilled persons will, the a part of memory cell that is arranged in an entity stores device paging is to store error correction information (a for example error correcting code (ECC code)), therefore, error correction circuit 1220 is to carry out error correction operation at the information (a for example code word) of reading that is read out by flash memory 1100.In present embodiment, error correction circuit 1220 includes an error correction decoding device (ECC decoder) 1222 and one error correction scrambler (ECCcorrector) 1229.Error correction decoding device 1222 is to check the correctness of reading information, to detect existing of any wrong bit by this.Yet error correction decoding device 1222 also is used for the wrong bit that information is found to of reading that checked is corrected, when the quantity of in esse wrong bit had surpassed error correction decoding device 1222 way is arranged according to the maximum quantity of the wrong bit of hard decoder (for example BCH (mode of Bose-Chaudhuri-Hocquenghem)) corrigendum in reading information, error correction decoding device 1222 just can indicate control logic circuit 1210 to read to include the mistake that can't correct in the information.Thus, control logic circuit 1210 will start soft reading (soft read) mechanism to obtain soft information, and those soft information can be used for carrying out soft decoding mechanism by ECC demoder 1222.This critical voltage tracing unit 1230 is used for by relatively reading information to judge the critical voltage moving direction and to judge a best critical voltage.Details describes in detail in the back.

In present embodiment, error correction decoding device 1222 can be by low density parity check (low density parity-check, LDPC) demoder does in fact, control logic circuit 1210 control flash memories 1100 provide the soft information (soft information) that will be decoded by the LDPC demoder, so, following in the control of control logic circuit 1210, flash memory 1100 is just exported a plurality of binary digits and is used as the soft bit (soft bit) that each memory cell M_0～M_K reads out.Furthermore, when carry out the reading of least significant bit (LSB) metadata, middle significance bit metadata read or during the reading of highest significant position metadata, control logic circuit 1210 is to carry out repeatedly read operation (for example 7 read operations) in order to control flash memory 1100 at each memory cell among the memory cell M_0～M_K of target entity memory paging.

See also Fig. 4, it is the synoptic diagram that reads the least significant bit (LSB) unit read operation of a soft bit (that is soft information numerical value) from one of flash memory 1100 memory cell.The example that distributes according to Fig. 2 and critical voltage shown in Figure 3, memory cell with any electric charge position standard among the accurate L0～L3 in electric charge position will store LSB=1, and the memory cell with any electric charge position standard among the accurate L4～L7 in electric charge position then can store LSB=0.In present embodiment, control module 1210 determines an initial control gate pole tension V _LSBAnd voltage spacing (voltage spacing) D, then control flash memory 1100 and carry out 7 read operations at each memory cell among memory cell M_0～M_K, and adjust order (voltage adjusting order) OD1 based on voltage, flash memory 1100 can be in regular turn with V _LSB, V _LSB+ D, V _LSB-D, V _LSB+ 2D, V _LSB-2D, V _LSB+ 3D, V _LSB-3D sets control gate pole tension VG_0, therefore, because the grid-control voltage V that applies _LSB, V _LSB+ D, V _LSB-D, V _LSB+ 2D, V _LSB-2D, V _LSB+ 3D, V _LSBThe cause of-3D, each metasequence among bit sequence BS_0～BS_M all can obtain 7 bits in regular turn.Note that each metasequence among bit sequence BS_0～BS_M as a soft bit, the soft information that its representative is read out by a memory cell, and by initial control gate pole tension V _LSBThe binary digit that obtains can be used as a sign bit (sign bit) (that is hard bit (hard bit) numerical value).Utilize initial control gate pole tension V _LSBThe running of carrying out of reading can be considered and generally reads running.And utilize control gate pole tension V _LSB+ D, V _LSB-D, V _LSB+ 2D, V _LSB-2D, V _LSB+ 3D, V _LSB-3D carries out reads running and can be considered as reading again running 1～6 respectively.

In present embodiment, each metasequence has one of them of eight kinds of possible binary digit combination BS1～BS8.When the electric charge that is stored in the floating grid of memory cell at present makes the critical voltage of memory cell be higher than V _LSB+ 3D, then the bit sequence that reads out from memory cell will have binary digit combination BS8=" 0000000 "; When the electric charge that is stored in the floating grid of memory cell at present makes the critical voltage of memory cell between V _LSB+ 2D and V _LSBBetween+the 3D, then the bit sequence that reads out from memory cell will have binary digit combination BS7=" 0000010 "; When the electric charge that is stored in the floating grid of memory cell at present makes the critical voltage of memory cell between V _LSB+ D and V _LSBBetween+the 2D, then the bit sequence that reads out from memory cell will have binary digit combination BS6=" 0001010 "; When the electric charge that is stored in the floating grid of memory cell at present makes the critical voltage of memory cell between V _LSBWith V _LSBBetween+the D, then the bit sequence that reads out from memory cell will have binary digit combination BS5=" 0101010 "; When the electric charge that is stored in the floating grid of memory cell at present makes the critical voltage of memory cell be lower than V _LSB-3D, then the bit sequence that reads out from memory cell will have binary digit combination BS1=" 1111111 "; When the electric charge that is stored in the floating grid of memory cell at present makes the critical voltage of memory cell between V _LSB-2D and V _LSBBetween-the 3D, then the bit sequence that reads out from memory cell will have binary digit combination BS2=" 1111110 "; When the electric charge that is stored in the floating grid of memory cell at present makes the critical voltage of memory cell between V _LSB-D and V _LSBBetween-the 2D, then the bit sequence that reads out from memory cell will have binary digit combination BS3=" 1111010 "; And the electric charge that ought be stored in the floating grid of memory cell at present makes the critical voltage of memory cell between V _LSBWith V _LSBBetween-the D, then the bit sequence that reads out from memory cell will have binary digit combination BS4=" 1101010 ".

When all binary digits in the bit sequence are " 1 " time, the corresponding memory cell of this representative has the accurate L0 in electric charge position, L1, L2 or L3, and the fiduciary level of LSB=1 (reliabil ity) is very high.On the other hand, when all binary digits in the bit sequence are " 0 " time, the corresponding memory cell of this representative has the accurate L5 in electric charge position, L6, L7 or L8, and the fiduciary level of LSB=0 is very high.Yet, when a bit sequence has different binary digits " and 0 " with " 1 " when mixing wherein, the corresponding memory cell of this representative has the accurate L3 in electric charge position or L4, because the critical voltage of corresponding memory cell is between V _LSB-3D and V _LSBBetween+the 3D, the fiduciary level of LSB=1/LSB=0 just can be owing to error rate be higher and lower, for instance, the memory cell that stores LSB=0 originally can have correspond to the accurate L4 in electric charge position the electric charge stored number so that critical voltage is higher than V _LSB+ 3D, however when writing/erasing the increase of number of times or data retention time, the quantity of stored electric charge just can change to some extent, thereby may make that critical voltage is lower than V _LSBSimilarly, the memory cell that originally stores LSB=1 can have correspond to the accurate L3 in electric charge position the electric charge stored number so that critical voltage is lower than V _LSB-3D, compared to hard decoder, the fiduciary level that is present in soft information numerical value can be increased in the correct probability of decoding when carrying out soft the decoding.Yet soft information numerical value is contained in and generally reads the obtained a plurality of binary digits of running and follow-up stressed running 1～6, seven binary digits as previously mentioned.In order to carry out soft decoding, complete soft information numerical value must be obtained and store to error correction decoding device 1222, and therefore, error correction decoding device 1222 needs a large amount of storage areas to store complete soft information numerical value.This will increase chip area and cost.

For reducing the storage area, the binary digit of obtaining from read running can just be encoded to short code word earlier before storing or decoding.Please at reference Fig. 1, as previously mentioned, error correction circuit 1220 is used for the information that reads that obtains from flash memory 1100 is carried out the error correction running.And error correction decoding device 1222 is used for checking the correctness that reads information.In addition, error correction decoding device 1222 more comprises a scrambler 1223, a storage device 1227 and a decoding unit 1228.Scrambler 1223 represents this binary digit in order to produce short code word according to the binary digit that reads from flash memory 1100.Storage device 1227 is in order to store the code word that is produced by scrambler and to provide stored code word to decoding unit 1228.Decoding unit 1228 is in order to operate this code word execution error corrigendum.Details describes in detail in the back.

In one embodiment, control logic circuit 1210 control flash memories 1100 are according to initial control gate pole tension V _LSBTo memory cell, for example storer cell unit M_0～M-K of entity stores device paging P_0 carries out reading running with the least significant bit (LSB) unit of identification storer cell unit M_0～M-K.According to initial control gate pole tension V _LSBThe running of carrying out of reading can be considered and generally reads running.Flash memory 1100 provides the binary digit (a page of binary digits) that has comprised the storage paging of one of data division, reserve piece and at least one check code (parity) part to control logic circuit 1210.Control logic circuit 1210 transmits its binary digit that receives to error correction circuit 1220.In one embodiment, error correction circuit 1220 is divided into two parts with the binary digit that receives.First comprises the data division check code part corresponding with it.Second portion comprise reserve piece with and corresponding check code part.1220 pairs of firsts of error correction circuit carry out soft decoding running (soft decode operation), and second portion is carried out rigid decoding running (hard decode operation).This is illustrative, but not restriction of the present invention.Arbitrary part of the binary digit of this paging is carried out soft decoding or rigid decoding running is category of the present invention.In this embodiment, scrambler 1223 produces a code word according to the binary digit of first.Details describes in detail in the back.

Please refer to Fig. 5 and Fig. 6, Fig. 5 is shown in the calcspar of the scrambler 1223 of Fig. 1.The synoptic diagram of Fig. 6 explanation to reading to encode from the binary digit of flash memory cells.Scrambler 1223 comprises a comparing unit 1224 and a judging unit 1225.Fig. 5 only shows the element relevant with technical characterictic of the present invention, that is scrambler 1223 also can comprise extra element and support other function.Comparing unit 1223 is used for relatively from the binary digit of the first that control logic circuit is sent here and the positive and negative bit that is stored in storage device 1227.When reading a target entity memory paging (for example entity stores device paging P_0), control logic circuit 1210 control flash memories 1210 are according to an initial control gate pole tension V _LSBTo storer cell unit (the storer cell M_0 of entity stores device paging P_0～M_K) carry out reading running with the least significant bit (LSB) unit of recognition memory cell M_0～M_K for example.As shown in Figure 6, the binary digit of the first of this entity stores device paging is sent to scrambler 1223.Note that each bit of those binary digits represents the hard bit (hard bit also can be described as hard information (hard information)) of least significant bit (LSB) unit of the storer cell unit of this entity stores device paging P_0.For example, the leftmost binary digit of those binary digits is " 1 ", its hard bit of least significant bit (LSB) unit that represents the storer cell M_0 of entity stores device paging P_0 is " and 1 ".The binary digit on the leftmost binary digit of those binary digits next door is " 1 ", its hard bit of least significant bit (LSB) unit that represent the storer cell M_1 of entity stores device paging P_0 is " and 1 ", by that analogy.Because the binary digit of first derives from reading running according to initial control gate pole tension in those storer cell unit, those binary digits can be considered the sign bit of those memory cells.Accordingly, scrambler 1223 produces (and setting) high strength bit and be " 1 " a low-intensity bit be " 1 ", to represent positive and negative bit " 1 " have a highest fiduciary level.In other words, memory cell M_0 is assumed to be " 1 ", and have the highest fiduciary level.In addition, comprise hard bit " 1 " and soft bit (soft bit also can be described as soft information (soft information)) " 11 " code word " 111 " be used for representing the stored information of memory cell M_0.The code word that is used for representing other memory cells is also carried out according to similar mode.Then, the code word of the binary digit of first is sent to storage device 1227.Then, storage device 1227 offers decoding unit 1228 with execution error corrigendum running with this code word.In one embodiment, this decoding unit 1228 is carried out an error correction hard decoder (error correction hard decode) in another embodiment according to this code word, this decoding unit 1228 is carried out an error correction hard decoder according to this sign bit and correctly maybe can be corrected (in other words error correction hard decoder indication one result that can correct) if this code word is pointed out in the error correction running, then error correction circuit 1220 is this result notification control logic circuit 1210, and correct data are offered control logic circuit 1210.If the error correction running is pointed out this code word (or this sign bit) and can not be corrected (in other words error correction hard decoder indication one result that can not correct), error correction circuit 1220 is with this result notification control logic circuit 1210, and control logic circuit 1210 control flash memories 1100 are according to control gate pole tension V _LSBThe storer cell of+D unit carries out one and reads running (D is a predetermined voltage spaces) again.Details describes in detail in the back.

Please refer to Fig. 7, Fig. 7 explanation is to reading to encode to obtain from the binary digit of flash memory cells the synoptic diagram of correct data.When reading a target entity memory paging (for example, entity stores device paging P_0), control logic circuit 1210 control flash memories 1100 are according to the second control gate pole tension V _LSB(for example, the memory cell M_0 of entity stores device paging P_0～M_K) execution one is read running with the least significant bit (LSB) unit of interpretation memory cell M_0～M_K to the memory cell of+D.This stressed running can be regarded as reading again for the first time running.As shown in Figure 7, the binary digit of the first of this entity stores device paging is delivered to coding unit 1223.Note that each bit of those binary digits represents the soft bit of the least significant bit (LSB) unit of one of entity stores device paging P_0 storer cell unit.For example, the leftmost binary digit of those binary digits is " 1 ", its represent entity stores device paging P_0 storer cell M_0 least significant bit (LSB) unit soft bit for " 1 ".The binary digit on the leftmost binary digit of those binary digits next door is " 0 ", its soft bit of least significant bit (LSB) unit that represent the storer cell M_1 of entity stores device paging P_0 is " and 0 ", by that analogy.Note that binary digit shown in Figure 7 (reading data again) may be not exclusively identical with the sign bit.The stressed control gate pole tension that operates is V because in order to carry out for the first time _LSB+ D is so utilizing grid-control voltage V _LSBWith V _LSB+ D reads critical voltage and drops on V _LSBWith V _LSBCan obtain different results during the memory cell of+D.For example, according to control gate pole tension V _LSBThe sign bit of the least significant bit (LSB) unit of obtained memory cell M_1 is " 0 ", and according to control gate pole tension V _LSBThe soft bit of the least significant bit (LSB) unit of the memory cell M_1 that+D is obtained is " 1 ".Therefore, scrambler 1223 need updated stored device unit M_1 least significant bit (LSB) unit the fiduciary level of code word.Details describes in detail in the back.

According to control gate pole tension V _LSBThe obtained stressed data of+D (binary digit) are delivered to comparing unit 1224.Comparing unit 1224 accesses are stored in the sign bit of storage device 1227, and relatively sign bit and stressed data with the renewal code word.If the sign bit is identical with its corresponding stressed data (binary digit), comparing unit 1224 is indicated judging unit 1225 with this result.And judging unit 1225 is judged the fiduciary level that will keep this sign bit.In other words, the code word that is used for expressing corresponding memory cell is not changed.Inequality as if the stressed data (binary digit) that the sign bit is corresponding with it, comparing unit 1224 is indicated judging unit 1225 with this result.And judging unit 1225 is judged fiduciary level to the lowest reliable degree that will upgrade this sign bit.In other words, the code word that is used for expressing corresponding memory cell is changed.For example, according to control gate pole tension V _LSBThe sign bit of the least significant bit (LSB) unit of obtained memory cell M_1 is " 0 ", and according to control gate pole tension V _LSBThe soft bit of the least significant bit (LSB) unit of the memory cell M_1 that+D is obtained is " 1 ".Accordingly, judging unit 1225 is judged a high strength bit " 0 " and a low-intensity bit " 0 " to represent the sign bit " 1 " have a minimum fiduciary level.In other words, the least significant bit (LSB) unit of memory cell M_1 is updated to the lowest reliable degree " 0 ".In addition, comprise hard bit " 0 " and soft bit " 00 " code word " 000 " be used for representing the least significant bit (LSB) unit of memory cell M_1.The code word that is used for expressing other memory cells is also carried out according to similar mode.Then, the code word of the binary digit of the first after the renewal is delivered to storage device 1227 in order to upgrade original code word.Then, the code word after storage device 1227 will upgrade offers decoding unit 1228 with execution error corrigendum running.In one embodiment, decoding unit 1228 carries out the soft decoding of an error correction (error correction soft decode) according to the code word after upgrading and notes that, the code word after the renewal is by comparing according to control lock and voltage V _LSBThe stressed data (binary digit) that+D is obtained and foundation control lock and voltage V _LSBObtained sign bit and getting.In other words, the soft decoding of error correction is carried out according to sign bit and stressed data (binary digit).If the code word after the error correction running is pointed out to upgrade correctly maybe can be corrected (the in other words soft decoding indication of error correction one result that can correct), then error correction circuit 1220 is this result notification control logic circuit 1210, and correct data are offered control logic circuit 1210.If the code word after the error correction running is pointed out to upgrade can not be corrected (the in other words soft decoding indication of error correction one result that can not correct), error correction circuit 1220 is with this result notification control logic circuit 1210, and control logic circuit 1210 control flash memories 1100 are according to control gate pole tension V _LSBThe storer cell of-D unit carries out one and reads running (D is a predetermined voltage spaces) again.According to control gate pole tension V _LSBThe stressed running that the storer cell of-D unit carries out can be considered second and reads running again.Note that, generally read the voltage spaces of running and the first stressed running and generally read the voltage spaces that operates with the second stressed running identical.Therefore, the rule of upgrading the code word fiduciary level should be similar, omits at this with the details that stores code word according to reading the obtained stressed data generation of running for the second time again.If the code word that error correction operates after the renewal of pointing out stressed running second time gained correctly maybe can be corrected (the in other words soft decoding indication of error correction one result that can correct), then error correction circuit 1220 is this result notification control logic circuit 1210, and correct data are offered control logic circuit 1210.If the code word that error correction operates after the renewal of pointing out stressed running second time gained can not be corrected (the in other words soft decoding indication of error correction one result that can not correct), error correction circuit 1220 is with this result notification control logic circuit 1210, and control logic circuit 1210 control flash memories 1100 carry out a stressed running (D is a predetermined voltage spaces) according to the storer cell of control gate pole tension VLSB+2D unit.The stressed running of carrying out according to the storer cell of control gate pole tension VLSB+2D unit can be considered the 3rd stressed running.In addition, by relatively reading the obtained binary digit of running again from generally reading running and first, can obtain generally reading bit change (bit flopping) sum that the binary digit of first in the running is read in running and first again, and it can be designated as bit changing number BF1.Similarly, by relatively reading the obtained binary digit of running again from generally reading running and second, can obtain generally reading the bit change sum that the binary digit of first in the running is read in running and second again, and it can be designated as bit changing number BF2.Bit changing number BF1 and BF2 can be used to follow the trail of the critical voltage an of the best.After details is specified in.

Please refer to Fig. 8, Fig. 8 explanation is to reading to encode to obtain from the binary digit of flash memory cells the synoptic diagram of correct data.When reading a target entity memory paging (for example, entity stores device paging P_0), control logic circuit 1210 control flash memories 1100 are according to the 3rd control gate pole tension V _LSB(for example, the memory cell M_0 of entity stores device paging P_0～M_K) execution one is read running with the least significant bit (LSB) unit of interpretation memory cell M_0～M_K to the memory cell of+2D.This stressed running can be regarded as reading again for the third time running.As shown in Figure 8, the binary digit of the first of this entity stores device paging is delivered to coding unit 1223.Note that each bit of those binary digits represents the soft bit of the least significant bit (LSB) unit of one of entity stores device paging P_0 storer cell unit.For example, the leftmost binary digit of those binary digits is " 0 ", it represents the soft bit of least significant bit (LSB) unit of the storer cell M_0 of entity stores device paging P_0.Note that binary digit shown in Figure 8 (reading data again) may be not exclusively identical with the sign bit.Because be V in order to the control gate pole tension of reading running for the third time again _LSB+ 2D is so utilizing grid-control voltage V _LSBWith V _LSB+ 2D reads critical voltage and drops on V _LSBWith V _LSBCan obtain different results during the memory cell of+2D.For example, according to control gate pole tension V _LSBThe sign bit of the least significant bit (LSB) unit of obtained memory cell M_0 is " 0 ", and according to control gate pole tension V _LSBThe soft bit of the least significant bit (LSB) unit of the memory cell M_0 that+2D is obtained is " 1 ".Therefore, scrambler 1223 need updated stored device unit M_0 least significant bit (LSB) unit the fiduciary level of code word.Details describes in detail in the back.

According to control gate pole tension V _LSBThe obtained stressed data of+2D (binary digit) are delivered to comparing unit 1224.Comparing unit 1224 accesses are stored in the sign bit of storage device 1227, and relatively sign bit and stressed data with the renewal code word.Note that, read again for the first time running with read again for the second time operate in some binary digit may be corresponding with it the sign bit different.The fiduciary level of those binary digits will no longer be updated.Comparing unit 1224 can be ignored those binary digits.1225 of judging units keep code word after this renewal fiduciary level.In other words, when high strength bit and low-intensity bit were updated, judging unit 1225 is kept the value of high strength bit and low-intensity bit.Inequality as if the stressed data (binary digit) that the sign bit is corresponding with it, comparing unit 1224 is indicated judging unit 1225 with this result.And judging unit 1225 is judged the fiduciary level that will keep this sign bit.In other words, do not change in order to the code word of expressing corresponding memory cell.Inequality as if the stressed data (binary digit) that the sign bit is corresponding with it, comparing unit 1224 is indicated judging unit 1225 with this result.And judging unit 1225 is judged the higher fiduciary level of fiduciary level to that will upgrade this sign bit.In other words, the code word that is used for expressing corresponding memory cell is changed.For example, according to the sign bit of the least significant bit (LSB) unit of the obtained memory cell M_0 of control gate pole tension VLSB be " 0 ", and according to control gate pole tension V _LSBThe soft bit of the least significant bit (LSB) unit of the memory cell M_0 that+2D is obtained is " 1 ".Accordingly, judging unit 1225 is judged a high strength bit " 0 " and a low-intensity bit " 1 " to represent the sign bit " 1 " have a higher fiduciary level.In other words, the least significant bit (LSB) unit of memory cell M_0 is updated to than high-reliability " 0 ".In addition, comprise hard bit " 0 " and soft bit " 01 " code word " 001 " be used for representing the least significant bit (LSB) unit of memory cell M_0.The code word that is used for expressing other memory cells is also carried out according to similar mode.Then, the code word of the binary digit of the first after the renewal is delivered to storage device 1227 in order to upgrade original code word.Then, the code word after storage device 1227 will upgrade offers decoding unit 1228 with execution error corrigendum running.In one embodiment, decoding unit 1228 carries out the soft decoding of an error correction according to the code word after upgrading.Note that the code word after the renewal is by comparing according to control lock and voltage V _LSBThe stressed data (binary digit) that+2D is obtained and foundation control lock and voltage V _LSBObtained sign bit and getting.In other words, the soft decoding of error correction is carried out according to sign bit and stressed data (binary digit).If the code word after the error correction running is pointed out to upgrade is correctly maybe to correct (the in other words soft decoding indication of error correction one result that can correct), then error correction circuit 1220 is this result notification control logic circuit 1210, and correct data are offered control logic circuit 1210.If the code word after the error correction running is pointed out to upgrade can not be corrected (the in other words soft decoding indication of error correction one result that can not correct), error correction circuit 1220 is with this result notification control logic circuit 1210, and control logic circuit 1210 control flash memories 1100 are according to control gate pole tension V _LSBThe storer cell of-2D unit carries out one and reads running (D is a predetermined voltage spaces) again.After details is specified in.

According to control gate pole tension V _LSBThe stressed running that the storer cell of-2D unit carries out can be considered quadruple and reads running.Note that, read generally that the voltage spaces of running is read in running and the 3rd again and generally to read the voltage spaces that running and quadruple read to operate identical.Therefore, the rule of upgrading the code word fiduciary level should be similar, reads the obtained stressed data generation of running again according to the 4th time and omit at this with the details that stores code word.If the code word that error correction operates after the renewal of pointing out the 4th stressed running gained correctly maybe can be corrected (the in other words soft decoding indication of error correction one result that can correct), then error correction circuit 1220 is this result notification control logic circuit 1210, and correct data are offered control logic circuit 1210.If the code word that error correction operates after the renewal of pointing out the 4th stressed running gained can not be corrected (the in other words soft decoding indication of error correction one result that can not correct), error correction circuit 1220 is with this result notification control logic circuit 1210, and control logic circuit 1210 control flash memories 1100 carry out a stressed running according to the storer cell of control gate pole tension VLSB+3D unit.The stressed running of carrying out according to the storer cell of control gate pole tension VLSB+3D unit can be considered the 5th stressed running.In addition, by relatively reading the obtained binary digit of running again from generally reading running and the 3rd, can obtain generally reading bit change (bit flopping) sum that the binary digit of first in the running is read in running and the 3rd again, and it can be designated as bit changing number BF3.Similarly, by relatively reading to operate obtained binary digit from generally reading running with quadruple, can obtain generally read running read to operate with quadruple in the bit change sum of binary digit of first, and it can be designated as bit changing number BF4.Bit changing number BF3 and BF4 can be used to follow the trail of the critical voltage an of the best.After details is specified in.

Please refer to Fig. 9, Fig. 9 explanation is to reading to encode to obtain from the binary digit of flash memory cells the synoptic diagram of correct data.When reading a target entity memory paging (for example, entity stores device paging P_0), control logic circuit 1210 control flash memories 1100 are according to the 5th control gate pole tension V _LSB(for example, the memory cell M_0 of entity stores device paging P_0～M_K) execution one is read running with the least significant bit (LSB) unit of interpretation memory cell M_0～M_K to the memory cell of+5D.This stressed running can be regarded as the 5th time and read running again.As shown in Figure 9, the binary digit of the first of this entity stores device paging is delivered to coding unit 1223.Note that each bit of those binary digits represents the soft bit of the least significant bit (LSB) unit of one of entity stores device paging P_0 storer cell unit.For example, the rightmost binary digit of those binary digits is " 0 ", it represents the soft bit of least significant bit (LSB) unit of the storer cell M_0 of entity stores device paging P_0.Note that binary digit shown in Figure 9 (reading data again) may be not exclusively identical with the sign bit.Because be V in order to the control gate pole tension that carries out reading again for the 5th time running _LSB+ 3D is so utilizing grid-control voltage V _LSBWith V _LSB+ 3D reads critical voltage and drops on V _LSBWith V _LSBCan obtain different results during the memory cell of+3D.For example, according to control gate pole tension V _LSBThe sign bit of the least significant bit (LSB) unit of obtained memory cell M_K is " 1 ", and according to control gate pole tension V _LSBThe soft bit of the least significant bit (LSB) unit of the memory cell M_0 that+3D is obtained is " 1 ".Therefore, scrambler 1223 need updated stored device unit M_K least significant bit (LSB) unit the fiduciary level of code word.Details describes in detail in the back.

According to control gate pole tension V _LSBThe obtained stressed data of+3D (binary digit) are delivered to comparing unit 1224.Comparing unit 1224 accesses are stored in the sign bit of storage device 1227, and relatively sign bit and stressed data with the renewal code word.Note that some binary digit may be different with its corresponding sign bit in first, second, third, fourth stressed running.The fiduciary level of those binary digits will no longer be updated.Comparing unit 1224 can be ignored those binary digits.1225 of judging units keep code word after this renewal fiduciary level.In other words, when high strength bit and low-intensity bit were updated, judging unit 1225 is kept the value of high strength bit and low-intensity bit.If the sign bit is identical with its corresponding stressed data (binary digit), comparing unit 1224 is indicated judging unit 1225 with this result.In other words, do not change in order to the code word of expressing corresponding memory cell.Inequality as if the stressed data (binary digit) that the sign bit is corresponding with it, comparing unit 1224 is indicated judging unit 1225 with this result.And judging unit 1225 is judged the higher fiduciary level of fiduciary level to that will upgrade this sign bit.In other words, the code word that is used for expressing corresponding memory cell is changed.For example, according to control gate pole tension V _LSBThe sign bit of the least significant bit (LSB) unit of obtained memory cell M_K is " 0 ", and according to control gate pole tension V _LSBThe soft bit of the least significant bit (LSB) unit of the memory cell M_K that+3D is obtained is " 1 ".Accordingly, judging unit 1225 is judged a high strength bit " 1 " and a low-intensity bit " 0 " to represent the sign bit " 1 " have a higher fiduciary level.In other words, the least significant bit (LSB) unit of memory cell M_K is updated to than high-reliability " 0 ".In addition, comprise hard bit " 0 " and soft bit " 10 " code word " 010 " be used for representing the least significant bit (LSB) unit of memory cell M_K.The code word that is used for expressing other memory cells is also carried out according to similar mode.Then, the code word of the binary digit of the first after the renewal is delivered to storage device 1227 in order to upgrade original code word.Then, the code word after storage device 1227 will upgrade offers decoding unit 1228 with execution error corrigendum running.In one embodiment, decoding unit 1228 carries out the soft decoding of an error correction according to the code word after upgrading.Note that the code word after the renewal is by comparing according to control lock and voltage V _LSBThe stressed data (binary digit) that+3D is obtained and foundation control lock and voltage V _LSBObtained sign bit and getting.In other words, the soft decoding of error correction is carried out according to sign bit and stressed data (binary digit).If the code word after the error correction running is pointed out to upgrade is correctly maybe to correct (the in other words soft decoding indication of error correction one result that can correct), then error correction circuit 1220 is this result notification control logic circuit 1210, and correct data are offered control logic circuit 1210.If the code word after the error correction running is pointed out to upgrade can not be corrected (the in other words soft decoding indication of error correction one result that can not correct), error correction circuit 1220 is with this result notification control logic circuit 1210, and control logic circuit 1210 control flash memories 1100 carry out a stressed running according to the storer cell of control gate pole tension VLSB-3D unit.After details is specified in.

According to control gate pole tension V _LSBThe stressed running that the storer cell of-3D unit carries out can be considered sixfold and reads running.Note that, read generally that the voltage spaces of running is read in running and the 5th again and generally to read the voltage spaces that running and sixfold read to operate identical.Therefore, the rule of upgrading the code word fiduciary level should be similar, reads to operate obtained stressed data generation according to sixfold and omit at this with the details that stores code word.If the code word that error correction operates after the renewal of pointing out the 6th stressed running gained is correctly maybe to correct (the in other words soft decoding indication of error correction one result that can correct), then error correction circuit 1220 is this result notification control logic circuit 1210, and correct data are offered control logic circuit 1210.If the code word that error correction operates after the renewal of pointing out the 6th stressed running gained is to correct (the in other words soft decoding indication of error correction one result that can not correct), error correction circuit 1220 is with this result notification control logic circuit 1210, and control logic circuit 1210 control flash memories 1100 are according to control gate pole tension V _LSBThe storer cell of+4D unit carries out one and reads running again.According to control gate pole tension V _LSBThe stressed running that the storer cell of+4D unit carries out can be considered septuple and reads running.Perhaps, if the code word that error correction operates after the renewal of pointing out the 6th stressed running gained is to correct (data that in other words are stored in memory cell can't correctly be obtained), error correction circuit 1220 is with this result notification control logic circuit 1210, and control logic circuit 1210 judgements are read failure to target entity memory paging P_0, and will read the failure repayment and give a main frame (host).But read the number of times arbitrary decision of running, it is non-to be restriction of the present invention.In addition, by relatively reading the obtained binary digit of running again from generally reading running and the 5th, can obtain generally reading bit change (bit flopping) sum that the binary digit of first in the running is read in running and the 5th again, and it can be designated as bit changing number BF5.Similarly, by relatively reading to operate obtained binary digit from generally reading running with sixfold, can obtain generally read running read to operate with sixfold in the bit change sum of binary digit of first, and it can be designated as bit changing number BF6.Bit changing number BF5 and BF6 can be used to follow the trail of the critical voltage an of the best.

Please refer to Figure 10, Figure 10 illustrates the synoptic diagram of the corresponding relation of code word and memory cell.For example, when the hard bit received according to one of the obtained memory cell of initial control gate pole tension VLSB, sign bit and default this sign bit that scrambler 1223 will this hard bit be considered as the least significant bit (LSB) unit of this memory cell have the highest fiduciary level, for example, code word " 011 " representative very strong " 0 ", and code word " 111 " representative very strong " 1 ".Yet, to read again in the running for the first time, critical voltage is positioned at V _LSBWith V _LSBMemory cell between the+D will be corresponded to very weak " 0 ", and be encoded to " 000 ".Reading again in the running for the second time, critical voltage is positioned at V _LSBWith V _LSBMemory cell between the-D will be corresponded to very weak " 1 ", and be encoded to " 100 ".Reading again in the running for the third time, critical voltage is positioned at V _LSB+ D and V _LSBMemory cell between the+2D will be corresponded to weak " 0 ", and be encoded to " 001 ".Read again in the running at the 4th time, critical voltage is positioned at V _LSB-D and V _LSBMemory cell between the-2D will be corresponded to weak " 1 ", and be encoded to " 101 ".Read again in the running at the 5th time, critical voltage is positioned at V _LSB+ 2D and V _LSBMemory cell between the+3D will be corresponded to strong " 0 ", and be encoded to " 010 ".Read again in the running at the 6th time, critical voltage is positioned at V _LSB-2D and V _LSBMemory cell between the-3D will be corresponded to weak " 1 ", and be encoded to " 110 ".The fiduciary level of (the hard bit) of sign bit notes that the corresponding relation of code word and critical voltage can at random determine, as long as can be come identification by different code words.In addition, the code word size of code word is three bits, its than a memory cell generally read running with first to the 6th this read binary digit obtained in the running (word string) and come shortly.For instance, the critical voltage of a memory cell is positioned at V _LSB+ 2D and V _LSBBetween+the 3D.Generally reading running with first to the 6th this binary digit that reads the least significant bit (LSB) unit of obtained this memory cell in the running be " 0000000 " (binary digit combination BS8).This binary digit comprises seven bits, and it is long than the code word size of code word.Could execution error correct running if error correction decoding device 1222 needs to store whole seven bits, but not only need store three bits, the error correction decoding device needs more storage space.Therefore, will read binary bit code word obtained in the running in difference and be encoded to short code word and can reduce storage space, and cost also can reduce.

In another embodiment, if error correction running indication is read the renewal code word that obtains in the running again at the 6th time and can not be corrected (in other words, the data that are stored in memory cell can't be by correct obtaining) decoding unit 1228 start general like than (LLR, log-likelihood ratio) training program with adjust in order to execution error correct soft decoding general like than corresponding rule (LLR mapping rule).Please contrast Figure 11, Figure 11 is in order to illustrate the calcspar of decoding unit 1228.Decoding unit 1228 comprises without exception like than training unit 12280, without exception like than corresponding unit 12282 and a decoding circuit 12284.Note that only have technical characterictic related to the present invention just to be shown among Figure 11.That is, decoding unit 1228 can comprise other elements in order to carry out other functions.Because the 6th stressed running can't obtain correct data, so be used for generally seemingly should adjusting than corresponding rule like the general of ratio upgrading back code word correspondence one-tenth.Details describes in detail in the back.

Code word after the 6th time is read again the renewal that obtains target entity storage paging (for example entity stores device paging P_0) in the running.General like than corresponding unit 12282 according to predetermined general like than corresponding rule with code word after the renewal of target entity memory paging corresponding become one group first general like than respective value.For instance, each code word that is used for expressing each memory cell corresponds to one specific general like than respective value.First group general like offering decoding circuit 12284 than respective value.Decoding circuit 12284 is general like carry out error correction running than respective value according to this first group.If according to this this first group general like error correction running indication one result that can not correct who carries out than respective value, the statistical nature of the correct data of general code word like the error correction unit of collecting the code word of one of these flash memories 1100 error correction unit that can correct than training unit 12280 and can correcting.For instance, this target entity memory paging comprises 8 sections, and individual section is an error correction unit.In these 8 sections, the first section S0 can not correct, and other sections are to correct.General like the code word that in the code word of target memory paging, obtains the second section S1 than training unit 12280.The second section S1 is adjacent to the first section S1 and comprises x memory cell.In this x memory cell, have n0 memory cell to be encoded to code word " 000 ", have n1 memory cell to be encoded to code word " 001 " ... and have n7 memory cell to be encoded to code word " 111 ".After the second section S1 being carried out the error correction running, can correctly obtain the correct data of the second section S1.Be encoded as for those " 000 " memory cell, have A0 memory cell correctly to be decoded as 1, and have A0 memory cell correctly to be decoded as 0.Therefore, code word " 000 " general like being configured as log (A0/B0) than respective value.Code word " 001 ", code word " 010 " ... and code word " 111 " general like also being obtained similarly than respective value.Code word and the statistical nature gained collected from the code word of the second section S1 and the correct data of the second section S1 general like can be considered as general like more regular than corresponding after the adjustment than the corresponding relation between the respective value.General general like than corresponding tables like can build up one than corresponding rule after the adjustment.Because the second section S1 can correct, so general like may show predetermined general like also suitable more general like more regular than corresponding than corresponding rule of a ratio than corresponding rule after the obtained adjustment of the second section S1.

Generally seemingly can offer than corresponding rule after the adjustment is general seemingly than corresponding unit 12282.Thus, general like than corresponding unit 12282 according to the general code word like the target entity memory paging that will obtain from the 6th stressed running than corresponding rule after adjusting corresponding become second group general like than respective value.Second group general like offering decoding circuit 12284 than respective value.Decoding circuit 12284 is general like carry out error correction running (for example soft decoding running of error correction) than respective value according to second group.If error correction running indication one result that can correct, general after the adjustment decoded like can be used to next entity stores device paging than respective value.For instance, running is read in another entity stores device paging (for example entity stores device paging P_1) of 1100 pairs of flash memories 1100 of control logic circuit 1210 control flash memories, and obtains the code word of another entity stores device paging.General like than corresponding unit 12282 general like obtaining one of this code word group than corresponding rule generally seemingly than respective value after according to this adjustments.12284 pairs of these groups of decoding circuit are general like carry out the error correction running than respective value.

Note that generally seemingly obtaining than the available different mode of corresponding rule after the adjustment.For example, general like can pass through other sections (for example section S2, S3 than corresponding rule after the adjustment ... the statistical nature of code word and S7) and the correct data of these other sections and getting.In addition, generally seemingly can get by other code word and this statistical natures that can correct the correct data of entity stores device paging that can correct entity stores device paging (for example entity stores device paging P_N) than corresponding rule after the adjustment.This can correct the paging of entity stores device can be adjacent to this target entity storage paging physically.And find out general like similar than the aforesaid embodiment of details drizzle of corresponding rule after the adjustment.Therefore, for the sake of clarity those explanations are omitted.

Please refer to Figure 12, it is the process flow diagram that the program of the data that are stored in flash memory is read in explanation.In step 200, control logic circuit 1210 control flash memories 1100 are according to initial threshold voltage V _LSBMemory cell to a target entity memory paging generally reads running, with first binary digit of obtaining a paging in order to represent the least significant bit (LSB) unit of each memory cell respectively.In step 202, error correction decoding device 1222 carries out the error correction hard decoder according to first binary digit of this paging.If result that can correct of error correction hard decoder indication enters step 214, read the paging of next entity stores device.In step 204, if result that cannot correct of error correction hard decoder indication, control logic circuit 1210 control flash memories 1100 are according to initial threshold voltage V _LSB+ D and V _LSBThe memory cell of the target entity memory paging of-D carries out first and second and reads running again, with second binary digit of obtaining two pagings in order to represent the least significant bit (LSB) unit of each memory cell respectively.Error correction decoding device 1222 according to from first binary digit with second binary digit coding must code word carry out the soft decoding of error correction.If result that can correct of the soft decoding indication of error correction then enters step 212, carry out the critical voltage tracing program.Details describes in detail in the back.Step 206, if result that can not correct of the soft decoding indication of error correction, control logic circuit 1210 control flash memories 1100 are according to initial threshold voltage V _LSB+ 2D and V _LSBThe memory cell of the target entity memory paging of-2D carry out the 3rd and quadruple read running, with the 3rd binary digit of obtaining two pagings in order to represent the least significant bit (LSB) unit of each memory cell respectively.Error correction decoding device 1222 carries out the soft decoding of error correction according to the code word that gets from first binary digit, second binary digit and the 3rd binary digit coding.If result that can correct of the soft decoding indication of error correction then enters step 212, carry out the critical voltage tracing program.In step 208, if result that can not correct of the soft decoding indication of error correction, control logic circuit 1210 control flash memories 1100 are according to initial threshold voltage V _LSB+ 3D and V _LSBThe memory cell of the target entity memory paging of-3D carry out the 5th and sixfold read running, with the 4th binary digit of obtaining two pagings in order to represent the least significant bit (LSB) unit of each memory cell respectively.Error correction decoding device 1222 carries out the soft decoding of error correction according to the code word that gets from first binary digit, second binary digit, the 3rd binary digit and the 4th binary digit coding.If result that can correct of the soft decoding indication of error correction then enters step 212, carry out the critical voltage tracing program.If result that can not correct of the soft decoding of error correction indication, enter generally like than training stage (LLR training stage) in step 210, generally be specified in Figure 11 and related description like the details than the training stage.Therefore details is omitted in the hope of succinctly in this.

Please refer to Figure 13, the synoptic diagram that the critical voltage of its explanation target entity memory paging distributes.The critical voltage of mark entity stores device paging distributes and derives from different stressed runnings.For example, critical voltage is positioned at V _LSBWith V _LSBThe quantity of the memory cell the between+D is X1.And quantity X1 equals bit changing number BF1.As previously mentioned, bit changing number BF1 reads the binary digit of running gained again and gets from more generally reading running and first.Similarly, critical voltage is positioned at V _LSBWith V _LSBThe quantity of the memory cell the between-D is X2.And quantity X2 equals bit changing number BF2.Critical voltage is positioned at V _LSB+ D and V _LSBThe quantity of the memory cell the between+2D is X3.And equaling bit changing number BF3, quantity X3 deducts bit changing number BF1.Similarly, critical voltage is positioned at V _LSB-D and V _LSBThe quantity of the memory cell the between-2D is X4.And quantity X4 equals bit changing number BF4 to deduct bit changing number BF2.In addition, critical voltage is positioned at V _LSB+ 2D and V _LSBThe quantity of the memory cell the between+3D is X5.And equaling bit changing number BF5, quantity X5 deducts bit changing number BF3 and bit changing number BF1.Similarly, critical voltage is positioned at V _LSB-2D and V _LSBThe quantity of the memory cell the between-3D is X6.And equaling bit changing number BF6, quantity X6 deducts bit changing number BF2 and bit changing number BF4.Critical voltage tracing unit 1230 is found out quantity X1～X6, and judges a critical voltage moving direction SD according to quantity X1～X6.Because quantity X1 is greater than quantity X2, preferable critical voltage may lower voltage of migration but not V _LSBIn addition, this preferable critical voltage may fall within V _LSB-D is because little relative with X4 of quantity X2.Note that, at preferable critical voltage (V for example _LSB-D) find after, control logic circuit 1210 can use this preferable voltage as the initial threshold voltage (control gate pole tension) of the next entity stores device paging of reading flash memory circuit 1100.

The above only is preferred embodiment of the present invention, and all equalizations of doing according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.

Claims (10)

1. one kind in order to read the method for the data that are stored in a flash memory, and this method comprises:

Control this flash memory running is read in the one first memory paging execution one of this flash memory;

Obtain one first code word of this first memory paging;

General general seemingly than respective value like obtain this first code word than corresponding rule one first group according to one first;

General like carry out error correction running than respective value according to this first group;

If it is generally indicate a result that can not correct like carry out this error correction running than respective value according to this first group, then generally general seemingly than respective value like obtain this first code word than corresponding rule one second group according to one second; And

General like carry out this error correction running than respective value according to this second group.

2. according to claim 1 in order to read the method for the data that are stored in a flash memory, it is characterized in that this is second general obtained like add up feature than one of the correct data of one second code word of corresponding rule by collecting this flash memory and this flash memory.

3. according to claim 2 in order to read the method for the data that are stored in a flash memory, it is characterized in that, this second generally seemingly be worth the part of the rule of correspondence by collecting this first code word and this part of this first code word correct data one to add up feature obtained.

4. according to claim 3 in order to read the method for the data that are stored in a flash memory, it is characterized in that, general point out that like the error correction running of carrying out than respective value one first section of this first memory paging can not correct according to this first group, and one second section that is adjacent to this first section can be corrected, and this is second general obtained like add up feature than one of the correct data of one second code word of corresponding rule by collecting this second section and this second section.

5. according to claim 3 in order to read the method for the data that are stored in a flash memory, it is characterized in that, general point out that like the error correction running of carrying out than respective value one first section of this first memory paging can not correct according to this first group, and other sections of this first section can be corrected, and this is second general obtained like add up feature than one of the correct data of one second code word of corresponding rule by collecting this second section and these other sections.

6. according to claim 2 in order to read the method for the data that are stored in a flash memory, it is characterized in that this is second general obtained like add up feature than one of the correct data of one second code word of the second memory paging of corresponding rule by collecting contiguous this first memory paging and this second memory paging.

7. according to claim 1ly it is characterized in that in order to read the method for the data that are stored in a flash memory that this is second general like obtaining by following steps than corresponding rule:

Obtain one second code word from this flash memory;

This second code word is carried out this error correction running;

Obtain the correct data of this second code word; And

A statistics feature of collecting this correct data and this second code word is second general like more regular than corresponding to obtain this.

8. according to claim 1ly it is characterized in that in order to read the method for the data that are stored in a flash memory this method more comprises:

Controlling this flash memory carries out this to one the 3rd memory paging of this flash memory and reads running;

Obtain one the 3rd code word of the 3rd memory paging;

Second general general like than respective value like obtain the 3rd code word than corresponding rule one the 3rd group according to this; And

General like carry out this error correction running than respective value to the 3rd group.

9. one kind in order to read the Memory Controller of the data that are stored in a flash memory, and this Memory Controller comprises:

One control logic circuit reads running to obtain one first code word of this first memory paging in order to control this flash memory to the first memory paging execution one of this flash memory;

Without exception seemingly than corresponding unit, in order to general general seemingly than respective value like obtain this first code word than corresponding rule one first group according to one first; And

One decoding circuit is in order to general like carry out error correction running than respective value according to this first group;

Wherein if according to this first group general like carry out than respective value that this error correction running indication one can not correct as a result the time, then should be general like more be used for than corresponding unit according to one second general like obtain this first code word than corresponding rule one second group general like than respective value, and that this decoding circuit more is used for according to this second group is general like carry out this error correction running than respective value.

10. one kind in order to read the accumulator system of the data that are stored in a flash memory, and this accumulator system comprises:

One control logic circuit reads running to obtain one first code word of this first memory paging in order to control this flash memory to the first memory paging execution one of this flash memory;

Without exception seemingly than corresponding unit, in order to general general seemingly than respective value like obtain this first code word than corresponding rule one first group according to one first; And

One decoding circuit is in order to general like carry out error correction running than respective value according to this first group;

Wherein if according to this first group general like carry out than respective value that this error correction running indication one can not correct as a result the time, then should be general like more be used for than corresponding unit according to one second general like obtain this first code word than corresponding rule one second group general like than respective value, and that this decoding circuit more is used for according to this second group is general like carry out this error correction running than respective value.

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