CN105304143B - Coding/decoding method, memorizer control circuit unit and memory storage apparatus - Google Patents
Coding/decoding method, memorizer control circuit unit and memory storage apparatus Download PDFInfo
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- CN105304143B CN105304143B CN201410347359.6A CN201410347359A CN105304143B CN 105304143 B CN105304143 B CN 105304143B CN 201410347359 A CN201410347359 A CN 201410347359A CN 105304143 B CN105304143 B CN 105304143B
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Abstract
A kind of coding/decoding method of present invention offer, memorizer control circuit unit and memory storage apparatus.This coding/decoding method includes：It sends to read multiple storage units to obtain multiple reading instruction sequences, and obtains multiple reliability informations corresponding to each multiple.This coding/decoding method further includes：The summation for the multiple reliability informations for meeting examination condition in these reliability informations is calculated, and this summation is added into balancing information to obtain the weight for corresponding to first in these with the first syndrome.This coding/decoding method further includes：Judge these positions whether have an at least mistake, and if these positions have an at least mistake, according to the weight execute iterative decoding procedures.
Description
Technical field
The invention relates to a kind of coding/decoding methods, and being used for duplicative non-volatile memories in particular to one kind
Coding/decoding method, memorizer control circuit unit and the memory storage apparatus of device module.
Background technology
Digital camera, mobile phone and MP3 player are very rapid in growth over the years so that consumer is to storage
The demand of media also rapidly increases.Since reproducible nonvolatile memorizer module (for example, flash memory) has data
It is non-volatile, power saving, small, and without characteristics such as mechanical structures, so being very suitable for being built into above-mentioned illustrated various
In portable multimedia device.
In general, the data of write-in to reproducible nonvolatile memorizer module can all be compiled according to an error correcting code
Code.Read data will also pass through corresponding decoding program from reproducible nonvolatile memorizer module.However, error correction
The corrigendum ability of code has its upper limit, and in reproducible nonvolatile memorizer module data the probability of mistake occurs can be with
Service life changes together.Therefore, how to increase decoded corrigendum ability and correctness, field technology personnel are of concern thus
Problem.
Invention content
A kind of coding/decoding method of present invention offer, memorizer control circuit unit and memory storage apparatus, can be effectively
Improve decoded corrigendum ability.
One example of the present invention embodiment provides a kind of coding/decoding method for reproducible nonvolatile memorizer module,
The reproducible nonvolatile memorizer module includes multiple storage units, this coding/decoding method includes：It sends and reads sequence of instructions
Row, wherein the reading instruction sequence is reading multiple storage units to obtain multiple positions；Multiple reliability informations are obtained,
In each reliability information correspond to one of institute's rheme；It calculates and meets the multiple of examination condition in the reliability information
The summation of reliability information；The summation is verified with obtaining first corresponded in institute's rheme with first plus balancing information
The weight of son；Judge whether institute's rheme has an at least mistake；And if institute's rheme have an at least mistake, according to the weight
Execute iterative decoding procedures.
In one example of the present invention embodiment, it is above-mentioned judge these positions whether have an at least wrong step include：
Odd-even check program is executed to obtain the multiple syndromes for including the first syndrome, wherein each institute's rheme is corresponding to institute's rheme
To at least one of the syndrome；And judge whether institute's rheme has an at least mistake according to the syndrome.Institute
It is according to performed by parity-check matrix to state odd-even check program, and the parity-check matrix includes multiple limitations
(constraint), the step of meeting the summation of the reliability information of examination condition in the above-mentioned calculating reliability information
Including：According to the first limitation for corresponding to first syndrome in the limitation, determine to meet from the reliability information
The reliability information of the examination condition.
In one example of the present invention embodiment, above-mentioned first limitation includes multiple elements, and is limited according to described first
Determine that the step of meeting the reliability information of the examination condition includes from the reliability information：According to the element
Intermediate value is multiple elements of " 1 ", and the reliability information for meeting the examination condition is determined from the reliability information.
It is above-mentioned that the summation is corresponded into institute plus the balancing information to obtain in one example of the present invention embodiment
The step of stating first weight with first syndrome include：By the summation plus the balancing information to obtain
First assessment information；And information divided by the second assessment information are assessed to obtain corresponding to described first and institute by described first
The weight of the first syndrome is stated, wherein the second assessment information is to correspond to described first in the reliability information
Reliability information.
In one example of the present invention embodiment, above-mentioned coding/decoding method further includes：From meeting described in the examination condition
Selection corresponds to the deputy reliability information in institute's rheme in reliability information, wherein the second is different from described the
One；And Dynamic gene will be multiplied by obtain the balancing information corresponding to the deputy reliability information.
One example of the present invention embodiment proposes a kind of storage for controlling reproducible nonvolatile memorizer module
Device control circuit unit, wherein reproducible nonvolatile memorizer module include multiple storage units.This memory control electricity
Road unit includes host interface, memory interface, memory management circuitry and error checking circuit.Host interface is to electrical
It is connected to host system.Memory interface is electrically connected to reproducible nonvolatile memorizer module.Memory management
Circuit is electrically connected to host interface and memory interface, wherein memory management circuitry to send reading instruction sequence, and
And the reading instruction sequence is to read the storage unit, to obtain multiple positions.Error checking circuit is electrically connected to institute
Memory management circuitry is stated and to obtain multiple reliability informations, wherein each reliability information corresponds to its of institute's rheme
One of.Here, error checking circuit also to calculate meet in the reliability information examination condition multiple reliabilitys letter
The summation of breath, and by the summation plus balancing information with obtain correspond to institute's rheme in first with the first syndrome
Weight.In addition, also to judge, whether rheme has an at least mistake to error checking circuit, if institute's rheme has at least one mistake
Accidentally, error checking circuit is also to according to weight execution iterative decoding procedures.
In one example of the present invention embodiment, above-mentioned error checking circuit judges whether institute's rheme has an at least mistake
Operation include：It includes the multiple of first syndrome that error checking circuit executes odd-even check program to obtain to institute's rheme
Syndrome wherein each institute's rheme is corresponded to at least one of the syndrome, and judges according to the syndrome
Whether institute's rheme has an at least mistake.The odd-even check program be according to performed by parity-check matrix, and it is described strange
Even parity check matrix includes multiple limitations.Above-mentioned error checking circuit, which calculates, meets the examination condition in the reliability information
The operation of the summation of the reliability information includes：Error checking circuit according in the limitation correspond to first syndrome
The first limitation, determine to meet the reliability information of the examination condition from the reliability information.
In one example of the present invention embodiment, it is above-mentioned first limitation include multiple elements, and error checking circuit according to
First limitation determines that the operation for the reliability information for meeting the examination condition includes from the reliability information：Mistake
Checking circuit determines to meet the examination item from the reliability information according to multiple elements that the element intermediate value is " 1 "
The reliability information of part.
In one example of the present invention embodiment, above-mentioned error checking circuit by the summation plus the balancing information with
Acquisition corresponds to described first and the operation of the weight of first syndrome includes：Error checking circuit adds the summation
The upper balancing information assesses information divided by the second assessment information to obtain to obtain the first assessment information, and by described first
Corresponding to described first and the weight of first syndrome, wherein the second assessment information is in the reliability information
Corresponding to the primary reliability information.
In one example of the present invention embodiment, above-mentioned error checking circuit is also to from the institute for meeting the examination condition
State in reliability information the deputy reliability information that selection corresponds in institute's rheme, wherein the second be different from it is described
First, and error checking circuit also to will correspond to the deputy reliability information be multiplied by Dynamic gene with
Obtain the balancing information.
One example of the present invention embodiment proposes a kind of memory storage apparatus comprising connecting interface unit can be made carbon copies
Formula non-volatile memory module and memorizer control circuit unit.Reproducible nonvolatile memorizer module includes multiple deposits
Storage unit.Connecting interface unit is electrically connected to host system.Memorizer control circuit unit is electrically connected to connection and connects
Mouth unit and reproducible nonvolatile memorizer module, and to send reading instruction sequence, wherein the reading instructs
Sequence is to read the storage unit, to obtain multiple positions.Here, memorizer control circuit unit also to obtain it is multiple can
By spending information, wherein each reliability information corresponds to one of institute's rheme.In addition, memorizer control circuit unit is also used
To calculate the summation for the multiple reliability informations for meeting examination condition in the reliability information, and by the summation plus flat
Weighing apparatus information is to obtain the weight for corresponding to first in institute's rheme with the first syndrome.Memorizer control circuit unit also to
Judge institute's rheme whether have an at least mistake, and if institute's rheme have an at least mistake, memorizer control circuit unit is also
To execute iterative decoding procedures according to the weight.
In one example of the present invention embodiment, whether above-mentioned memorizer control circuit unit judges institute rheme has at least
One mistake operation include：It includes described first that memorizer control circuit unit executes odd-even check program to obtain to institute's rheme
Multiple syndromes of syndrome, wherein each institute's rheme is corresponded to at least one of the syndrome；And memory
Control circuit unit judges whether institute's rheme has an at least mistake according to the syndrome.The odd-even check program is basis
Performed by parity-check matrix, and the parity-check matrix includes multiple limitations.Above-mentioned memorizer control circuit unit meter
The operation for calculating the summation for the reliability information for meeting the examination condition in the reliability information includes：Memory controls
Circuit unit determines symbol according to the first limitation for corresponding to first syndrome in the limitation from the reliability information
Close the reliability information of the examination condition.
In one example of the present invention embodiment, above-mentioned first limitation includes multiple elements, and memorizer control circuit list
The behaviour that member determines to meet the reliability information of the examination condition from the reliability information according to first limitation
Work includes：Memorizer control circuit unit is according to multiple elements that the element intermediate value is " 1 ", from the reliability information certainly
Surely meet the reliability information of the examination condition.
In one example of the present invention embodiment, the summation is added the balance by above-mentioned memorizer control circuit unit
Information corresponds to the operation of described first and the weight of first syndrome and includes to obtain：Memorizer control circuit unit
By the summation plus the balancing information to obtain the first assessment information；And memorizer control circuit unit is by described first
Assessment information divided by one second assessment information correspond to described first and the weight of first syndrome, wherein institute to obtain
It is to correspond to the primary reliability information in the reliability information to state the second assessment information.
In one example of the present invention embodiment, above-mentioned memorizer control circuit unit is also to from meeting the examination item
Selection corresponds to the deputy reliability information in institute's rheme in the reliability information of part, wherein the second is different
In described first.Memorizer control circuit unit is also multiplied by tune will correspond to the deputy reliability information
Integral divisor is to obtain the balancing information.
In one example of the present invention embodiment, the above-mentioned value corresponding to the deputy reliability information is symbol
It closes minimum in the value of the reliability information of the examination condition.
In one example of the present invention embodiment, the above-mentioned value corresponding to the deputy reliability information is according with
Close the value that the reliability information corresponding to described first is merely greater than in the reliability information of the examination condition.
In one example of the present invention embodiment, the value of above-mentioned balancing information is positive correlation (positive
Correlation) the row weight of the first limitation corresponding in parity-check matrix in first syndrome.
It is of the invention when the position read from reproducible nonvolatile memorizer module has mistake based on above-mentioned
One exemplary embodiment can calculate verification weight information according to the weighted value corresponding to each, and thus determine which to be updated
Position.In particular, coding/decoding method, memorizer control circuit unit and memory storage apparatus that exemplary embodiment of the present invention proposes are
It is reliable in the position calculated at present according to the whole reliability information, the non-corresponding that correspond to each in each limitation
Minimum value in degree information and the weighted value of each is calculated corresponding to the reliability information of the position calculated at present.Base
This, can effectively increase decoded corrigendum ability.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to coordinate attached drawing to make
Carefully it is described as follows.
Description of the drawings
Fig. 1 is that the example of the host system and memory storage apparatus shown by an exemplary embodiment according to the present invention shows
It is intended to；
Fig. 2 is that computer, input/output device and the memory storage shown by an exemplary embodiment according to the present invention fill
The example schematic set；
Fig. 3 is that the example of the host system and memory storage apparatus shown by an exemplary embodiment according to the present invention shows
It is intended to；
Fig. 4 is the schematic block diagram for showing memory storage apparatus shown in FIG. 1；
Fig. 5 is the summary of the reproducible nonvolatile memorizer module shown by an exemplary embodiment according to the present invention
Block diagram；
Fig. 6 is the example schematic of the memory cell array shown by an exemplary embodiment according to the present invention；
Fig. 7 is the management reproducible nonvolatile memorizer module shown by an exemplary embodiment according to the present invention
Example schematic；
Fig. 8 is the schematic block diagram of the memorizer control circuit unit shown by an exemplary embodiment according to the present invention；
Fig. 9 is the example schematic of the parity-check matrix shown by an exemplary embodiment according to the present invention；
Figure 10 is the critical voltage point of the SLC type flash memory modules shown by an exemplary embodiment according to the present invention
The example schematic of cloth；
Figure 11 is the example schematic of the matrix multiple shown by an exemplary embodiment according to the present invention；
Figure 12 is the example schematic of the weight matrix shown by an exemplary embodiment according to the present invention；
Figure 13 be code word shown by an exemplary embodiment according to the present invention, reliability information, parity-check matrix with
The example schematic of correspondence between syndrome；
Figure 14 is the example schematic of the calculated weight shown by an exemplary embodiment according to the present invention；
Figure 15 is the example schematic of the matrix multiple shown by an exemplary embodiment according to the present invention；
Figure 16 is the example schematic of the verification weight information shown by an exemplary embodiment according to the present invention；
Figure 17 is the flow chart of the coding/decoding method shown by an exemplary embodiment according to the present invention.
Reference sign：
1000：Host system；
1100：Computer；
1102：Microprocessor；
1104：Random access memory；
1106：Input/output device；
1108：System bus；
1110：Data transmission interface；
1202：Mouse；
1204：Keyboard；
1206：Display；
1208：Printer；
1212：USB flash disk；
1214：Storage card；
1216：Solid state disk；
1310：Digital camera；
1312：SD card；
1314：Mmc card；
1316：Memory stick；
1318：CF cards；
1320：Embedded storage device；
100：Memory storage apparatus；
102：Connecting interface unit；
104：Memorizer control circuit unit；
106：Reproducible nonvolatile memorizer module；
2202：Memory cell array；
2204：Character line control circuit；
2206：Bit line control circuit；
2208：Row decoder；
2210：Data input/output buffer；
2212：Control circuit；
702：Storage unit；
704：Bit line；
706：Character line；
708：Common source line；
712、714：Transistor；
400 (0)~400 (N)：Entity program unit；
202：Memory management circuitry；
204：Host interface；
206：Memory interface；
208：Error checking circuit；
210：Buffer storage；
212：Electric power management circuit；
900：Parity-check matrix；
1010、1020：Distribution；
1001：Read voltage；
1030：Overlapping region；
1101：Code word；
1103：Reliability information vector；
1105：Verification vector；
1200：Weight matrix；
S1701、S1703、S1705、S1707、S1709、S1711、S1713：The step of coding/decoding method.
Specific implementation mode
In general, memory storage apparatus (also referred to as, storage system) includes duplicative non-volatile memories
Device module and controller (also referred to as, control circuit).Being commonly stored device storage device is used together with host system, so that host
System can write data into memory storage apparatus or be read from memory storage apparatus data.
Fig. 1 is that the example of the host system and memory storage apparatus shown by an exemplary embodiment according to the present invention shows
It is intended to.Fig. 2 is computer, input/output device and the memory storage apparatus shown by an exemplary embodiment according to the present invention
Example schematic.
Fig. 1 is please referred to, host system 1000 generally comprises computer 1100 and input/output (input/output；Abbreviation I/
O) device 1106.Computer 1100 includes microprocessor 1102, random access memory (random access memory；Referred to as
RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 include as Fig. 2 mouse 1202,
Keyboard 1204, display 1206 and printer 1208.It will be appreciated that the unrestricted input/output device of device shown in Fig. 2
1106, input/output device 1106 can further include other devices.
In an exemplary embodiment, memory storage apparatus 100 is by data transmission interface 1110 and host system
1000 other elements are electrically connected.Pass through microprocessor 1102, random access memory 1104 and input/output device 1106
Running can write data into memory storage apparatus 100 or read data from memory storage apparatus 100.For example, depositing
Reservoir storage device 100 can be USB flash disk 1212, storage card 1214 or solid state disk (Solid State as shown in Figure 2
Drive；Abbreviation SSD) 1216 equal type nonvolatile storage devices.
Fig. 3 is that the example of the host system and memory storage apparatus shown by an exemplary embodiment according to the present invention shows
It is intended to.
In general, host system 1000 is that can substantially coordinate with memory storage apparatus 100 to store appointing for data
Meaning system.Although in this exemplary embodiment, host system 1000 is explained with computer system, however, another example is real
It applies in example, host system 1000 can be that digital camera, video camera, communication device, audio player or video player etc. are
System.For example, when host system is digital camera (video camera) 1310, type nonvolatile storage device is then
Its used SD card 1312, mmc card 1314, memory stick (memory stick) 1316, CF cards 1318 or embedded storage dress
Set 1320 (as shown in Figure 3).Embedded storage device 1320 includes embedded multi-media card (Embedded MMC；Referred to as
eMMC).It is noted that embedded multi-media card is directly to be electrically connected on the substrate of host system.
Fig. 4 is the schematic block diagram for showing memory storage apparatus shown in FIG. 1.
Fig. 4 is please referred to, memory storage apparatus 100 includes connecting interface unit 102, memorizer control circuit unit 104
With reproducible nonvolatile memorizer module 106.
In this exemplary embodiment, connecting interface unit 102 is to be compatible to Serial Advanced Technology Attachment (Serial
Advanced Technology Attachment；Abbreviation SATA) standard.However, it is necessary to be appreciated that, the present invention is not limited to
This, connecting interface unit 102 can also be to meet parallel advanced technology annex (Parallel Advanced Technology
Attachment；Abbreviation PATA) standard, Institute of Electrical and Electric Engineers (Institute of Electrical and
Electronic Engineers；Abbreviation IEEE) 1394 standards, high-speed peripheral component connecting interface (Peripheral
Component Interconnect Express；Abbreviation PCI Express) standard, universal serial bus (Universal
Serial Bus；Abbreviation USB) standard, secure digital (Secure Digital；Abbreviation SD) interface standard, a ultrahigh speed generation
(Ultra High Speed-I；Abbreviation UHS-I) interface standard, two generation of ultrahigh speed (Ultra High Speed-II；Referred to as
UHS-II) interface standard, memory stick (Memory Stick；Abbreviation MS) interface standard, multimedia storage card (Multi Media
Card；Abbreviation MMC) interface standard, built-in multimedia storage card (Embedded Multimedia Card；Abbreviation eMMC) it connects
Mouth standard, general flash memory (Universal Flash Storage；Abbreviation UFS) interface standard, compact flash
(Compact Flash；Abbreviation CF) interface standard, IDE interface (Integrated Device
Electronics；Abbreviation IDE) standard or other suitable standards.Connecting interface unit 102 can be with memorizer control circuit list
Member 104 is encapsulated in a chip or connecting interface unit 102 is to be laid in one to include memorizer control circuit unit 104
Chip outside.
Memorizer control circuit unit 104 is executing in the form of hardware or multiple logic gates of form of firmware implementation or control
System instruction, and data are carried out in reproducible nonvolatile memorizer module 106 according to the instruction of host system 1000
The runnings such as be written, read and erase.
Reproducible nonvolatile memorizer module 106 is electrically connected to memorizer control circuit unit 104, and uses
The data being written with host system 1000.Reproducible nonvolatile memorizer module 106 can be that single-order storage is single
Member (Single Level Cell；Abbreviation SLC) NAND type flash memory module, multi-level cell memory (Multi Level
Cell；Abbreviation MLC) NAND type flash memory module be (that is, can store the flash of 2 bit datas in a storage unit
Device module), Complex Order storage unit (Triple Level Cell；Abbreviation TLC) NAND type flash memory module is (that is, one
The flash memory module of 3 bit datas can be stored in storage unit), other flash memory modules or other with identical spy
The memory module of property.
Fig. 5 is the summary of the reproducible nonvolatile memorizer module shown by an exemplary embodiment according to the present invention
Block diagram.Fig. 6 is the example schematic of the memory cell array shown by an exemplary embodiment according to the present invention.
Fig. 5 is please referred to, reproducible nonvolatile memorizer module 106 includes memory cell array 2202, character line traffic control
Circuit 2204 processed, bit line control circuit 2206, row decoder (column decoder) 2208, data input/output buffer
2210 with control circuit 2212.
In this exemplary embodiment, memory cell array 2202 may include storing multiple storage units 702 of data,
Multiple select grid drain electrode (select gate drain；Abbreviation SGD) transistor 712 and multiple select grid source electrode (select
gate source；Abbreviation SGS) transistor 714 and connect the multiple bit lines 704 of these storage units, a plurality of character line
706, with common source line 708 (as shown in Figure 6).Storage unit 702 is by array way (or in a manner of three-dimensional stacking) configuration
On the crosspoint of bit line 704 and character line 706.When receiving write instruction or reading from memorizer control circuit unit 104
When instruction, control circuit 2212 can control character line control circuit 2204, bit line control circuit 2206, row decoder 2208, number
Memory cell array 2202 is write data to according to input/output (i/o) buffer 2210 or reads number from memory cell array 2202
According to, wherein character line control circuit 2204 to control the voltage bestowed to character line 706, bit line control circuit 2206 is controlling
System is bestowed to the voltage of bit line 704, and row decoder 2208 is according to the row address in instruction to select corresponding bit line, and data
Input/output (i/o) buffer 2210 is configured to temporarily store data.
Each storage unit in reproducible nonvolatile memorizer module 106 is deposited with the change of critical voltage
Store up one or more positions.Specifically, the control grid (control gate) of each storage unit between channel there are one
Electric charge capture layer.By bestowing a write-in voltage to controlling grid, thus it is possible to vary the amount of electrons of electric charge capture layer, thus change
The critical voltage of storage unit.This program for changing critical voltage is also referred to as " write the data to storage unit " or " sequencing
Storage unit ".With the change of critical voltage, each storage unit of memory cell array 2202 has multiple storage shapes
State.And it may determine that storage unit is which storage state belonged to by reading voltage, thereby obtain storage unit and deposited
One or more positions of storage.
Fig. 7 is the management reproducible nonvolatile memorizer module shown by an exemplary embodiment according to the present invention
Example schematic.
Fig. 7 is please referred to, the storage unit 702 of reproducible nonvolatile memorizer module 106 can constitute multiple entity journeys
Sequence unit, and these entity program units can constitute multiple entity erased cells 400 (0)~400 (N).Specifically,
Storage unit on same character line can form one or more entity program units.If each storage unit can store 2
A above position, then the entity program unit on same character line can be classified as lower entity program unit and upper entity
Programmed cell.For example, the LSB of each storage unit is to belong to lower entity program unit, and the MSB of each storage unit
It is to belong to entity program unit.In general, in MLC NAND type flash memories, lower entity program unit is write
The reliability for entering writing speed or lower entity program unit that speed can be more than upper entity program unit is above entity
The reliability of programmed cell.In this exemplary embodiment, entity program unit is the minimum unit of sequencing.That is, entity
Programmed cell is the minimum unit that data are written.For example, entity program unit is physical page or entity fan
(sector).If entity program unit be physical page, each entity program unit generally include data bit area with
Redundant digit area.Data bit area is fanned comprising multiple entities, and to store the data of user, and redundant digit area is to storage system
Data (for example, error correcting code).In this exemplary embodiment, each data bit area includes that 32 entities are fanned, and an entity is fanned
Size be 512 hyte (byte；Abbreviation B).However, also may include in other exemplary embodiments, in data bit area 8,16
The more or fewer entity fans of a or number, the present invention are not intended to limit the size and number of entity fan.On the other hand, entity is smeared
Except unit is the least unit erased.That is, each entity erased cell contains the storage list of minimal amount being erased together
Member.For example, entity erased cell is physical blocks.
Fig. 8 is the schematic block diagram of the memorizer control circuit unit shown by an exemplary embodiment according to the present invention.
Fig. 8 is please referred to, memorizer control circuit unit 104 includes memory management circuitry 202, host interface 204, storage
Device interface 206 and error checking circuit 208.
Memory management circuitry 202 to control memory control circuit unit 104 overall operation.Specifically, it deposits
Reservoir, which manages circuit 202, has multiple control instructions, and when memory storage apparatus 100 operates, these control instruction meetings
It is performed the runnings such as to carry out the write-in of data, read and erase.When illustrating the operation of memory management circuitry 202 below, etc.
It is same as illustrating the operation of memorizer control circuit unit 104, below and repeat no more.
In this exemplary embodiment, the control instruction of memory management circuitry 202 is to carry out implementation with form of firmware.For example,
Memory management circuitry 202 has microprocessor unit (not shown) and read-only memory (not shown), and these controls refer to
Order is programmed in so far read-only memory.When memory storage apparatus 100 operates, these control instructions can be by microprocessor
Unit is executed the runnings such as to carry out the write-in of data, read and erase.
In another exemplary embodiment, the control instruction of memory management circuitry 202 can also procedure code form be stored in
The specific region of reproducible nonvolatile memorizer module 106 is (for example, be exclusively used in storage system data in memory module
System area) in.In addition, memory management circuitry 202 have microprocessor unit (not shown), read-only memory (not shown) and
Random access memory (not shown).In particular, this read-only memory has boot code (boot code), and work as memory
When control circuit unit 104 is enabled, microprocessor unit can first carry out this boot code, and will to be stored in duplicative non-volatile
Control instruction in property memory module 106 is loaded into the random access memory of memory management circuitry 202.Later, micro-
Processor unit such as can operate these control instructions to carry out the write-in of data, read and erase at the runnings.
In addition, in another exemplary embodiment, the control instruction of memory management circuitry 202 can also an example, in hardware
Implementation.For example, memory management circuitry 202 includes microcontroller, memory management unit, memory writing unit, memory
Reading unit, memory erased cell and data processing unit.Memory management unit, memory writing unit, memory are read
Unit, memory erased cell and data processing unit is taken to be electrically connected to microcontroller.Wherein, memory management unit is used
To manage the entity erased cell of reproducible nonvolatile memorizer module 106；Memory writing unit is pair can making carbon copies
Formula non-volatile memory module 106 assigns write instruction to write data into reproducible nonvolatile memorizer module
In 106；Memory reading unit to reproducible nonvolatile memorizer module 106 assigning reading instruction with from can make carbon copies
Data are read in formula non-volatile memory module 106；Memory erased cell is to type nonvolatile
Module 106 assigns instruction of erasing so that data to be erased from reproducible nonvolatile memorizer module 106；And data processing list
Member is intended to be written data to reproducible nonvolatile memorizer module 106 and is deposited from duplicative is non-volatile to handle
The data read in memory modules 106.
Host interface 204 is electrically connected to memory management circuitry 202 and to receive and identify host system
1000 instructions transmitted and data.That is, the instruction that host system 1000 is transmitted can pass through host interface with data
204 are sent to memory management circuitry 202.In this exemplary embodiment, host interface 204 is to be compatible to SATA standard.So
And, it should be understood that the invention is not limited thereto, host interface 204 can also be compatible to PATA standards, IEEE1394 standards,
PCI Express standards, USB standard, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards,
UFS standards, CF standards, IDE standards or other suitable data transmission standards.
Memory interface 206 is electrically connected to memory management circuitry 202 and non-volatile to access duplicative
Property memory module 106.That is, the data for being intended to be written to reproducible nonvolatile memorizer module 106 can be via depositing
Memory interface 206 is converted to the 106 receptible format of institute of reproducible nonvolatile memorizer module.
Error checking circuit 208 is electrically connected to memory management circuitry 202 and to execution error checking routine
To ensure the correctness of data.Specifically, when memory management circuitry 202 write instruction is received from host system 1000
When, error checking circuit 208 can be that the data of this corresponding write instruction generate corresponding error correcting code (error correcting
code；Abbreviation ECC) and/or error-detecging code (error detecting code；Abbreviation EDC), and memory management circuitry 202
The data of this corresponding write instruction can be written with corresponding error correcting code or error-detecging code to type nonvolatile mould
In block 106.Later, meeting when reading data from reproducible nonvolatile memorizer module 106 when memory management circuitry 202
The corresponding error correcting code of this data or error-detecging code are read simultaneously, and error checking circuit 208 can be according to this error correcting code or error-detecging code
To read data execution error checking routine.
In an exemplary embodiment, memorizer control circuit unit 104 further includes buffer storage 210 and power management electricity
Road 212.
Buffer storage 210 is electrically connected to memory management circuitry 202 and is configured to temporarily store come from host system
1000 data and the data for instructing or coming from reproducible nonvolatile memorizer module 106.
Electric power management circuit 212 is electrically connected to memory management circuitry 202 and stores to control memory fill
Set 100 power supply.
It is low density parity check code (low in this exemplary embodiment, used in error checking circuit 208
density parity code；Abbreviation LDPC).However, in another exemplary embodiment, used in error checking circuit 208
Can also be BCH code, convolution code (convolutional code), turbine code (turbo code), but not limited to this.
In this exemplary embodiment, error checking circuit 208 can check algorithm to encode according to a low-density parity
With decoding.It is to define effective code word with a parity-check matrix in low-density parity checks correcting code.It below will be strange
Even parity check matrix is labeled as matrix H, and a code word is labeled as CW.According to following equation (1), if parity-check matrix H with
The multiplication of code word CW is null vector, indicates that code word CW is effective code word.Wherein operatorIndicate the matrix phase of mould 2 (mod2)
Multiply.In other words, the kernel (null space) of matrix H just contains all effective code words.However, the present invention and unlimited
The content of code word CW processed.For example, code word CW can also include error correcting code or error-detecging code caused by arbitrary algorithm.
The dimension of wherein matrix H is that m- multiplies-n (m-by-n), and the dimension of code word CW is that 1- multiplies-n.M and n is positive integer.Code
Include information bit and parity bit in word CW, i.e. code word CW can be expressed as [M P], and wherein vector M is made of information bit,
Vectorial P is made of parity bit.The dimension of vector M is that 1- multiplies-(n-m), and the dimension of vector P is that 1- multiplies-m.It below will letter
Breath position is referred to as data bit with parity bit.In other words, there is n data bit, the wherein length of information bit is (n- in code word CW
M) position, and the length of parity bit is m, i.e., and the code check of code word CW (code rate) is (n-m)/n.
In general one can be used to generate matrix in coding (following label is) so that all for arbitrary vector M
Following equation sequence (2) can be met.It is that (n-m)-multiplies-n wherein to generate the dimension of matrix G.
The code word CW caused by equation (2) is effective code word.Therefore equation (2) can be substituted into equation (1),
Thereby obtain following equation sequence (3).
Since vector M can be arbitrary vector, following equation (4) inherently meets.That is, determining
After parity-check matrix H, corresponding generation matrix G can be also determined.
When decoding a code word CW, can an odd-even check program first be executed to the data bit in code word, such as will be strange
Even parity check matrix H is multiplied to produce a vector with code word CW (following label is, as shown in following equation (5)).If vectorial
S is null vector, then can directly output codons CW.If vector S is not null vector, then it represents that code word CW is not effective code word.
The dimension of vectorial S is that m- multiplies -1, and wherein each element is also referred to as syndrome (syndrome).If code word CW is not
Effective code word, then error checking circuit 208 can execute a decoding program, to attempt the error bit in corrigendum code word CW.
In one exemplary embodiment, the decoding program performed by error checking circuit 208 is an iteration (iteration) decoding program.
That is decoded program can be repeated constantly, a predetermined threshold is reached until successfully solving code word or executing number
Until.
Fig. 9 is the example schematic of the parity-check matrix shown by an exemplary embodiment according to the present invention.
Please refer to Fig. 9, the dimension of parity-check matrix 900 is that 4- multiplies -9, but the present invention is not intended to limit positive integer m and n and is
How much.Each row (row) of parity-check matrix 900 also represent a limitation (constraint).For example, parity-check matrix
900 first row to the 4th row respectively represents the first limitation to the 4th limitation.Each limitation in parity-check matrix 900 includes
Multiple elements.By taking first row (that is, first limitation) of parity-check matrix 900 as an example, if some code word is effective code word
(valid codeword) can be obtained then by the 1st in this code word, after 2,3 and the 4th positions do the addition of mould 2 (modulo-2)
Position " 0 ".In this field, usually intellectual will be understood that how to be encoded with parity-check matrix 900, just repeat no more herein.
In addition, parity-check matrix 900 is only an example matrix, rather than to limit the present invention.
It is poor when multiple are written to reproducible nonvolatile memorizer module 106 memory management circuitry 202
Wrong checking circuit 208 can be to all generating corresponding m parity bit per (n-m) a position to be written into (that is, information bit).It connects down
Come, memory management circuitry 202 can be written using this n position as a code word to reproducible nonvolatile memorizer module
106。
Figure 10 is the critical voltage point of the SLC type flash memory modules shown by an exemplary embodiment according to the present invention
The example schematic of cloth.
Please refer to Figure 10, the critical voltage of horizontal axis representative memory cell, and longitudinal axis representative memory cell number.For example, figure
10 be the critical voltage for indicating each storage unit in an entity program unit.It is assumed herein that when some storage unit
Critical voltage is fallen when being distributed 1010, and what this storage unit was stored is position " 1 "；If on the contrary, some storage unit
Critical voltage is fallen when being distributed 1020, and what this storage unit was stored is position " 0 ".It is noted that this exemplary embodiment
It is possible by taking SLC type flash memory modules as an example, therefore there are two types of the distributions of critical voltage.However, implementing in other examples
In example, the distribution of critical voltage may be four kinds, eight kinds or any other a possible, and reading voltage can be distributed in any two
Between.In addition, the present invention does not limit the representative position of each distribution yet.
When to read data from reproducible nonvolatile memorizer module 106, memory management circuitry 202 can be sent
One reads instruction sequence to reproducible nonvolatile memorizer module 106.It includes one or more instructions that this, which reads instruction sequence,
Or procedure code, and to indicate to read multiple storage units in an entity program unit to obtain multiple positions.For example,
Multiple storage units in an entity program unit are read according to voltage 1001 is read.If some storage unit is faced
Boundary's voltage is less than this reading voltage, then this storage unit can be connected, and memory management circuitry 202 can read position " 1 ".On the contrary
Ground, if the critical voltage of some storage unit is more than this reading voltage, this storage unit does not turn on, and memory pipe
Reason circuit 202 can read position " 0 ".
It is worth noting that, distribution 1010 includes an overlapping region 1030 with distribution 1020.Overlapping region 1030 indicates
What is stored in some storage units should be position " 1 " (belonging to distribution 1010), but its critical voltage is more than reading voltage
1001；Alternatively, it should be position " 0 " (belonging to distribution 1020) to have stored in some storage units, but its critical voltage is less than
Read voltage 1001.In other words, in read position, there is the position of part can be wrong.In another exemplary embodiment, also may be used
To read out multiple positions from a storage unit, the present invention does not limit.In addition, primary reading can also be reading one
Multiple storage units or any number of storage unit, the present invention in a entity fan do not limit.
In this exemplary embodiment, when memory management circuitry 202 is from reproducible nonvolatile memorizer module 106
When reading n position (forming a code word), memory management circuitry 202 can also obtain the reliability letter corresponding to each
Breath.Here, reliability information is to indicate that corresponding position is decoded as the probability (or confidence) of position " 1 " or " 0 ".It is special
It is not that when using different algorithms, the value of the reliability information corresponding to each obtained can differ.For example,
Summation-product algorithm (Sum-Product Algorithm), minimum value-summation calculation may be used in error checking circuit 208
Method (Min-Sum Algorithm) or bit flipping algorithm (bit-flipping Algorithm), the present invention is not intended to limit
Using which kind of algorithm.
Error checking circuit 208 can judge whether these positions have at least one mistake.For example, in this exemplary embodiment
In, error checking circuit 208 can execute these positions odd-even check program to obtain multiple syndromes (syndrome), wherein often
One position is corresponded to at least one of these syndromes.In other words, these syndromes can form above-mentioned vector S.
In an exemplary embodiment, above-mentioned vector S also referred to as verifies vector.Error checking circuit 208 can be according to more in verification vector S
A syndrome judges whether these positions have at least one mistake.For example, if each syndrome in verification vector S is
" 0 ", error checking circuit 208 can judge that these positions do not have any mistake, and judge by the code word that these are formed to be to have
Imitate code word；If one or more syndromes in verification vector S are " 1 ", error checking circuit 208 can judge that these positions have extremely
A few mistake, and judge that the code word being made of these is not effective code word.
Figure 11 is the example schematic of the matrix multiple shown by an exemplary embodiment according to the present invention.
Figure 11 is please referred to, it is that parity-check matrix 900 is multiplied with code word 1101 the result is that verification vector 1105.Code word 1101
In each position be to correspond at least one of 1105 syndromes of verification vector.For example, the position V in code word 11011
(corresponding to the first row (column) in parity-check matrix 900) is to correspond to syndrome S1And S2；Position V2It is (corresponding to odd even
The second row in test matrix 900) it is to correspond to syndrome S1And S3, and so on.If position V1Mistake has occurred, then syndrome
S1And S2May be " 1 "；If position V2Mistake has occurred, then syndrome S1And S3May be " 1 ", and so on.In addition, odd even
The first limitation in test matrix 900 is corresponding to syndrome S1, the second limitation in parity-check matrix 900 is corresponding to school
Test sub- S2, the third limitation in parity-check matrix 900 is corresponding to syndrome S3, and the in parity-check matrix 900 the 4th
Limitation is corresponding to syndrome S4。
If the position V in code word 11011~V9There is no mistake, then the position V in the meeting of error checking circuit 208 output codons 11011
~V9.If position V1~V9With at least one mistake, error checking circuit 208 can align V1~V9Execute an iterative decoding procedures with
Obtain multiple solution code bits.In particular, before executing an iterative decoding procedures, error checking circuit 208 can be corresponded to
One weight of each and each syndrome.These weights can be indicated using a weight matrix.These weights
It can also be recorded in a look-up table.Error checking circuit 208 can execute iterative decoding procedures according to these weights.Or
Person obtains the operation corresponding to each and the weight of each syndrome, can also be considered as in an exemplary embodiment
A part for iterative decoding procedures, the present invention do not limit.
Figure 12 is the example schematic of the weight matrix shown by an exemplary embodiment according to the present invention.
Figure 12 is please referred to, weight W has been recorded in weight matrix 12001,1~W4,9.Wherein, weight W1,1Correspond to a V1
With syndrome S1；Weight W1,2Correspond to a V2With syndrome S1；Weight W2,1Correspond to a V1With syndrome S2, with such
It pushes away.The matrix size of weight matrix 1200 is consistent with parity-check matrix 900.For example, weight matrix 1200 also have m row and
N row.
Error checking circuit 208 can calculate the multiple reliabilitys letter for meeting an examination condition in obtained reliability information
The summation of breath, and this summation is added into a corresponding balancing information to obtain a weight in weight matrix 1200.Below
It will be to calculate weight W1,1It is illustrated as example.
Figure 13 be code word shown by an exemplary embodiment according to the present invention, reliability information, parity-check matrix with
The example schematic of correspondence between syndrome.
Figure 13 is please referred to, it is assumed herein that corresponding to each V in code word 11011~V9Reliability information be respectively can
By degree information vector 1103 in " 0.6 ", " 0.8 ", " -0.2 ", " 1.3 ", " -1.5 ", " 0.3 ", " -1.2 ", " 0.4 " with
“0.1”.However, be only an example array in this reliability information vector 1103, rather than to limit the present invention.In this example
In embodiment, each reliability information in reliability information vector 1103 can be taken absolute value.Therefore, reliability information vector
Reliability information in 1103 becomes " 0.6 ", " 0.8 ", " 0.2 ", " 1.3 ", " 1.5 ", " 0.3 ", " 1.2 ", " 0.4 " and " 0.1 ".
If the absolute value corresponding to the reliability information of some is bigger, then it represents that the probability that mistake occurs in this is lower；If corresponding
It is smaller in the absolute value of the reliability information of some, then it represents that the probability that mistake occurs in this is higher.However, in another model
In example embodiment, arbitrary logical operation, this hair can also be made to each reliability information in reliability information vector 1103
It is bright not limit.In addition, each reliability information in reliability information vector 1103 corresponds respectively to parity-check matrix
An element in 900 each limitation.For example, as shown in figure 13, " 0.6 " in reliability information vector 1103 corresponds to
First element to come from left side number in first limitation to the 4th limitation, and " 0.8 " in reliability information vector 1103
Second element to come from left side number in the first limitation to the 4th limitation is corresponded to, and so on.Due to weight matrix
Weight W in 12001,1Correspond to the position V in code word 11011With the syndrome S in verification vector 11051, therefore below
In exemplary embodiment, the position V in code word 11011Also referred to as first, and verify the syndrome S in vector 11051Also referred to as
One syndrome, in order to illustrate how to calculate weight W1,1。
Calculating weight W1,1When, error checking circuit 208 can be according to the first limitation in parity-check matrix 900, from can
The multiple reliability informations for meeting examination condition are determined in degree information vector 1103.For example, error checking circuit 208 can basis
In the included element of first limitation, value is multiple elements of " 1 ", determines that meeting this looks into from reliability information vector 1103
Test multiple reliability informations of condition.For example, in this exemplary embodiment, the first four to come from left side number in the first limitation is first
Element element value be " 1 ", therefore meet in reliability information vector 1103 examination condition reliability information be " 0.6 ",
" 0.8 ", " 0.2 " and " 1.3 ".Later, error checking circuit 208 can obtain the summation for the reliability information for meeting this examination condition
For " 2.9 ".
In this exemplary embodiment, each limitation is corresponding to a balancing information.The meeting of error checking circuit 208 will be upper
It states summation and adds the balancing information for corresponding to the first limitation to obtain weight W1,1.More specifically, 208 meeting of error checking circuit
Above-mentioned summation is added and corresponds to the balancing information of the first limitation to obtain the first assessment information, and the first assessment information is removed
With one second assessment information to obtain weight W1,1。
Error checking circuit 208 can from the above-mentioned reliability information for meeting examination condition selection correspond to another one (
Referred to as second) reliability information.Wherein, this second is different from first.That is, in this exemplary embodiment, this
Two are a V2~V4One of.In particular, in this exemplary embodiment, selected corresponds to deputy reliability
The value of information be all reliability informations for meeting examination condition value in it is minimum, or corresponding to deputy reliability believe
The value of breath is that the value of the reliability information corresponding to first is merely greater than in all reliability informations for meeting examination condition.Example
Such as, in this exemplary embodiment, first (that is, position V1) corresponding to reliability information value be " 0.6 ", therefore, mistake school
Electrical verification road 208 can select its value to be used as corresponding to deputy for the reliability information of " 0.2 " from " 0.8 ", " 0.2 ", " 1.3 "
Reliability information.That is, in this exemplary embodiment, second is position V3, and believe corresponding to deputy reliability
Breath is " 0.2 ".However, in the implementation of another example, second can also be selected according to arbitrary condition, and the present invention is not
It limits.For example, in an exemplary embodiment, the reliability information for meeting examination condition can also be inputted a look-up table or
One algorithm, and using the output of this look-up table or this algorithm as corresponding to deputy reliability information.
In this exemplary embodiment, each limitation is corresponding to a Dynamic gene αm.For example, α1It corresponds to the first limit
System, α2It corresponds to the second limitation, α3It corresponds to third and limits, and α4It corresponds to the 4th limitation.It is obtaining corresponding to deputy
After reliability information, error checking circuit 208 can will be multiplied by Dynamic gene α corresponding to deputy reliability information1To obtain
Obtain the balancing information for corresponding to the first limitation.Thereby, the summation and balance that may make the reliability information for meeting examination condition are believed
The value of breath is suitable, avoids making it be ignored because the value of balancing information is too small.It is noted that in this exemplary embodiment,
Dynamic gene αmThe integer or real number for being more than " 1 " for one.However, in another exemplary embodiment, Dynamic gene αmCan also be to appoint
The real number of meaning, the present invention do not limit.In addition, in another exemplary embodiment, Dynamic gene αmMay be " 1 ".At this
In exemplary embodiment, it is assumed that Dynamic gene α1For " 11.36 ", then error checking circuit 208 can get the first assessment information and be
“5.172”.In addition, error checking circuit 208 can will correspond to first (that is, position V1) reliability information as second assessment
Information.That is, in this exemplary embodiment, the second assessment information is " 0.6 ".Thereby, by by the first assessment information divided by the
Two assessment information, error checking circuit 208 can obtain weight W1,1For " 8.62 ".Alternatively, in an exemplary embodiment, mistake
Checking circuit 208 can pass through the weight W in weight matrix 1200 of the following equation (6) to obtain Figure 121,1~W4,9。
Wherein,According to correspond to m limitation the reliability information for meeting examination condition summation,Information is assessed for first, | yn| information is assessed for second,To correspond to deputy reliability
Information, andFor the balancing information limited corresponding to m.
In an exemplary embodiment, the value corresponding to the balancing information of m limitations is to be positively correlated with the row power of m limitations
Weight.For example, the value corresponding to the balancing information of the first limitation is to be positively correlated with the row weight of the first limitation；Corresponding to the second limitation
The value of balancing information be to be positively correlated with the row weight of the second limitation, and so on.For example, 208 meeting of error checking circuit
The row weight of the first limitation is determined according to the first limitation intermediate value is the number of the element of " 1 ".For example, the example in Figure 13 is implemented
There are four the value of element it is " 1 " in the first limitation, therefore error checking circuit 208 can determine the row weight of the first limitation in example
For " 4 ".And so on, the second row weight limited is " 6 ", and the row weight of third limitation is " 6 ", and the row of the 4th limitation are weighed
Weight is " 4 ".In addition, in another exemplary embodiment, the value corresponding to the balancing information of m limitations can also be negative about or
The uncorrelated row weight in m limitations, the present invention do not limit.
In an exemplary embodiment, the m row weights limited can be multiplied by an amplification factor to obtain by error checking circuit 208
Obtain the Dynamic gene α for corresponding to m limitationsm.It is put for example, the row weight of the first limitation can be multiplied by one by error checking circuit 208
Big multiple obtains Dynamic gene α1.For example, error checking circuit 208 can calculate it is all in reliability information vector 1103
An average value (also referred to as the first average value) for reliability information, and according to each limitation in parity-check matrix 900, from
The minimum value and sub-minimum of reliability information are obtained in the corresponding reliability information for meeting examination condition.For example, error checking and correction
Minimum value and the sub-minimum that circuit 208 can obtain corresponding to the reliability information of the first limitation are respectively " 0.2 " and " 0.6 ", right
Should be respectively " 0.2 " and " 0.3 " in minimum value and the sub-minimum of the reliability information of the second limitation, correspond to that third limits can
Minimum value and sub-minimum by spending information are respectively " 0.1 " and " 0.3 ", and the reliability information limited corresponding to the 4th is most
Small value and sub-minimum are respectively " 0.1 " and " 0.2 ".Later, error checking circuit 208 can calculate these minimum values and these time small
An average value (also referred to as the second average value) after value totalling, and by the first average value divided by the second average value to obtain this
Amplification factor.In this exemplary embodiment, the amplification factor that the row weight of each m limitations is multiplied by is identical.So
And in another exemplary embodiment, the amplification factor that the row weight of each m limitations is multiplied by can also be different.This
Outside, in another exemplary embodiment, minimum value and the sub-minimum of reliability information can also be to be selected with arbitrary rule, this
Invention does not limit.Alternatively, in an exemplary embodiment, error checking circuit 208 can also by following equation sequence (7) come
Obtain Dynamic gene αm。
Wherein, row_weight (m) is the row weight that m is limited in parity-check matrix 900, and mean (| y |) is upper
State the first average value and mean (| ymin|) it is above-mentioned second average value.For example, in this exemplary embodiment, the first average value
It is " 0.71 " (that is, (0.6+0.8+0.2+1.3+1.5+0.3+1.2+0.4+0.1)/9=0.71), the second average value is " 0.25 "
(that is, (0.2+0.2+0.1+0.1+0.6+0.3+0.3+0.2)/9=0.25).Therefore, 1~α of Dynamic gene α 4 are can get to distinguish
It is " 11.36 ", " 17.04 ", " 11.36 " and " 17.04 ".
According to aforesaid operations, error checking circuit 208 can obtain the weight W1 in the weight matrix 1200 of Figure 12 respectively, and 1
~W4,9.For example, in this exemplary embodiment, in calculating weight W2,1, first is a V1, and second is a V3.
Error checking circuit 208 can determine the multiple reliabilitys for meeting examination condition according to the second limitation in parity-check matrix 900
Information is " 0.6 ", " 0.2 ", " 1.3 ", " 1.5 ", " 0.3 " and " 1.2 " and its summation is " 5.1 ".Then, it is assumed that Dynamic gene
α 2 is " 17.04 ", and it is " 8.508 " (that is, 5.1+ (17.04 × 0.2)) that error checking circuit 208, which can obtain the first assessment information,
Second assessment information is " 0.6 " (that is, correspond to primary reliability information), and weight W2,1 for " 14.18 " (that is,
8.508/0.6=14.18).The calculating of remaining weight can the rest may be inferred in weight matrix 1200, and not in this to go forth.
Figure 14 is the example schematic of the calculated weight shown by an exemplary embodiment according to the present invention.
Figure 14 is please referred to, in the first limitation of weight matrix 1200, corresponds to the weight W1 of position V1 and syndrome S1,1
For " 8.62 ", correspond to the weight W1 of position V2 and syndrome S1,2 be " 6.47 ", corresponds to the weight W1 of position V3 and syndrome S1,
3 be " 48.58 ", and corresponding to the weight W1 of position V4 and syndrome S1,4 be " 3.45 ".In the second limit of weight matrix 1200
In system, correspond to the weight W2 of position V1 and syndrome S2,1 is " 14.18 ", corresponds to the weight W2 of position V3 and syndrome, 3 are
" 51.06 " correspond to the weight W2 of position V4 and syndrome S2, and 4 be " 6.54 ", correspond to the weight W2 of position V5 and syndrome S2, and 5
For " 5.67 ", correspond to the weight W2 of position V6 and syndrome S2,6 be " 28.36 ", and corresponds to position V7 and the second syndrome S2
Weight W2,7 be " 7.09 ", and so on.It is noted that in this exemplary embodiment, error checking circuit 208 can be right
It is the element of " 0 " to answer its value in parity-check matrix 900, and the weight of part in weight matrix 1200 is set as " 0 ".
Figure 15 is the example schematic of the matrix multiple shown by an exemplary embodiment according to the present invention.
Please refer to Figure 15, in iterative decoding procedures, error checking circuit 208 can according to above-mentioned syndrome with it is calculated
Weight obtains the verification weight information of a V1~V9.For example, each syndrome can be multiplied by by error checking circuit 208
One weight, and the result of total check and multiplied by weight is to obtain verification weight information.For example, the verification weight of position V1
Information can be equal to W1,1S1+W2,1S2, and wherein weight W1,1 and W2,1 is " 8.62 " and " 14.18 " in above-mentioned Figure 14.
In this exemplary embodiment, error checking circuit 208 can be " 1 " or " 0 " according to a syndrome to determine to correspond to this verification
The value of the weight of son is greater than 0 or less than 0.If for example, a syndrome is " 1 ", corresponding to the weight of this syndrome can multiply
Upper " 1 "；If a syndrome is " 0 ", corresponding to the weight of this syndrome can be multiplied by " -1 ".It is worth noting that, right at this
The addition that syndrome S1~S4 is done is general addition, rather than the addition of mould 2 (modulo-2).In other words, mistake school
Electrical verification road 208 can obtain the verification weight information corresponding to position V1~V9 by following equation sequence (8).
Wherein, vectorial EnIt can be used to indicate each V1~V9Verification weight information.
Error checking circuit 208 can be according to position V1~V9Verification weight information come overturn (flip) these at least its
One of.For example, some or multiple positions can be turned into " 0 " from " 1 " or be turned into from " 0 " by error checking circuit 208
“1”.In an exemplary embodiment, the operation of above-mentioned flip bit is also referred to as bit flipping (bit flipping).Specifically, every
In primary iterative decoding procedures, at most it can be only reversed there are one position in a code word.For example, the verification of this position being reversed
The value of weight information can be more than the value of the verification weight information of other positions not being reversed.In addition, in another exemplary embodiment
In, error checking circuit 208 can judge whether the verification weight information of each in code word 1101 meets a weight condition.
For example, error checking circuit 208 can judge whether the value of the verification weight information of each is more than a threshold value.If some
When the value of the verification weight information of position is more than this threshold value, then error checking circuit 208 can judge this verification weight information symbol
Weight condition is closed, and overturns this position.In other words, in an exemplary embodiment, the verification weight information for the position being reversed is i.e.
To meet the verification weight information of weight condition.
Figure 16 is the example schematic of the verification weight information shown by an exemplary embodiment according to the present invention.
Please refer to Figure 16, it is assumed that the position V in code word 11011~V9Be respectively " 1 ", " 1 ", " 0 ", " 1 ", " 0 ", " 1 ", " 0 ",
" 0 " and " 1 ", the syndrome S in verification vectorial 11051~S4" 1 ", " 0 ", " 1 " and " 0 " respectively, then it is poor according to equation (8)
Wrong checking circuit 208 can obtain vectorial En, the vector EnTo indicate a V1~V9Verification weight information be respectively "-
5.56 ", " 13.98 ", " -13.16 ", " -3.09 ", " -1.67 ", " -15.47 ", " -0.29 ", " 9.67 " and " 61.4 ".In this model
In example embodiment, error checking circuit 208 can select maximum one of its value in these verification weight informations after taking absolute value
Verify weight information (that is, " 15.47 "), and the position V that this verification weight information will be corresponded to6Overturning.Then, this iterative decoding journey
Sequence can export another code word for having multiple.For example, these positions can be respectively " 1 ", " 1 ", " 0 ", " 1 ", " 0 ", " 0 ", " 0 ",
" 0 " and " 1 ".Then, error checking circuit 208 can judge whether these positions have mistake again.If without mistake, error checking and correction
Circuit 208 can export these positions.If wrong, error checking circuit 208 can determine it is the iterative decoding journey that execute another time
Sequence stops decoding.
In this exemplary embodiment, if there are mistake, error checking and correction electricity in 208 decision codeword 1101 of error checking circuit
208 counting of road, one iterations for example, iterations are added 1, and judge whether the iterations after counting reach in one
Only number.Here, it is, for example, 30 times or more or less to stop number.If the iterations after counting reach suspension number,
Then error checking circuit 208 can judge decoding failure, and stop decoding.If the iterations after counting do not reach suspension time
It counts, then error checking circuit 208 can execute another iterative decoding procedures.
Figure 17 is the flow chart of the coding/decoding method shown by an exemplary embodiment according to the present invention.
Figure 17 is please referred to, first, in step S1701, one is sent and reads instruction sequence, wherein the reading instruction sequence
To read multiple storage units to obtain multiple positions.In step S1703, obtains and correspond to the reliability information of each.
Then, in step S1705, the summation for the multiple reliability informations for meeting examination condition in the reliability information is calculated.
In step S1707, by the summation plus a balancing information to obtain first and the first syndrome corresponding in institute's rheme
Weight.Later, in step S1709, judge whether institute's rheme has an at least mistake.If institute's rheme has described at least one
Mistake executes iterative decoding procedures in step S1711 according to the weight.If institute's rheme does not have the mistake, in step
In S1713, institute's rheme is exported.
However, each step has been described in detail as above in Figure 17, just repeat no more herein.It is worth noting that, each in Figure 17
Step can be implemented as multiple procedure codes or circuit, and the present invention is simultaneously not subject to the limits.In addition, more than the method for Figure 17 can arrange in pairs or groups
Embodiment uses, and can also be used alone, the present invention is simultaneously not subject to the limits.
In conclusion when the position read from reproducible nonvolatile memorizer module has mistake, model of the present invention
Coding/decoding method, the memorizer control circuit unit of example embodiment can be given from memory storage apparatus corresponding to different positions in code word
With the weight weighted value appropriate of different check.Thereby, the decoding effect being decoded according to verification weight information can be increased
Rate.
Finally it should be noted that：The above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Present invention has been described in detail with reference to the aforementioned embodiments for pipe, it will be understood by those of ordinary skill in the art that：Its according to
So can with technical scheme described in the above embodiments is modified, either to which part or all technical features into
Row equivalent replacement；And these modifications or replacements, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (24)
1. a kind of coding/decoding method is used for reproducible nonvolatile memorizer module, which is characterized in that the duplicative is non-volatile
Property memory module includes multiple storage units, which includes：
It sends and reads instruction sequence, the wherein reading instruction sequence is to read the multiple storage unit, to obtain multiple positions；
Multiple reliability informations are obtained, wherein the multiple reliability information corresponds respectively to one of the multiple position；
Calculate the summation for the multiple reliability informations for meeting examination condition in the multiple reliability information；
By the summation plus balancing information to obtain the weight for corresponding to first in the multiple position with the first syndrome；
Judge whether the multiple position has an at least mistake；And
If the multiple position has an at least mistake, iterative decoding procedures are executed according to the weight, to correct at least one mistake
Accidentally.
2. coding/decoding method according to claim 1, which is characterized in that judge whether the multiple position has at least one mistake
Accidentally the step of include：
Odd-even check program is executed to obtain the multiple syndromes for including first syndrome, wherein each institute to the multiple position
Stating multiple positions is corresponded to at least one of the multiple syndrome；And
Judge whether the multiple position has an at least mistake according to the multiple syndrome,
Wherein the odd-even check program is according to performed by parity-check matrix, and the parity-check matrix includes multiple limits
System,
Wherein calculate the summation of the multiple reliability information for meeting the examination condition in the multiple reliability information
Step includes：
According to the first limitation for corresponding to first syndrome in the multiple limitation, determined from the multiple reliability information
Meet the multiple reliability information of the examination condition.
3. coding/decoding method according to claim 2, which is characterized in that first limitation includes multiple elements, and according to this
First limitation determines to wrap the step of meeting the multiple reliability information of the examination condition from the multiple reliability information
It includes：
It is multiple elements of " 1 " according to the multiple element intermediate value, determines to meet the examination from the multiple reliability information
The multiple reliability information of condition.
4. coding/decoding method according to claim 1, which is characterized in that by the summation plus the balancing information to obtain correspondence
Include in this first and the step of weight of first syndrome：
By the summation plus the balancing information to obtain the first assessment information；And
By the first assessment information divided by the second assessment information to obtain the power for corresponding to this first with first syndrome
Weight, wherein the second assessment information is to correspond to the primary reliability information in the multiple reliability information.
5. coding/decoding method according to claim 1, which is characterized in that further include：
From in the multiple reliability information for meet the examination condition selection correspond to the multiple position in it is deputy can
By spending information, the wherein second is different from this first；And
Dynamic gene will be multiplied by obtain the balancing information corresponding to the deputy reliability information.
6. coding/decoding method according to claim 5, which is characterized in that correspond to the value of the deputy reliability information
Be the multiple reliability information for meeting the examination condition value in it is minimum.
7. coding/decoding method according to claim 5, which is characterized in that correspond to the value of the deputy reliability information
It is the value that the reliability information corresponding to this first is merely greater than in the multiple reliability information for meeting the examination condition.
8. coding/decoding method according to claim 1, which is characterized in that the value of the balancing information is to be positively correlated with first school
Test the row weight of son the first limitation corresponding in parity-check matrix.
9. a kind of memorizer control circuit unit is used for reproducible nonvolatile memorizer module, which is characterized in that this can be answered
The formula non-volatile memory module of writing includes multiple storage units, which includes：
Host interface is electrically connected to host system；
Memory interface is electrically connected to the reproducible nonvolatile memorizer module；
Memory management circuitry is electrically connected to the host interface and the memory interface, and to send reading sequence of instructions
Row, the wherein reading instruction sequence is to read the multiple storage unit, to obtain multiple positions；And
Error checking circuit is electrically connected to the memory management circuitry, to obtain multiple reliability informations, wherein described more
A reliability information corresponds respectively to one of the multiple position；
The error checking circuit is also calculating the multiple reliability informations for meeting examination condition in the multiple reliability information
Summation,
The error checking circuit also to by the summation plus balancing information with obtain correspond to the multiple position in first
With the weight of the first syndrome,
The error checking circuit also to judge the multiple position whether have an at least mistake,
If the multiple position has an at least mistake, the error checking circuit is also to according to weight execution iterative decoding journey
Sequence, to correct an at least mistake.
10. memorizer control circuit unit according to claim 9, which is characterized in that the error checking circuit judges institute
Stating multiple positions, whether the operation at least one mistake includes：
The error checking circuit executes odd-even check program to obtain the multiple schools for including first syndrome to the multiple position
Son is tested, wherein each the multiple position is corresponded to at least one of the multiple syndrome；And
The error checking circuit judges whether the multiple position has an at least mistake according to the multiple syndrome,
Wherein the odd-even check program is according to performed by parity-check matrix, and the parity-check matrix includes multiple limits
System,
Wherein the error checking circuit calculates the multiple reliability for meeting the examination condition in the multiple reliability information
The operation of the summation of information includes：
The error checking circuit according in the multiple limitation correspond to first syndrome first limitation, from it is the multiple can
The multiple reliability information for meeting the examination condition is determined in degree information.
11. memorizer control circuit unit according to claim 10, which is characterized in that first limitation includes multiple members
Element, and the institute that the error checking circuit determines to meet the examination condition from the multiple reliability information according to first limitation
The operation for stating multiple reliability informations includes：
The error checking circuit is according to multiple elements that the multiple element intermediate value is " 1 ", from the multiple reliability information
Determine the multiple reliability information for meeting the examination condition.
12. memorizer control circuit unit according to claim 9, which is characterized in that the error checking circuit is total by this
Correspond to the operation of this first and the weight of first syndrome to obtain with plus the balancing information and include：
The error checking circuit is by the summation plus the balancing information to obtain the first assessment information；And
The error checking circuit by the first assessment information divided by the second assessment information with obtain correspond to this first with this
The weight of one syndrome, wherein the second assessment information are primary reliable corresponding to this in the multiple reliability information
Spend information.
13. memorizer control circuit unit according to claim 9, which is characterized in that the error checking circuit also to
Correspond to the deputy reliability in the multiple position from selection in the multiple reliability information for meet the examination condition
Information, the wherein second are different from this first,
The error checking circuit is also multiplied by Dynamic gene will correspond to the deputy reliability information and is put down with obtaining this
Weigh information.
14. memorizer control circuit unit according to claim 13, which is characterized in that correspond to this it is deputy this can
By spend information value be the multiple reliability information for meeting the examination condition value in it is minimum.
15. memorizer control circuit unit according to claim 13, which is characterized in that correspond to this it is deputy this can
Value by spending information is merely greater than reliable corresponding to this first in the multiple reliability information for meeting the examination condition
Spend the value of information.
16. memorizer control circuit unit according to claim 9, which is characterized in that the value of the balancing information is positive
The row weight of first limitation corresponding in parity-check matrix about first syndrome.
17. a kind of memory storage apparatus, which is characterized in that including：
Connecting interface unit, is electrically connected to host system；
Reproducible nonvolatile memorizer module, including multiple storage units；And
Memorizer control circuit unit is electrically connected to the connecting interface unit and the type nonvolatile mould
Block,
The wherein memorizer control circuit unit is to send reading instruction sequence, and wherein the reading instruction sequence is to read
Multiple storage units are stated, to obtain multiple positions,
The memorizer control circuit unit is also to obtain multiple reliability informations, wherein the multiple reliability information is right respectively
Should in one of the multiple position,
The memorizer control circuit unit also meets the multiple reliable of examination condition to calculate in the multiple reliability information
The summation of information is spent,
The memorizer control circuit unit is also corresponded to obtaining in the multiple position the summation is added balancing information
First with a weight of the first syndrome,
The memorizer control circuit unit also to judge the multiple position whether have an at least mistake,
If there is an at least mistake, the memorizer control circuit unit also to change to execute one according to the weight for the multiple position
For decoding program, to correct an at least mistake.
18. memory storage apparatus according to claim 17, which is characterized in that the memorizer control circuit unit judges
Whether the operation at least one mistake includes for the multiple position：
It includes first syndrome that the memorizer control circuit unit executes odd-even check program to obtain to the multiple position
Multiple syndromes, wherein each the multiple position is corresponded to at least one of the multiple syndrome；And
The memorizer control circuit unit judges whether the multiple position has an at least mistake according to the multiple syndrome,
Wherein the odd-even check program is according to performed by parity-check matrix, and the parity-check matrix includes multiple limits
System,
Wherein the memorizer control circuit unit, which calculates, meets the multiple of the examination condition in the multiple reliability information
The operation of the summation of reliability information includes：
The memorizer control circuit unit is according to the first limitation for corresponding to first syndrome in the multiple limitation, from described
The multiple reliability information for meeting the examination condition is determined in multiple reliability informations.
19. memory storage apparatus according to claim 18, which is characterized in that first limitation includes multiple elements,
And the memorizer control circuit unit determines to meet the examination condition from the multiple reliability information according to first limitation
The operation of the multiple reliability information include：
The memorizer control circuit unit is according to multiple elements that the multiple element intermediate value is " 1 ", from the multiple reliability
The multiple reliability information for meeting the examination condition is determined in information.
20. memory storage apparatus according to claim 17, which is characterized in that the memorizer control circuit unit should
Summation corresponds to the operation of this first and the weight of first syndrome and includes plus the balancing information to obtain：
The memorizer control circuit unit is by the summation plus the balancing information to obtain the first assessment information；And
The first assessment information divided by the second assessment information are corresponded to this first by the memorizer control circuit unit to obtain
With the weight of first syndrome, wherein the second assessment information is to correspond to this first in the multiple reliability information
Reliability information.
21. memory storage apparatus according to claim 17, which is characterized in that the memorizer control circuit unit is also used
It is deputy reliable in the multiple position to correspond to from selection in the multiple reliability information for meet the examination condition
Information is spent, the wherein second is different from this first,
The memorizer control circuit unit is also multiplied by Dynamic gene to obtain will correspond to the deputy reliability information
Obtain the balancing information.
22. memory storage apparatus according to claim 21, which is characterized in that correspond to the deputy reliability
The value of information be the multiple reliability information for meeting the examination condition value in it is minimum.
23. memory storage apparatus according to claim 21, which is characterized in that correspond to the deputy reliability
The value of information is merely greater than the reliability letter corresponding to this first in the multiple reliability information for meeting the examination condition
The value of breath.
24. memory storage apparatus according to claim 17, which is characterized in that the value of the balancing information is to be positively correlated with
The row weight of first syndrome the first limitation corresponding in parity-check matrix.
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| TWI631830B (en) * | 2016-12-30 | 2018-08-01 | 慧榮科技股份有限公司 | Decoding method and related apparatus |
| DE102017116280B4 (en) * | 2017-07-19 | 2024-02-22 | Infineon Technologies Ag | STORAGE ARRANGEMENT |
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| CN101512661A (en) * | 2006-05-12 | 2009-08-19 | 爱诺彼得技术有限责任公司 | Combined distortion estimation and error correction coding for memory devices |
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| CN101512661A (en) * | 2006-05-12 | 2009-08-19 | 爱诺彼得技术有限责任公司 | Combined distortion estimation and error correction coding for memory devices |
| CN102932006A (en) * | 2012-11-19 | 2013-02-13 | 电子科技大学 | Average magnitude based weighted bit-flipping decoding method for low-density parity-check codes |
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