CN105161137B - Nand Flash controller circuitry realization device in a kind of MLC architecture - Google Patents
Nand Flash controller circuitry realization device in a kind of MLC architecture Download PDFInfo
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Abstract
The error checking and correct ECC module that error correcting capability can match are embedded the invention discloses Nand Flash controller NFC circuit realization device in a kind of MLC architecture, in the NFC；The ECC module includes ECC_Enc_Sx module, DeCodeBM module, DeCodeChien module, DeCodeCor module and ECC_Flow_Ctrl module, wherein, ECC_Enc_Sx module, code word is acquired for carrying out coding to the data received, and syndrome is calculated according to the systematic code received；DeCodeBM module for solving key equation according to syndrome, and acquires error location polynomial according to key equation；DeCodeChien module, for determining errors present according to error location polynomial；DeCodeCor module, for carrying out the error correction of corresponding data according to errors present；ECC_Flow_Ctrl module, for controlling other modules.By means of the invention it is possible to realize that the ECC of the high-performance of Nand Flash controller and highly compatible is designed in MLC architecture.
Description
Technical field
The present invention relates to technical field of integrated circuits, espespecially a kind of multi-level point is hired (MLC, Multi Level Cell) frame
Large capacity nonvolatile memory (Nand Flash) controller circuitry realization device in structure.
Background technique
Nand Flash is with it with non-volatile, erasability, lesser chip area, faster write-in and erasing speed
Degree and less expensive every bit price, are widely used in a variety of applications in the mass-memory units such as mobile phone, mobile memory card.
The characteristics of due to Nand Flash structure and its noise jamming etc., factors may produce when data storage is on Nand Flash
The reversion of raw individual bits, so as to cause storing data error.Nand Flash is more by every Cell storage in MLC architecture
Bits realizes the leap at double on capacity, is the trend of Nand Flash of new generation, but due between adjacent data voltage
Space become smaller, the error probability of MLC architecture Nand Flash is bigger, and mistake once occurs, will lead to 2 times or more
Corrupted data.It therefore is usually all when data write-in storage in order to can be carried out error detection and correction when guaranteeing that data are read
When unit, needs that a part of redundant data is artificially written by certain rule, carry out error checking with error correcting code circuitry and entangle
Positive (ECC, Error Code Correction) Error Control.In view of the extensive use of Nand Flash, recent domestic pair
The research and design of Nand Flash controller are all carried out like a raging fire.
Be currently used for the codec of Nand Flash controller, error correcting capability be it is fixed, generally 4bit or
8bit the advantage is that specificity is good, and area is small, be suitable for existing redundant space be 16bytes/512bytes or
The Nand Flash of 128bytes/4K bytes.Due to the progress of technique, the reduction of line width, Nand Flash storage density is got over
Come higher, error probability is also increasing, therefore the redundant space in a new generation Nand Flash has been increased to 218bytes/4K
Bytes, allowing for Nand Flash controller in this way can be using the error correcting code for entangling more bits mistakes, to reduce Nand
The error rate of Flash, and the existing ECC for being only capable of correcting 4bit or 8bit mistake far can not reach requirement；On the other hand,
It is existing to entangle 15bit or 24bit decoder below, due to its not configurability, so that verification bits length is fixed simultaneously
And it is greater than 16bytes, it is only used for the Nand Flash of MLC type of new generation, may not apply to common Nand Flash, to
Lower compatibility is bad.
In addition, at present, about the research and design of Nand Flash controller circuitry, there are following defects both at home and abroad:
First, poor compatibility, this is because the ECC circuit in most of Nand Flash controller is all based on certain
One specific application system or certain a specific Nand Flash are designed；
Second, data transmission bauds is slow, this is primarily referred to as those and uses software as the ECC electricity for Software-only method realization of advocating peace
Road；
Third, data reliability is poor, some Nand Flash controllers do not have data check function or ECC check energy
Power is lower；
4th, area is big, and power consumption is high, this is primarily due to the design of many ECC and has used to pursue function largely
Register, while again do not pay attention to reduce power consumption.
Summary of the invention
It is real that in order to solve the above-mentioned technical problems, the present invention provides Nand Flash controller circuitrys in a kind of MLC architecture
Existing device can be realized the ECC of the high-performance of Nand Flash controller and highly compatible in MLC architecture and design.
In order to reach the object of the invention, the present invention provides Nand Flash controller circuitrys in a kind of MLC architecture to realize
Device, the Nand Flash controller NFC and Nand Flash and two-way programmable storage Dpram carry out data exchange,
The error checking and correct ECC module that error correcting capability can match are embedded in NFC；The ECC module include ECC_Enc_Sx module,
DeCodeBM module, DeCodeChien module, DeCodeCor module and ECC_Flow_Ctrl module, wherein
ECC_Enc_Sx module acquires code word for carrying out coding to the data received, and according to the system received
Code calculates syndrome；DeCodeBM module for solving key equation according to syndrome, and acquires error bit according to key equation
Set multinomial；DeCodeChien module, for determining errors present according to error location polynomial；DeCodeCor module is used
According to errors present, the error correction of corresponding data is carried out；ECC_Flow_Ctrl module, for control ECC_Enc_Sx module,
DeCodeBM module, DeCodeChien module and DeCodeCor module.
Compared with prior art, ECC circuit of the invention is embedded in Nand Flash controller, realizes Nand
Verification control in Flash data transmission, ECC error correction digit can match, 512Byte data block can at most be supported to entangle 12bit
Mistake, 1K byte data block can at most entangle 40bit mistake.Scheme as a result, by using software and hardware combining, based on hardware
It is fast to devise a transmission speed, compatibility is strong, high reliablity, the strong band for MLC architecture Nand Flash of error correcting capability
There is the Nand Flash controller circuitry of ECC data error correction.
Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification
It obtains it is clear that understand through the implementation of the invention.The objectives and other advantages of the invention can be by specification, right
Specifically noted structure is achieved and obtained in claim and attached drawing.
Detailed description of the invention
Attached drawing is used to provide to further understand technical solution of the present invention, and constitutes part of specification, with this
The embodiment of application technical solution for explaining the present invention together, does not constitute the limitation to technical solution of the present invention.
Fig. 1 is the structural schematic diagram of Nand Flash in MLC architecture in a kind of embodiment of the invention.
Fig. 2 is the signal of Nand Flash controller circuitry realization device in MLC architecture in a kind of embodiment of the invention
Figure.
Fig. 3 is the schematic diagram of ECC module in a kind of embodiment of the invention.
Fig. 4 is the schematic diagram that the circuit of ECC_Enc_Sx module in ECC module in Fig. 3 is realized.
Fig. 5 is the schematic diagram that the circuit of DeCodeBM module in ECC module in Fig. 3 is realized.
Fig. 6 is the schematic diagram that the circuit of DeCodeChien module and DeCodeCor module is realized in ECC module in Fig. 3.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention
Embodiment be described in detail.It should be noted that in the absence of conflict, in the embodiment and embodiment in the application
Feature can mutual any combination.
Step shown in the flowchart of the accompanying drawings can be in a computer system such as a set of computer executable instructions
It executes.Also, although logical order is shown in flow charts, and it in some cases, can be to be different from herein suitable
Sequence executes shown or described step.
Different vendor can supply for a long time, process stabilizing and the Nand Flash of the MLC architecture of volume production needed for ECC
The digit of error correction is not quite similar, and by taking Samsung and Micron Technology as an example, table 1 describes the amount of capacity of this two products, error correction requirement, page
Size (Pagesize) and redundancy size (Sparesize).A part gives file system in the space in the area capacity (Spare)
With another part is for storing check bit.Therefore it is designed according to the requirement of different Nand Flash error correcting capabilities configurable
ECC entangle decoder module, have important research significance.
Table 1
For the difference of the redundant space of current Nand Flash, the invention proposes the one of the different Nand Flash of compatibility
The configurable ECC circuit implementation of kind.
Fig. 1 is Nand Flash interface diagram, and wherein AHB BUS is Advanced High-performance Bus
Agreement has the bus protocol of permanent order between address and control signal and data；DMA is direct memory access；
Parctl is register control；Intctl is to interrupt control；P is port controlling；Fsm is state machine.
As shown in Figure 1, Nand Flash controller (NFC) and large capacity nonvolatile memory (Nand Flash) and pair
Data exchange is carried out to programmable storage (Dpram), the ECC module that error correcting capability can match is embedded in NFC.Wherein, due to
It accesses Nand Flash and needs certain interface sequence, NFC is exactly to realize the controller for being able to access that Nand Flash；
Nand Flash is the data storage of large capacity, to be accessed to it, and the data transmission of large capacity is mainly made；Dpram
As caching, storage needs to be written the data of Nand flash, chip is needed to be written nand flash's by NFC interface
Data move out in dpram to be come, in the timing write-in nand flash required further according to nand flash.NFC and Nand
The data exchange ways of Flash and Dpram mode according to used in different chips is different, such as uses buffer, single port
Ram, ram of twoport etc..It is more efficient in order to make in specific embodiments of the present invention, use twoport ram.
Since Nand Flash write-in data are possible to malfunction, so NFC needs ECC error correction circuit.When data pass
When on to Nand Flash data line, while also entering ECC module and carrying out data encoding, the data transfer ends, while ECC coding
It completes, transmission code word is written together in Nand Flash on the data line at this time.Read data it is also similar, when data be written Dpram,
ECC module is also passed to simultaneously, is decoded operation.The control of these operations is controlled by NFC module state machine.
Fig. 2 is the structural schematic diagram of Nand Flash controller.As shown in Fig. 2, Nand Flash controller includes: control
Signal output register, system interface circuit, NFC module work register group, NFC module state machine, control signal decoder,
Dpram control signal and data input/output register, Nand Flash control signal and data input/output register and
ECC module, wherein Nand Flash controller, for being responsible for data and order of the parsing from bus end, and according to Nand
The interface sequence of Flash requires to send order and data to target Nand Flash device；The realization pair of register configuration module
The configuration feature of all kinds of registers in Nand Flash controller；Input into/output from cache is used to cache the number of dealing Nand Flash
According to the rate of balance ECC coder and bus.
System interface circuit for completing read and write access of the system bus to NFC module work register, and generates corresponding
Ack signal.
Dpram controls signal and data input/output register, the input of the control signal and data for Dpram and defeated
Out, the output of this group of signal is register output.
Nand Flash controls signal and data input/output register, for export the control signal of Nand Flash with
And the data of Nand Flash to be written are provided, the output of the group and control signal are register output, and input signal passes through
One falling edge detectors, which exports, gives NFC module state machine.
NFC module state machine, it is corresponding to decide whether to continue for detecting the BUSY/READY state of Nand Flash
Operation.Specifically, it after Nand Flash receives order according to timing, can wipe accordingly, the operation such as write-read, when operation starts
BUSY signal can be provided, the signal becomes READY after operation, this signal is that NFC, NFC are fed by BUSY/READY
Jumping for NFC state machine can be determined according to BUSY/READY signal.
Control signal output register, for parse realize Nand Flash clock signal, be mainly used for realize with
The processing of the port information of Nand Flash interaction.
NFC module work register group interrupts enabled equal signals for configuring the enabling of NFC.
Control signal decoder, for giving ECC after the information parsing after system configuration NFC module work register group
Module, and NFC module work register group is given after the information decodings such as state that ECC module is generated, for CPU inquiry etc..
ECC module is an independent module.In a specific embodiment of the present invention, the ECC module is for calculating
The ECC check error correction of 512bytes 1K bytes, does not do other judgements.Starting and stopping for ECC module is arranged by software,
Whether data effectively also need NFC module state machine to indicate in bus simultaneously.The ECC coding that the ECC module ultimately generates
It is exported by control signal decoder and gives NFC module work register group, for CPU processing and accessed.Read data when and Nand
The ECC that takes out in Flash, which is compared, realizes error correction, write-in when every data for having inputted a 512bytes or 1Kbytes,
CPU reads an ECC value and is inserted in Dpram and corresponded in the corresponding data position of Nand Flash.
As shown in figure 3, ECC module include ECC_Enc_Sx module, DeCodeBM module, DeCodeChien module,
DeCodeCor module and ECC_Flow_Ctrl module, wherein
ECC_Enc_Sx module acquires code word, and the systematic code R by receiving for carrying out coding to the data received
(x) syndrome is calculated, syndrome is also known as syndrome S (x)；
DeCodeBM module for solving key equation according to syndrome S (x), and acquires error bit according to key equation
Set multinomial σ (x) and error value multinomial ω (x)；
DeCodeChien module is used for according to error location polynomial σ (x) and error value multinomial ω (x), using money
Searching algorithm acquires errors present；
DeCodeCor module, for carrying out the error correction of corresponding bit according to errors present；
ECC_Flow_Ctrl module, for controlling the working condition of entire circuit.
Specifically, the circuit of ECC_Enc_Sx module is realized as shown in Figure 4.
Coding is carried out to the data received by ECC_Enc_Sx module and acquires code word, as shown in figure 4, initial value is complete
0,16 data nfc_ecc_data [15:0] are inputted, one group of data is often carried out, the value in register carries out one by combinational logic
Secondary update, it is the code word acquired that data, which write the value in late register,.
It solves correction subprocess and is divided into two steps: the first step, complementation formula (RC Div ψ i)；Second step substitutes into evaluation (RC
Eval (α i)), α i is taken in residue si (x), final syndrome can be acquired.Detailed solution process is those skilled in the art
Known to member, so it will not be repeated.To sum up, the circuit of ECC_Enc_Sx module is by constituting with door and XOR gate, is mode with door
Required for selection, and exclusive or is then the add operation of field element.
Specifically, the circuit of DeCodeBM module is realized as shown in Figure 5.
Table 2 is resource required for BM iterative algorithm.
Table 2
According to table 2, error location polynomial part is solved using the simplified BM iterative algorithm (SiBM) that do not invert.According to
The compromise of area and speed selects 9 processing units (PE) and 49 registers real in a specific embodiment of the present invention
It is existing.9 SiBM pe array are formed, each PE includes three finite field multipliers and a finite field addition, and there are also one
A m multiple selector.SiBM algorithm, in the r times iteration, in SiBM.1 the update of i-th of coefficient can in SiBM.2
The update of i+1 coefficient can be calculated simultaneously, SiBM algorithm structure is uniform, without the resource in hardware realization of inverting
Reusability is higher.
DeCodeChien modular circuit is realized as shown in Figure 6.
Specifically, error location polynomial σ (x)=1+ σ is calculated by BM iterative algorithm1x+σ2x2+…+σtxt, then
It can use chien search algorithm and find out root of polynomial X, root is the inverse of errors present.Chien search algorithm essence is a kind of
The method for trying root.Since galois field GF is a finite field, domain interior element number is limited, and is 214- 1 (N), therefore can
To attempt all possible X=α1,α2,α3….αNIn substitution formula, its value is 0 after bringing multinomial into for corresponding i, then
Just corresponding errors present 2 is had found14-1-i。
In a specific embodiment of the present invention, money search circuit searches root using four parallel, the highest of the money search circuit
Error correcting capability t=40, therefore error location polynomial are as follows:
σ (x)=σ40x40+σ39x39+...σ23x23+σ22x22+σ21x21+σ20x20+σ19x19+σ18x18+σ17x17+σ16x16+σ15x15+σ14x14+σ13x13+σ12x12+σ11x11+σ10x10+σ9x9+σ8x8+σ7x7+σ6x6+σ5x5+σ4x4+σ3x3+σ2x2+σ1x+1。
By x=αiIt substitutes into error location polynomial σ (x):
σ(αi)=σ40(αi)40+σ39(αi)39+...σ24(αi)24+σ23(αi)23+σ22(αi)22+σ21(αi)21+σ20(αi)20+
σ19(αi)19+σ18(αi)18+σ17(αi)17+σ16(αi)16+σ15(αi)15+σ14(αi)14+σ13(αi)13+σ12(αi)12+σ11(αi)11+σ10
(αi)10+σ9(αi)9+σ8(αi)8+σ7(αi)7+σ6(αi)6+σ5(αi)5+σ4(αi)4+σ3(αi)3+σ2(αi)2+σ1αi+1。
By x=αi+1It substitutes into error location polynomial σ (x):
σ(αi+1)=σ40(αi)40+σ39(αi)39+...σ24(αi+1)24+σ23(αi+1)23+σ22(αi+1)22+σ21(αi+1)21+σ20
(αi+1)20+σ19(αi+1)19+σ18(αi+1)18+σ17(αi+1)17+σ16(αi+1)16+σ15(αi+1)15+σ14(αi+1)14+σ13(αi+1)13+σ12
(αi+1)12+σ11(αi+1)11+σ10(αi+1)10+σ9(αi+1)9+σ8(αi+1)8+σ7(αi+1)7+σ6(αi+1)6+σ5(αi+1)5+σ4(αi+1)4+
σ3(αi+1)3+σ2(αi+1)2+σ1αi+1+1；
=σ40(αi)40α40+σ39(αi)39α39+...σ24(αi)24α24+σ23(αi)23α23+σ22(αi)22α22+σ21(αi)21α21+
σ20(αi)20α20+σ19(αi)19α19+σ18(αi)18α18+σ17(αi)17α17+σ16(αi)16α16+σ15(αi)15α15+σ14(αi)14α14+σ13
(αi)13α13+σ12(αi)12α12+σ11(αi)11α11+σ10(αi)10α10+σ9(αi)9α9+σ8(αi)8α8+σ7(αi)7α7+σ6(αi)6α6+σ5
(αi)5α5+σ4(αi)4α4+σ3(αi)3α3+σ2(αi)2α2+σ1(αi)α+1。
It is derived from by above-mentioned, σ (αi+1) items be σ (αi) corresponding entry multiplied by a known element-specific, σ
(αi+1) n-th be σ (αi) n-th multiplied by αn(n is integer), it may be assumed that
σ(αi+1) the 40th be σ (αi) the 40th multiplied by α40；
σ(αi+1) the 39th be σ (αi) the 39th multiplied by α39；
……
σ(αi+1) Section 24 be σ (αi) Section 24 multiplied by α24；
σ(αi+1) Section 23 be σ (αi) Section 23 multiplied by α23；
……
σ(αi+1) Section 2 be σ (αi) Section 2 multiplied by α2；
σ(αi+1) first item be σ (αi) first item multiplied by α.
Therefore, using field element multiplication, error location polynomial and some field element, the field element can be calculated
Money search is divided into several groups parallel computation with this by the search situation of later each element.
Since the present invention shortens code (one kind of ECC algorithm) using BCH, some is 0 always, is that will not malfunction
, so first to be pre-processed before carrying out money search, i.e., needed after BM iteration be to error location polynomial
Number is multiplied by α(16381-14t-4096)*i(data of 512bytes) or α(16381-14t-8192)*i(data of 1k bytes), so may be used
To save the time for searching 0.
In this way, DeCodeChien module first initializes the error location polynomial coefficient lambda that BM is provided,
Error correction mode of the present invention is configurable, and mainly include following 2 kinds of modes: 512byte entangles mistake within 12bit, and 1024byte entangles
Ecc_mode value 0 or 1 is arranged by register configuration to select different modes, if such as ecc_mode in mistake within 40bit
=1, error correction t=12, that is, entangle mistake within 12bit, needs to search for 4264 bit informations altogether, and 1066 clk is needed to complete search.
If ecc_mode=0, error correction t=40, that is, mistake within 40bit is entangled, needs to search for 8752 altogether, 2188 clk is needed to complete
Search.It was found that being corrected after mistake by DeCodeCor module.Due to being 2 binary datas, if error, directly takes it
It is counter that error correction can be completed.
In the present invention, by the correctness of Matlab verification algorithm, wave simulation is verified using ModelSim, is guaranteed
The correctness of algorithm and timing.The present invention has done 1,000,000 groups of tests, error in data number during the test, by ModelSim
It is traversed by 0-50, errors present is random, and verification result is all correct.
In a specific embodiment of the present invention, the Nand Flash control circuit with BCH codec can use Huahong
0.13 μm of technique flow successively passes through FPGA and board level test, uses Flash chip for the K9GBG08U0B of Samsung,
K9G4G08X0B test speed is 10MB/s.By actual measurement, mistake is worked as using 512byte as data cell for K9G4G08X0B
In 12bit can normal error correction, for K9GBG08U0B, using 1k byte as data cell, when mistake can in 40bit
Normal error correction can guarantee that data correctly communicate in normal read-write for above-mentioned 2 sections of FLASH.Mistake is more than error correction energy
Power can be reported an error by register.To sum up, the controller circuitry error correcting capability that the present invention realizes can match, and function is correct.
Be currently used for the codec of Nand Flash controller, error correcting capability be it is fixed, generally 4bit or
8bit the advantage is that specificity is good, and area is small, and being suitable for existing redundant space (spare area) is 16bytes/
The Nand Flash of 512bytes or 128bytes/4K bytes.On the other hand, existing to entangle 15bit or 24bit or less
Decoder, since its not configurability is only used for a new generation so that 16bytes is fixed and be greater than to verification bits length
The Nand Flash of MLC type, may not apply to common Nand Flash, and downward compatibility is bad.Compared with the existing technology,
The present invention has carried out at least 3 points of improvement below:
(1) error correcting capability is configurable, and coding is real-time.
ECC circuit proposed by the present invention has the characteristics that error correcting capability is configurable, and error correcting capability is to correct respectively
In 512bytes data in the 12bits mistake of random distribution and 1K bytes data random distribution 40bits mistake.This hair
The coding of bright proposition and to seek correction sub-circuit be 16 parallel-by-bits, the Nand Flash for being either 8 for interface bit wide, also
It is the Nand Flash that interface bit wide is 16, is encoded when writing data into Nand Flash, while to it, it is final real
Show and has carried out real-time data encoding circuit with the write operation of Nand Flash.
(2) optimize money search circuit
The money search used when solving bit-error locations is the process of a full search, calculating when big data quantity verification decodes
It measures larger.Money search is the bottleneck for verifying speed, and in order to improve verification speed, the present invention is optimized by searching for money,
It is searched in the areal extent of permission using grouping parallel, search speed is improved 4 times.
(3) BM iteration module uses SiBM algorithm, and area is saved in hardware resource multiplexing.
When solving errors present equation, using SiBM algorithm, which does not have inversion operation, and circuit structure is uniform, firmly
Part can be with resource multiplex, to save circuit area, this is an innovative point for realizing BCH algorithm, and present invention employs this
SiBM algorithm, but it is optimized, and can be multiplexed with some arithmetic elements of money search circuit module, it can save
Chip area.
ECC circuit is embedded in Nand Flash controller in the present invention, is realized in the transmission of Nand Flash data
Verification control, ECC error correction digit can match, 512Byte data block can at most be supported to entangle 12bit mistake, 1K byte data block
40bit mistake can at most be entangled.As a result, by using software and hardware combining, a transmission speed of conceptual design based on hardware
Fastly, compatibility is strong, high reliablity, error correcting capability it is strong for MLC architecture Nand Flash with ECC data error correction
Nand Flash controller circuitry.
Although disclosed herein embodiment it is as above, the content only for ease of understanding the present invention and use
Embodiment is not intended to limit the invention.Technical staff in any fields of the present invention is taken off not departing from the present invention
Under the premise of the spirit and scope of dew, any modification and variation, but the present invention can be carried out in the form and details of implementation
Scope of patent protection, still should be subject to the scope of the claims as defined in the appended claims.
Claims (9)
1. a kind of multi-level point is hired large capacity nonvolatile memory Nand Flash controller circuitry in MLC architecture and realizes dress
It sets, which is characterized in that
Nand Flash controller NFC and Nand Flash and two-way programmable storage Dpram carries out data exchange, described
The error checking and correct ECC module that error correcting capability can match are embedded in NFC；
The ECC module includes error correction mode configuration register, error correction mode is arranged by the register are as follows: 512byte entangles
Mistake or 1024byte entangle mistake within 40bit within 12bit；
The ECC module includes ECC_Enc_Sx module, and the ECC_Enc_Sx module carries out coding to the data received and asks
Obtain code word, comprising:
Initial value is full 0, inputs 16 data nfc_ecc_data [15:0], when data transmission is to Nand Flash data line,
Enter ECC module simultaneously and carries out data encoding；Often carry out one group of data, the value in register carries out once more by combinational logic
Newly, it is the code word acquired that data, which write the value in late register, and calculates syndrome according to the systematic code received；
The ECC_Enc_Sx module with door and XOR gate by constituting.
2. the apparatus according to claim 1, which is characterized in that the ECC module includes DeCodeBM module, described
DeCodeBM module includes at the BM iterative algorithm SiBM of the simplification that 9 processing unit PE and 49 registers are formed not inverted
Cell array is managed, wherein each PE includes 3 finite field multipliers, 1 finite field addition and 1 m multiple selector.
3. the apparatus of claim 2, which is characterized in that the DeCodeBM module uses the SiBM, according to school
Positron S (x) solves key equation, and acquires error location polynomial σ (x) and error value multinomial ω (x) according to key equation；
The SiBM algorithm, specifically:
In the r times iteration, the update of the i+1 coefficient in SiBM.N in the update and SiBM.N+1 of i-th of coefficient is simultaneously
It is calculated, PE updates simultaneously in 1 SiBM processing unitI-th coefficient andI+1 system
Number.
4. the apparatus according to claim 1, which is characterized in that the ECC module includes DeCodeChien module, described
DeCodeChien module determines errors present according to error location polynomial, specifically:
The DeCodeChien module is error bit using the root x, x that chien search algorithm finds out error location polynomial σ (x)
The inverse set.
5. device according to claim 4, which is characterized in that find out error location polynomial σ using chien search algorithm
(x) root x, specifically:
Root is tried to domain interior element using chien search algorithm, the number of domain interior element is 214- 1 (N), by the root x=of domain interior element
α1,α2,α3….αNThe error location polynomial for substituting into chien search algorithm, is worth after i-th bit root brings error location polynomial into
It is 0, it is determined that corresponding errors present is 214-1-i。
6. device according to claim 4, which is characterized in that the error location polynomial of the chien search algorithm are as follows:
σ (x)=σ40x40+σ39x39+...σ23x23+σ22x22+σ21x21+σ20x20+σ19x19+σ18x18+σ17x17+σ16x16+σ15x15+σ14x14+σ13x13+σ12x12+σ11x11+σ10x10+σ9x9+σ8x8+σ7x7+σ6x6+σ5x5+σ4x4+σ3x3+σ2x2+σ1x+1。
7. device according to claim 5, which is characterized in that the root of the domain interior element is αiAnd αi+1When errors present
Polynomial relationship are as follows:
σ(αi+1) n-th be σ (αi) n-th multiplied by αn, n is integer；
The DeCodeChien module is according to αiAnd αi+1When error location polynomial relationship, calculate domain interior element n-th
Search situation afterwards, and domain interior element grouping parallel is calculated.
8. device according to claim 7, which is characterized in that errors present of the DeCodeChien module in solution
After multinomial, for the data of 512bytes, by the coefficient of error location polynomial multiplied by α(16381-14t-4096)*i；For 1k
The data of bytes, by the coefficient of error location polynomial multiplied by α(16381-14t-8192)*i。
9. the apparatus according to claim 1, which is characterized in that described device further include: control signal output register, be
System interface circuit, NFC module work register group, NFC module state machine, control signal decoder, Dpram control signal and number
According to input/output register and Nand Flash control signal and data input/output register, wherein
System interface circuit for completing read and write access of the system bus to NFC module work register, and generates corresponding
Ack signal；
Dpram controls signal and data input/output register, and the control signal and data for Dpram are output and input；
Nand Flash controls signal and data input/output register, for export Nand Flash control signal and to
The data of Nand Flash to be written out, input signal is exported by a falling edge detectors and gives NFC module state machine；
NFC module state machine for detecting the BUSY/READY state of Nand Flash, and feeds back to NFC；
Signal output register is controlled, for parsing the clock signal for realizing Nand Flash；
NFC module work register group interrupts enable signal for configuring the enabling of NFC；
Control signal decoder, for giving ECC mould after the information parsing after system configuration NFC module work register group
Block, and NFC module work register group is given after the information decoding that ECC module is generated.
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| US10824554B2 (en) * | 2016-12-14 | 2020-11-03 | Via Technologies, Inc. | Method and apparatus for efficiently sorting iteration with small sorting set |
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| CN101483442A (en) * | 2009-02-11 | 2009-07-15 | 芯原微电子(上海)有限公司 | BCH decoder for configuring error correcting capability according to Nand Flash extra space |
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| CN101483442A (en) * | 2009-02-11 | 2009-07-15 | 芯原微电子(上海)有限公司 | BCH decoder for configuring error correcting capability according to Nand Flash extra space |
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