CN106776104B - Nand Flash controller, terminal and method for controlling Nand Flash - Google Patents
Nand Flash controller, terminal and method for controlling Nand Flash Download PDFInfo
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- CN106776104B CN106776104B CN201610994244.5A CN201610994244A CN106776104B CN 106776104 B CN106776104 B CN 106776104B CN 201610994244 A CN201610994244 A CN 201610994244A CN 106776104 B CN106776104 B CN 106776104B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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Abstract
A Flash memory (Nand Flash) controller and terminal and a method and apparatus for controlling Nand Flash, comprising: the first register, the third register and the Nand Flash state machine circuit are used for analyzing the command in the first register, and when the command obtained by analysis is a write-in command, data needing to be written in the Nand Flash in the third register is written in the DPRAM signal input and output circuit of the dual-port random access memory and is written in the Nand Flash; after the data with the second preset length is written into the Nand Flash, reading redundant codes in a register set in the ECC generation module and writing the redundant codes into the Nand Flash; the DPRAM signal input/output circuit is used for storing data written by the Nand Flash state machine circuit; the ECC generation module comprises an encoding submodule and a register set; and the coding submodule is used for coding and calculating the data needing to be written in the Nand Flash according to the pre-configured error correction capability to obtain a redundancy code in the process that the Nand Flash state machine circuit writes the data needing to be written in the Nand Flash in the DPRAN signal input and output circuit into the Nand Flash, and storing the redundancy code in the register group.
Description
Technical Field
The present disclosure relates to, but not limited to, storage technologies, and more particularly, to a Flash memory (Nand Flash) controller and terminal and a method of controlling Nand Flash.
Background
Flash memory (Nand Flash) is widely used in mass storage devices such as mobile phones and mobile memory cards. As shown in fig. 1, in order to ensure that Error detection and Correction can be performed during data reading, when data is written in NandFlash, a part of redundant data needs to be written according to a certain rule, and an Error Correction Code (ECC) control is performed by using an Error Correction coding and decoding circuit.
The related technical scheme is as follows:
the error correction coding and decoding circuit for the Nand Flash controller is not configurable for the error correction capability of the ECC, the adaptability is influenced, the area of the error correction coding and decoding circuit is increased a lot along with the increase of the error correction capability, and the influence generated by the power consumption of the Nand Flash controller is obvious at this time.
For the problem of larger power consumption, the power consumption of the Nand Flash controller can be reduced by clock frequency reduction, clock reversal and the like, but for the ECC algorithm with larger data capacity and stronger error correction capability, the frequency reduction can influence the encoding and decoding time, so that the reading and writing speed is influenced, and the related proposed Nand Flash controller has low power consumption, small area and weaker corresponding ECC capability.
At present, the research and design of circuits of Nand Flash controllers at home and abroad have the following defects:
first, the scalability is poor, because most error correction coding/decoding circuits in Nand Flash controllers are designed based on a specific application system or a specific Nand Flash.
Secondly, the adaptability is poor, some Nand Flash controllers do not have a data checking function, or the ECC checking capability is low, and the error correction requirement of the Nand Flash with large capacity cannot be met.
Third, power consumption is high, mainly because many ECC designs use a large number of registers for functionality, while not paying attention to reduce power consumption.
Fourth, the transmission speed is slow. Some controller designs use frequency reduction in low power consumption designs, which trades off speed for power consumption reduction.
Disclosure of Invention
The embodiment of the invention provides a Nand Flash controller, a terminal and a method for controlling Nand Flash, which can improve the expandability of the Nand Flash controller.
The embodiment of the invention provides a Nand Flash controller of a Flash memory, which comprises:
the first register is used for storing the stored command of the CPU;
the third register is used for storing data needing to be written into the Nand Flash;
the Nand Flash state machine circuit is used for analyzing the command in the first register, writing the data needing to be written in the Nand Flash in the third register into the DPRAM signal input and output circuit of the double-port random access memory when the analyzed command is a write-in command, and writing the data needing to be written in the Nand Flash in the DPRAM signal input and output circuit into the Nand Flash; after the data with the second preset length is written into the Nand Flash, reading the redundant codes in the register set in the ECC generation module, and writing the redundant codes into the Nand Flash;
the DPRAM signal input/output circuit is used for storing data written by the Nand Flash state machine circuit;
the ECC generation module comprises an encoding submodule and a register set;
the coding submodule is used for carrying out coding operation on the data needing to be written in the Nand Flash according to the pre-configured error correction capability to obtain a redundant code in the process that the Nand Flash state machine circuit writes the data needing to be written in the Nand Flash in the DPRAN signal input-output circuit into the Nand Flash, and storing the calculated redundant code into the register group;
and the register group is used for storing the redundant codes written in the coding submodule.
Optionally, the Nand Flash controller further includes:
a second register for accessing an address of the CPU storing the read data;
the Nand Flash state machine circuit is further configured to:
when the command obtained by analysis is a read command, sequentially reading data to be read and corresponding redundant codes in Nand Flash by taking a third preset length as a unit according to the address in the second register, and writing the read data and the redundant codes into the DPRAM signal input/output circuit until the data with the length being an integral multiple of the second preset length is written into the DPRAM signal input/output circuit; when a signal of completing correction of the coding submodule is received, a control system interface and an interrupt circuit generate an interrupt signal; when the CPU reads data from the third register, the corrected data in the DPRAM signal input and output circuit is written into the third register;
the ECC generation module further comprises a decoding sub-module;
and the decoding submodule is used for correcting the read data with the second preset length according to the redundant codes in the DPRAM signal input-output circuit and sending a corrected signal to the Nand Flash state machine circuit.
Optionally, the Nand Flash state machine circuit is further configured to:
when the command obtained by analysis is a write-in command, controlling a decoding submodule in the ECC generation module to be in a non-working state;
and when the command obtained by analysis is a read command, controlling the coding submodule in the ECC generation module to be in a non-working state.
Optionally, the number of the register groups is N; n is an integer greater than or equal to 1;
the Nand Flash state machine circuit is further configured to:
and when the command obtained by analysis is a write-in command, determining the number of the required register groups according to the pre-configured error correction capability, setting the required register groups to be in a working state, and setting other register groups to be in a non-working state.
Optionally, the Nand Flash state machine circuit is further configured to:
and when the command obtained by analysis is a setting instruction, setting corresponding parameters according to the setting instruction.
Optionally, the Nand Flash state machine circuit is specifically configured to:
analyzing the command in the first register, when the command obtained by analyzing is a write-in command, writing data with the length being an integral multiple of a second preset length in data needing to be written in Nand Flash in the third register into the DPRAM signal input and output circuit, and sequentially writing data with the second preset length in data with the length being an integral multiple of the second preset length in the DPRAM signal input and output circuit into the Nand Flash by taking the third preset length as a unit;
after data with a second preset length is written into the Nand Flash, reading redundant codes in a register set in the ECC generation module, and writing the redundant codes into the Nand Flash;
continuing to perform the step of sequentially writing the next data with the second preset length in the data with the length being the integral multiple of the second preset length into the Nand Flash by taking the third preset length as a unit until all the data with the length being the integral multiple of the second preset length and the corresponding redundancy codes are written into the Nand Flash;
and continuing to execute the step of writing the next data with the length being the integral multiple of the second preset length in the data needing to be written in the Nand Flash into the DPRAM signal input-output circuit until all the data needing to be written in the Nand Flash are written into the DPRAM signal input-output circuit.
Optionally, the Nand Flash state machine circuit is specifically configured to:
sequentially writing data needing to be written into the Nand Flash into a DPRAM signal input and output circuit by taking a first preset length as a unit, and sequentially writing the data needing to be written into the Nand Flash in the DPRAM signal input and output circuit into the Nand Flash by taking a third preset length as a unit;
after the data with the second preset length is written into the Nand Flash, reading the redundant codes in the register set in the ECC generation module, and writing the redundant codes into the Nand Flash;
and continuing to execute the step of sequentially writing the data needing to be written in the Nand Flash into the DPRAM signal input and output circuit by taking the first preset length as a unit until all the data needing to be written in the Nand Flash are written into the DPRAM signal input and output circuit.
Optionally, the error correction capability includes:
the 512Bytes of byte data correct 4bits or 8bits or 15bits errors, or the 1K Bytes of byte data correct 24bits or 40bits or 60bits errors.
An embodiment of the present invention further provides a terminal, including: any one of the Nand Flash controllers;
further comprising:
nand Flash for storing data written by the CPU;
a CPU for storing the command in a first register; when the stored command is a write-in command, storing data needing to be written in the NandFlash into a third register; and when the stored command is a read command, storing the address of the read data into the second register.
Optionally, the CPU is further configured to:
and reading data from the third register after detecting the interrupt signals generated by the system interface and the interrupt circuit.
Optionally, the CPU is further configured to:
and receiving a setting instruction from a user, and storing the setting instruction into the first register.
The embodiment of the invention also provides a method for controlling the Nand Flash of the Flash memory, which comprises the following steps:
the CPU stores the write-in command into a first register of the Nand Flash controller, and stores data needing to be written into the Nand Flash into a third register of the Nand Flash controller;
the Nand Flash state machine circuit of the Nand Flash controller analyzes the command in the first register, when the command obtained by analysis is a write-in command, data needing to be written in the Nand Flash in the third register is written in a DPRAM signal input and output circuit of the dual-port random access memory, and the data needing to be written in the Nand Flash in the DPRAM signal input and output circuit is written in the Nand Flash; after the data with the second preset length is written into the Nand Flash, reading the redundant codes in the register set in the ECC generation module, and writing the redundant codes into the Nand Flash;
and a coding sub-module of an ECC generation module of the Nand Flash controller performs coding operation on data needing to be written in the Nand Flash according to the pre-configured error correction capability to obtain a redundancy code in the process that the Nand Flash state machine circuit writes the data needing to be written in the Nand Flash in the DPRAN signal input/output circuit into the Nand Flash, and stores the calculated redundancy code into a register group of the ECC generation module.
Optionally, the method further includes:
the CPU stores the reading command into a first register of the Nand Flash controller and stores the address of the read data into a second register of the Nand Flash controller;
the Nand Flash state machine circuit analyzes the command in the first register, when the command obtained by analysis is a reading command, data needing to be read and corresponding redundant codes in the Nand Flash are sequentially read by taking a third preset length as a unit according to the address in the second register, and the read data and the redundant codes are written into the DPRAM signal input and output circuit until the data with the length being an integral multiple of the second preset length are written into the DPRAM signal input and output circuit;
a decoding submodule of an ECC generation module of the Nand Flash controller corrects the read data with the second preset length according to the redundant codes in the DPRAM signal input and output circuit and sends a corrected signal to a Nand Flash state machine circuit;
when the Nand Flash state machine circuit receives a signal of completing correction of the coding submodule, a control system interface and an interrupt circuit generate an interrupt signal;
after the CPU detects an interrupt signal generated by a system interface and an interrupt circuit of the Nand Flash controller, reading data from the third register;
when the CPU reads data from the third register, the Nand Flash state machine circuit writes the corrected data in the DPRAM signal input and output circuit into the third register.
Compared with the related art, the technical scheme of the embodiment of the invention comprises the following steps: the first register is used for storing the stored command of the CPU; the third register is used for storing data needing to be written into the Nand Flash; the Nand Flash state machine circuit is used for analyzing the command in the first register, writing the data needing to be written in the Nand Flash in the third register into the DPRAM signal input and output circuit of the double-port random access memory when the analyzed command is a write-in command, and writing the data needing to be written in the Nand Flash in the DPRAM signal input and output circuit into the Nand Flash; after the data with the second preset length is written into the Nand Flash, reading the redundant codes in the register set in the ECC generation module, and writing the redundant codes into the Nand Flash; the DPRAM signal input/output circuit is used for storing data written by the Nand Flash state machine circuit; the ECC generation module comprises an encoding submodule and a register set; the coding submodule is used for carrying out coding operation on the data needing to be written in the Nand Flash according to the pre-configured error correction capability to obtain a redundant code in the process that the Nand Flash state machine circuit writes the data needing to be written in the Nand Flash in the DPRAN signal input-output circuit into the Nand Flash, and storing the calculated redundant code into the register group; and the register group is used for storing the redundant codes written in the coding submodule. By the scheme of the embodiment of the invention, the error correction capability of the ECC generation module can be configured, so that the expandability of the Nand Flash controller is improved.
Optionally, the power consumption of the Nand Flash controller is reduced by controlling the decoding submodule and the encoding submodule to work at the same time.
Optionally, the power consumption of the Nand Flash controller is further reduced by controlling part of the register sets to be in a working state and other register sets to be in a non-working state.
Optionally, in the process that the CPU stores the data to be written into the Nand Flash in the third register, the Nand Flash controller writes the data into the Nand Flash at the same time, thereby increasing the writing speed.
Optionally, the Nand Flash controller can support 1K Bytes to correct 60bits at most, and the error correction capability of the Nand Flash controller is improved.
Drawings
The accompanying drawings in the embodiments of the present invention are described below, and the drawings in the embodiments are provided for further understanding of the present invention, and together with the description serve to explain the present invention without limiting the scope of the present invention.
FIG. 1 is a schematic diagram of the structure of a Nand Flash controller in the related art;
FIG. 2 is a schematic structural diagram of a Nand Flash controller according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating the operating state of a Nand Flash state machine circuit control register set according to an embodiment of the present invention;
fig. 4 is a schematic structural component diagram of a terminal according to an embodiment of the present invention;
FIG. 5 is a flowchart of a method for controlling Nand Flash according to an embodiment of the present invention.
Detailed Description
The following further description of the present invention, in order to facilitate understanding of those skilled in the art, is provided in conjunction with the accompanying drawings and is not intended to limit the scope of the present invention. In the present application, the embodiments and various aspects of the embodiments may be combined with each other without conflict.
Referring to fig. 2, an embodiment of the present invention provides a Nand Flash controller, including:
the device comprises a first register, a third register, a system interface, an interrupt circuit, a Nand Flash state machine circuit, a Double-Port Random Access Memory (DPRAM) signal input/output circuit and an ECC generation module.
The first register is used for storing the stored command of the CPU.
The CPU stores commands such as reset (reset), read (read), erase (erase), write (write), and the like.
When the command stored by the CPU is write-in, the CPU may store a write-in start command in the first register, then store data to be written in the third register, and store a write-in end command in the first register after the CPU stores all the data to be written in the third register.
The length of the data to be written may be set by a user or may be set as a fixed value. The length of data needing to be written set by a user cannot exceed the length of one page of Nand Flash, and the lengths of the Nand Flash with different specifications are different.
The CPU can store the data to be written into the third register at one time, and also can sequentially store the data to be written into the third register by taking the first preset length as a unit so as to improve the writing speed.
The first preset length may be set by a user or may be set as a fixed value. For example, the user may set the first preset length to be 32 bits (bit), and of course, the first preset length may also be another value, which is not limited in this embodiment of the present invention.
When the command stored by the CPU is reading, the CPU also stores the address of the read data into the second register.
And the third register is used for storing data needing to be written in the Nand Flash and/or data read from the Nand Flash.
The Nand Flash state machine circuit is used for analyzing the command in the first register, writing data needing to be written in the Nand Flash in the third register into the DPRAM signal input and output circuit when the analyzed command is a write-in command, and writing the data needing to be written in the Nand Flash in the DPRAM signal input and output circuit into the Nand Flash; and after the data with the second preset length is written into the Nand Flash, reading the redundant codes in the register set in the ECC generation module, and writing the redundant codes into the Nand Flash.
The second preset length may be set by a user or may be set as a fixed value. For example, the user may set the second preset length to 2nBytes (bytes), e.g., 1k byte or 512bytes, etc.
When the CPU stores data to be written into the third register at one time, the Nand Flash state machine circuit is specifically used for:
analyzing the command in the first register, writing data with the length being an integral multiple of a second preset length in data needing to be written in the Nand Flash in the third register into the DPRAM signal input and output circuit when the analyzed command is a write-in command, and sequentially writing the data with the second preset length in the data with the length being the integral multiple of the second preset length in the DPRAM signal input and output circuit into the Nand Flash by taking the third preset length as a unit; after the data with the second preset length is written into the Nand Flash, reading the redundant codes in the register set in the ECC generation module, and writing the redundant codes into the Nand Flash; continuing to perform the step of sequentially writing the next data with the second preset length in the data with the length being the integral multiple of the second preset length into the Nand Flash by taking the third preset length as a unit until all the data with the length being the integral multiple of the second preset length and the corresponding redundancy codes are written into the Nand Flash; and continuing to execute the step of writing the next data with the length being the integral multiple of the second preset length in the data needing to be written in the Nand Flash into the DPRAM signal input-output circuit until all the data needing to be written in the Nand Flash are written into the DPRAM signal input-output circuit.
The third preset length may be set by a user or may be set as a fixed value. For example, the user may set the third preset length to be 8bits or 16 bits.
When the CPU stores the data to be written into the third register in sequence by taking the first preset length as a unit, the NandFlash state machine circuit is specifically used for:
sequentially writing data needing to be written into the Nand Flash into a DPRAM signal input and output circuit by taking a first preset length as a unit, and sequentially writing the data needing to be written into the Nand Flash in the DPRAM signal input and output circuit into the Nand Flash by taking a third preset length as a unit; after the data with the second preset length is written into the Nand Flash, reading the redundant codes in the register set in the ECC generation module, and writing the redundant codes into the Nand Flash; and continuing to execute the step of sequentially writing the data needing to be written in the Nand Flash into the DPRAM signal input and output circuit by taking the first preset length as a unit until all the data needing to be written in the Nand Flash are written into the DPRAM signal input and output circuit.
When the Nand Flash state machine circuit writes the redundant code into the Nand Flash, the redundant code can be written into a position adjacent to the data with the second preset length in the Nand Flash.
The DPRAM signal input/output circuit is used for storing data written by the Nand Flash state machine circuit.
The ECC generation module comprises an encoding submodule and a register set.
The coding sub-module is used for coding and calculating the data needing to be written in the Nand Flash according to the pre-configured error correction capability to obtain a redundant code in the process that the Nand Flash state machine circuit writes the data needing to be written in the Nand Flash in the DPRAN signal input and output circuit into the Nand Flash, and storing the calculated redundant code into the register group.
The error correction capability may be set by a user or may be set as a fixed value. For example, the user may set the error correction capability to 512Bytes data to correct 4bits or 8bits or 15bits errors, or 1K Bytes data to correct 24bits or 40bits or 60bits errors, or of course, the error correction capability may be other values, which is not limited in the embodiment of the present invention.
For different error correction capabilities, the encoding circuits for performing the encoding operation are independent, and 512Bytes share one decoding circuit, and 1K Bytes share one decoding circuit.
And the register group is used for storing the redundant codes written in the coding submodule.
The coding submodule can sequentially carry out coding operation on data needing to be written into Nand Flash by taking a fourth preset length as a unit, and the data obtained by each coding operation is written into a register group; and continuing to perform coding calculation on the data with the length of the fourth preset length according to the data in the register group for the next time until the coding calculation on the data with the length of the second preset length is completed, wherein the data written into the register group is the redundant code of the data with the second preset length.
The fourth preset length may be set by a user or may be set as a fixed value. For example, the user may set the fourth preset length to be 16bits, and of course, the fourth preset length may also be another value, which is not limited in the embodiment of the present invention.
Optionally, the Nand Flash controller further includes a second register for accessing an address of the read data stored in the CPU.
The Nand Flash state machine circuit is further configured to:
when the command obtained by analysis is a reading command, sequentially reading data to be read and corresponding redundancy codes in Nand Flash by taking a third preset length as a unit according to the address in the second register, and writing the read data and the redundancy codes into the DPRAM signal input/output circuit until the data with the length being an integral multiple of the second preset length is written into the DPRAM signal input/output circuit; when a signal of completing correction of the coding submodule is received, a control system interface and an interrupt circuit generate an interrupt signal; when the CPU reads data from the third register, the corrected data in the DPRAM signal input/output circuit is written into the third register.
The ECC generation module also comprises a decoding submodule, and the decoding submodule is used for correcting the read data with the second preset length according to the redundant codes in the DPRAM signal input-output circuit and sending signals of completing correction to the Nand Flash state machine circuit.
The third preset length may be set by a user or may be set as a fixed value. For example, the user may set the third preset length to be 8bits or 16bits, and certainly, the third preset length may also take other values, which is not limited in the embodiment of the present invention.
And after detecting the interrupt signals generated by the system interface and the interrupt circuit, the CPU reads data from the third register.
Optionally, the Nand Flash state machine circuit is further configured to:
when the command obtained by analysis is a write-in command, controlling a decoding submodule in an ECC generation module to be in a non-working state; and when the command obtained by analysis is a read command, controlling the coding submodule in the ECC generation module to be in a non-working state.
The Nand Flash state machine circuit can control the decoding submodule to be in a non-working state by controlling the working clock of the decoding submodule, for example, the working clock of the decoding submodule is set to be at a low level, so that the decoding submodule is in the non-working state.
The Nand Flash state machine circuit can control the encoding submodule to be in a non-working state by controlling the working clock of the encoding submodule, for example, the working clock of the encoding submodule is set to be at a low level, so that the decoding submodule is in the non-working state.
As can be known by power consumption simulation of the Nand Flash controller, the transient peak power consumption of the Nand Flash controller is 1.76 watts (W), the average power consumption current is 60 milliamperes (mA), and the large power consumption of the Nand Flash controller is mainly generated during the working period of the ECC generation module, so that the Nand Flash state machine circuit in the embodiment of the invention controls the working states of the coding submodule and the decoding submodule to enable the coding submodule and the decoding submodule to work at different times, and the power consumption of the Nand Flash controller is reduced.
After the method is adopted, the power consumption of the Nand Flash controller is simulated again, the transient peak power consumption is reduced to 0.9W, and the average power consumption current is reduced to 40 mA.
Optionally, the number of the register groups is N, where N is an integer greater than or equal to 1.
The storage space of each group of registers may be configured according to actual requirements, which is not limited in the embodiment of the present invention. For example, when the number of the register groups is 6, the storage space of the first group of registers may be configured to be 52bits, the storage space of the second group of registers may be 52bits, the storage space of the third group of registers may be 91bits, the storage space of the fourth group of registers may be 141bits, the storage space of the fifth group of registers may be 224bits, and the storage space of the sixth group of registers may be 280 bits.
The Nand Flash state machine circuit is further configured to:
and when the command obtained by analysis is a write-in command, determining the number of the required register groups according to the pre-configured error correction capability, setting the required register groups to be in a working state, and setting other register groups to be in a non-working state.
For example, as shown in fig. 3, the operating state of the register set is controlled by a Multiplexer (MUX) circuit, the MUX circuit is actually an and circuit, when the parsed command is a write command, the encoding submodule is in an operating state, that is, the clock of the encoding submodule is an active clock, at this time, if the enable terminal of the register set is set, the register set is in an operating state, and if the enable terminal of the register set is not set, the register set is in a non-operating state.
In the method, different error correction capabilities are met by setting a plurality of register groups, and the power consumption of the Nand Flash controller is reduced by controlling the unnecessary register groups to be in a non-working state.
Optionally, when the CPU receives a setting instruction from a user, the CPU stores the setting instruction in the first register.
The Nand Flash state machine circuit is further configured to:
and when the command obtained by analysis is a setting instruction, setting corresponding parameters according to the setting instruction.
Wherein, the setting instruction comprises: the set parameters and the values of the parameters.
The set parameter may be any one or more of a first preset length, a second preset length, a third preset length, a length of data to be written, a fourth preset length, and an error correction capability.
For example, the length of the data to be written may be a length less than or equal to one page of Nand Flash, the first preset length may be 32 bits, and the second preset length may be 2bitsnThe third preset length may be 8bits or 16bits, the error correction capability may be 512Bytes data corrected 4bits or 8bits or 15bits errors, or 1K Bytes data corrected 24bits or 40bits or 60bits, and the fourth preset length may be 16 bits.
Of course, the above-mentioned value is only an example, and the embodiment of the present invention does not limit the specific value.
Referring to fig. 4, an embodiment of the present invention further provides a terminal, including:
any Nand Flash controller;
the terminal further includes:
nand Flash for storing data written by the CPU;
a CPU for storing the command in a first register; when the stored command is a write-in command, storing data needing to be written in the NandFlash into a third register; and when the stored command is a read command, storing the address of the read data into the second register.
Optionally, the CPU is further configured to:
and reading data from the third register after detecting the interrupt signals generated by the system interface and the interrupt circuit.
Optionally, the CPU is further configured to:
and receiving a setting instruction from a user, and storing the setting instruction into the first register.
Referring to fig. 5, an embodiment of the present invention further provides a method for controlling Nand Flash, including:
and 500, the CPU stores the write-in command into a first register of the Nand Flash controller, and stores data needing to be written into the Nand Flash into a third register of the Nand Flash controller.
In this step, the CPU may store the data to be written into the third register at one time, or may sequentially store the data to be written into the third register in units of a first preset length, so as to increase the writing rate.
The first preset length may be set by a user or may be set as a fixed value. For example, the user may set the first preset length to be 32 bits (bit), and of course, the first preset length may also be another value, which is not limited in this embodiment of the present invention.
502, a coding submodule of an ECC generation module of the Nand Flash controller performs coding operation on data needing to be written in the Nand Flash according to a pre-configured error correction capability to obtain a redundant code in the process that the Nand Flash state machine circuit writes the data needing to be written in the Nand Flash in the DPRAN signal input/output circuit into the Nand Flash, and stores the calculated redundant code into a register group of the ECC generation module.
Optionally, the method further includes:
the CPU stores the reading command into a first register of the Nand Flash controller and stores the address of the read data into a second register of the Nand Flash controller;
the Nand Flash state machine circuit analyzes the command in the first register, when the command obtained by analysis is a reading command, data needing to be read and corresponding redundant codes in the Nand Flash are sequentially read by taking a third preset length as a unit according to the address in the second register, and the read data and the redundant codes are written into the DPRAM signal input and output circuit until the data with the length being an integral multiple of the second preset length are written into the DPRAM signal input and output circuit;
a decoding submodule of an ECC generation module of the Nand Flash controller corrects the read data with the second preset length according to the redundant codes in the DPRAM signal input and output circuit and sends a corrected signal to a Nand Flash state machine circuit;
when the Nand Flash state machine circuit receives a signal of completing correction of the coding submodule, a control system interface and an interrupt circuit generate an interrupt signal;
after the CPU detects an interrupt signal generated by a system interface and an interrupt circuit of the Nand Flash controller, reading data from the third register;
when the CPU reads data from the third register, the Nand Flash state machine circuit writes the corrected data in the DPRAM signal input and output circuit into the third register.
Optionally, the method further includes:
when the command obtained by analyzing the Nand Flash state machine circuit is a write-in command, the Nand Flash state machine circuit controls a decoding submodule in the ECC generation module to be in a non-working state; and when the command obtained by analyzing the Nand Flash state machine circuit is a read command, the Nand Flash state machine circuit controls the coding sub-module in the ECC generation module to be in a non-working state.
Optionally, when the number of the register sets is greater than or equal to 2, the method further includes:
when the command obtained by the Nand Flash state machine circuit analysis is a write-in command, the Nand Flash state machine circuit determines the number of the required register groups according to the pre-configured error correction capability, sets the required register groups to be in a working state, and sets other register groups to be in a non-working state.
Optionally, the method further comprises:
when the CPU receives a setting instruction from a user, the CPU stores the setting instruction into a first register; and when the command obtained by analyzing the NandFlash state machine circuit is a setting instruction, setting corresponding parameters according to the setting instruction.
It should be noted that the above-mentioned embodiments are only for facilitating the understanding of those skilled in the art, and are not intended to limit the scope of the present invention, and any obvious substitutions, modifications, etc. made by those skilled in the art without departing from the inventive concept of the present invention are within the scope of the present invention.
Claims (13)
1. A Nand Flash controller of a Flash memory is characterized by comprising:
the first register is used for storing the stored command of the CPU;
the third register is used for storing data needing to be written into the Nand Flash;
the Nand Flash state machine circuit is used for analyzing the command in the first register, writing the data needing to be written in the Nand Flash in the third register into the DPRAM signal input and output circuit of the double-port random access memory when the analyzed command is a write-in command, and writing the data needing to be written in the Nand Flash in the DPRAM signal input and output circuit into the Nand Flash; after data with a second preset length is written into the Nand Flash each time, reading redundant codes in a register set in the ECC generation module, and writing the redundant codes into the Nand Flash;
the DPRAM signal input/output circuit is used for storing data written by the Nand Flash state machine circuit;
the ECC generation module comprises an encoding submodule and a register set;
the coding submodule is used for carrying out coding operation on the data needing to be written in the Nand Flash according to the pre-configured error correction capability to obtain a redundant code in the process that the Nand Flash state machine circuit writes the data needing to be written in the Nand Flash in the DPRAN signal input-output circuit into the Nand Flash, and storing the calculated redundant code into the register group;
the register group is used for storing redundant codes written in the coding sub-modules; the written redundant code is a redundant code of data with a second preset length.
2. The Nand Flash controller of claim 1, further comprising:
a second register for accessing an address of the CPU storing the read data;
the Nand Flash state machine circuit is further configured to:
when the command obtained by analysis is a read command, sequentially reading data to be read and corresponding redundant codes in Nand Flash by taking a third preset length as a unit according to the address in the second register, and writing the read data and the redundant codes into the DPRAM signal input/output circuit until the data with the length being an integral multiple of the second preset length is written into the DPRAM signal input/output circuit; when a signal of completing correction of the coding submodule is received, a control system interface and an interrupt circuit generate an interrupt signal; when the CPU reads data from the third register, the corrected data in the DPRAM signal input and output circuit is written into the third register;
the ECC generation module further comprises a decoding sub-module;
and the decoding submodule is used for correcting the read data with the second preset length according to the redundant codes in the DPRAM signal input-output circuit and sending a corrected signal to the Nand Flash state machine circuit.
3. The Nand Flash controller of claim 1 or 2, wherein the Nand Flash state machine circuit is further configured to:
when the command obtained by analysis is a write-in command, controlling a decoding submodule in the ECC generation module to be in a non-working state;
and when the command obtained by analysis is a read command, controlling the coding submodule in the ECC generation module to be in a non-working state.
4. The Nand Flash controller of claim 1 or 2, wherein the number of the register sets is N; n is an integer greater than or equal to 1;
the Nand Flash state machine circuit is further configured to:
and when the command obtained by analysis is a write-in command, determining the number of the required register groups according to the pre-configured error correction capability, setting the required register groups to be in a working state, and setting other register groups to be in a non-working state.
5. The Nand Flash controller of claim 1 or 2, wherein the Nand Flash state machine circuit is further configured to:
and when the command obtained by analysis is a setting instruction, setting corresponding parameters according to the setting instruction.
6. The Nand Flash controller of claim 1 or 2, wherein the Nand Flash state machine circuit is specifically configured to:
analyzing the command in the first register, when the command obtained by analyzing is a write-in command, writing data with the length being an integral multiple of a second preset length in data needing to be written in Nand Flash in the third register into the DPRAM signal input and output circuit, and sequentially writing data with the second preset length in data with the length being an integral multiple of the second preset length in the DPRAM signal input and output circuit into the Nand Flash by taking the third preset length as a unit;
after data with a second preset length is written into the Nand Flash, reading redundant codes in a register set in the ECC generation module, and writing the redundant codes into the Nand Flash;
continuing to perform the step of sequentially writing the next data with the second preset length in the data with the length being the integral multiple of the second preset length into the Nand Flash by taking the third preset length as a unit until all the data with the length being the integral multiple of the second preset length and the corresponding redundancy codes are written into the Nand Flash;
and continuing to execute the step of writing the next data with the length being the integral multiple of the second preset length in the data needing to be written in the Nand Flash into the DPRAM signal input-output circuit until all the data needing to be written in the Nand Flash are written into the DPRAM signal input-output circuit.
7. The Nand Flash controller of claim 1 or 2, wherein the Nand Flash state machine circuit is specifically configured to:
sequentially writing data needing to be written into the Nand Flash into a DPRAM signal input and output circuit by taking a first preset length as a unit, and sequentially writing the data needing to be written into the Nand Flash in the DPRAM signal input and output circuit into the Nand Flash by taking a third preset length as a unit;
after the data with the second preset length is written into the Nand Flash, reading the redundant codes in the register set in the ECC generation module, and writing the redundant codes into the Nand Flash;
and continuing to execute the step of sequentially writing the data needing to be written in the Nand Flash into the DPRAM signal input and output circuit by taking the first preset length as a unit until all the data needing to be written in the Nand Flash are written into the DPRAM signal input and output circuit.
8. The Nand Flash controller of claim 1 or 2, wherein the error correction capability comprises:
the 512Bytes of byte data correct 4bits or 8bits or 15bits errors, or the 1K Bytes of byte data correct 24bits or 40bits or 60bits errors.
9. A terminal, comprising: the Nand Flash controller of any one of claims 1 to 8;
further comprising:
nand Flash for storing data written by the CPU;
a CPU for storing the command in a first register; when the stored command is a write-in command, storing data needing to be written in the NandFlash into a third register; and when the stored command is a read command, storing the address of the read data into the second register.
10. The terminal of claim 9, wherein the CPU is further configured to:
and reading data from the third register after detecting the interrupt signals generated by the system interface and the interrupt circuit.
11. The terminal of claim 9, wherein the CPU is further configured to:
and receiving a setting instruction from a user, and storing the setting instruction into the first register.
12. A method for controlling Nand Flash of a Flash memory is characterized by comprising the following steps:
the CPU stores the write-in command into a first register of the Nand Flash controller, and stores data needing to be written into the Nand Flash into a third register of the Nand Flash controller;
the Nand Flash state machine circuit of the Nand Flash controller analyzes the command in the first register, when the command obtained by analysis is a write-in command, data needing to be written in the Nand Flash in the third register is written in a DPRAM signal input and output circuit of the dual-port random access memory, and the data needing to be written in the Nand Flash in the DPRAM signal input and output circuit is written in the Nand Flash; after data with a second preset length is written into the Nand Flash each time, reading redundant codes in a register set in the ECC generation module, and writing the redundant codes into the Nand Flash;
in the process that a coding submodule of an ECC (error correction code) generation module of a Nand Flash controller writes data needing to be written into the Nand Flash in a DPRAN (digital data radio Access network) signal input/output circuit into the Nand Flash, coding operation is carried out on the data needing to be written into the Nand Flash according to the pre-configured error correction capability to obtain a redundancy code, and the calculated redundancy code is stored in a register bank of the ECC generation module; the written redundant code is a redundant code of data with a second preset length.
13. The method of claim 12, further comprising:
the CPU stores the reading command into a first register of the Nand Flash controller and stores the address of the read data into a second register of the Nand Flash controller;
the Nand Flash state machine circuit analyzes the command in the first register, when the command obtained by analysis is a reading command, data needing to be read and corresponding redundant codes in the Nand Flash are sequentially read by taking a third preset length as a unit according to the address in the second register, and the read data and the redundant codes are written into the DPRAM signal input and output circuit until the data with the length being an integral multiple of the second preset length are written into the DPRAM signal input and output circuit;
a decoding submodule of an ECC generation module of the Nand Flash controller corrects the read data with the second preset length according to the redundant codes in the DPRAM signal input and output circuit and sends a corrected signal to a Nand Flash state machine circuit;
when the Nand Flash state machine circuit receives a signal of completing correction of the coding submodule, a control system interface and an interrupt circuit generate an interrupt signal;
after the CPU detects an interrupt signal generated by a system interface and an interrupt circuit of the Nand Flash controller, reading data from the third register;
when the CPU reads data from the third register, the Nand Flash state machine circuit writes the corrected data in the DPRAM signal input and output circuit into the third register.
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| CN109656845A (en) * | 2018-12-06 | 2019-04-19 | 天津津航计算技术研究所 | ECC storage controlling method with data debugging function |
| CN109814888B (en) * | 2019-01-25 | 2022-06-07 | 深圳忆联信息系统有限公司 | NandFlash controller EFUSE replacing method and device |
| CN111813591B (en) * | 2020-07-03 | 2023-12-29 | 深圳市国微电子有限公司 | Data error correction method and device of Nand Flash, electronic equipment and storage medium |
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