CN105161137A - Nand Flash controller circuit implementation apparatus in MLC framework - Google Patents

Nand Flash controller circuit implementation apparatus in MLC framework Download PDF

Info

Publication number
CN105161137A
CN105161137A CN201510536361.2A CN201510536361A CN105161137A CN 105161137 A CN105161137 A CN 105161137A CN 201510536361 A CN201510536361 A CN 201510536361A CN 105161137 A CN105161137 A CN 105161137A
Authority
CN
China
Prior art keywords
module
ecc
nandflash
data
mlc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201510536361.2A
Other languages
Chinese (zh)
Other versions
CN105161137B (en
Inventor
韩晓晶
赵红敏
龚宗跃
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Datang Microelectronics Technology Co Ltd
Datang Semiconductor Design Co Ltd
Original Assignee
Datang Microelectronics Technology Co Ltd
Datang Semiconductor Design Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Datang Microelectronics Technology Co Ltd, Datang Semiconductor Design Co Ltd filed Critical Datang Microelectronics Technology Co Ltd
Priority to CN201510536361.2A priority Critical patent/CN105161137B/en
Publication of CN105161137A publication Critical patent/CN105161137A/en
Application granted granted Critical
Publication of CN105161137B publication Critical patent/CN105161137B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

The present invention discloses a Nand Flash controller circuit implementation apparatus in an MLC framework. An error checking and correcting ECC module equipped with error-correcting capability is embedded in the NFC. The ECC module comprises a ECC_Enc_Sx module, a DeCodeBM module, a DeCodeChien module, a DeCodeCor module and an ECC_Flow_Ctrl module, wherein the ECC_Enc_Sx module is used for performing coding on the received data to obtain a code word and calculating a syndrome according to a received systematic code; the DeCodeBM module is used for solving a pivotal equation according to the syndrome and obtaining an error location polynomial according to the pivotal equation; the DeCodeChien module is used for determining an error location according to the error location polynomial; the DeCodeCor module is used for correcting the corresponding data according to the error location; and the ECC_Flow_Ctrl module is used for controlling other modules. According to the Nand Flash controller circuit implementation apparatus in the MLC framework provided by the present invention, a high-performance and high-compatibility ECC design of Nand Flash controller in the MLC framework is realized.

Description

Nand Flash controller circuitry implement device in a kind of MLC framework
Technical field
The present invention relates to technical field of integrated circuits, hire Large Copacity nonvolatile memory (NandFlash) controller circuitry implement device in (MLC, MultiLevelCell) framework for espespecially a kind of multi-level point.
Background technology
NandFlash has non-volatile, erasability, less chip area, faster write and erasing speed and cheaper every bit price with it, obtains and use widely in the mass-memory unit such as mobile phone, mobile memory card.Due to factors such as the feature of NandFlash structure and noise thereof, when data are stored on NandFlash, the reversion of indivedual bits may be produced, thus cause storing corrupt data.In MLC framework, NandFlash stores by every Cell the leap at double that more bits realizes on capacity, the trend of NandFlash of new generation, but because the space between adjacent data voltage diminishes, the probability of makeing mistakes of MLC framework NandFlash is larger, and once there is mistake, 2 times and above corrupted data will be caused.Therefore in order to can Error detection and correction be carried out when ensureing data reading, usually be all when data write storage unit, need to write a part of redundant data artificially by certain rule, bug check and correction (ECC, ErrorCodeCorrection) Error Control is carried out with error correcting code circuitry.In view of the widespread use of NandFlash, recent domestic to the research of NandFlash controller and design all carry out like a raging fire.
The existing codec for NandFlash controller, its error correcting capability is fixing, is generally 4bit or 8bit, and its advantage is that specificity is good, area is little, is applicable to the NandFlash that existing redundant space is 16bytes/512bytes or 128bytes/4Kbytes.Due to the progress of technique, the reduction of live width, NandFlash storage density is more and more higher, error probability is also increasing, therefore the redundant space in NandFlash of new generation has brought up to 218bytes/4Kbytes, so just make NandFlash controller can adopt the error correcting code of entangling more bits mistakes, reduce the error rate of NandFlash, and the existing ECC that only can correct 4bit or 8bit mistake can not meet the requirements of far away; On the other hand, the existing demoder that can entangle 15bit or below 24bit, due to its not configurability, verification bits length is made to fix and be greater than 16bytes, can only be used for the NandFlash of MLC type of new generation, can not be applied to common NandFlash, its downward compatibility is bad.
In addition, there is following defect in the domestic and international research about NandFlash controller circuitry and design at present:
The first, poor compatibility, this is because the ECC circuit in the NandFlash controller of the overwhelming majority is all design based on some concrete application systems or certain a concrete NandFlash;
The second, data rate is slow, and this mainly refers to that those adopt softwares to be the ECC circuit that Software-only method realizes of advocating peace;
3rd, data reliability is poor, and some NandFlash controller does not have data check function, or ECC checking feature is lower;
4th, area is large, and power consumption is high, and this does not note again reducing power consumption mainly because the design of a lot of ECC employs a large amount of registers to pursue function simultaneously.
Summary of the invention
In order to solve the problems of the technologies described above, the invention provides NandFlash controller circuitry implement device in a kind of MLC framework, the high-performance of NandFlash controller in MLC framework and the ECC design of highly compatible can be realized.
In order to reach the object of the invention, the invention provides NandFlash controller circuitry implement device in a kind of MLC framework, described NandFlash controller NFC and NandFlash and two-way programmable storage Dpram carries out exchanges data, the bug check that in NFC, embedded error correcting capability can be joined and correction ECC module; Described ECC module comprises ECC_Enc_Sx module, DeCodeBM module, DeCodeChien module, DeCodeCor module and ECC_Flow_Ctrl module, wherein,
ECC_Enc_Sx module, tries to achieve code word for carrying out coding to the data received, and calculates syndrome according to the systematic code received; DeCodeBM module, for solving key equation according to syndrome, and tries to achieve error location polynomial according to key equation; DeCodeChien module, for according to error location polynomial, determines errors present; DeCodeCor module, for according to errors present, carries out the error correction of corresponding data; ECC_Flow_Ctrl module, for control ECC_Enc_Sx module, DeCodeBM module, DeCodeChien module and DeCodeCor module.
Compared with prior art, ECC circuit of the present invention is embedded in NandFlash controller, and the verification achieved in the transmission of NandFlash data controls, and ECC error correction figure place can be joined, can support at most to entangle 12bit mistake for 512Byte data block, 1Kbyte data block can entangle 40bit mistake at most.Thus, by adopting software and hardware combining, a transmission speed of the conceptual design based on hardware is fast, and by force compatible, reliability is high, the NandFlash controller circuitry with ECC data error correction for MLC framework NandFlash that error correcting capability is strong.
Other features and advantages of the present invention will be set forth in the following description, and, partly become apparent from instructions, or understand by implementing the present invention.Object of the present invention and other advantages realize by structure specifically noted in instructions, claims and accompanying drawing and obtain.
Accompanying drawing explanation
Accompanying drawing is used to provide the further understanding to technical solution of the present invention, and forms a part for instructions, is used from and explains technical scheme of the present invention, do not form the restriction to technical solution of the present invention with the embodiment one of the application.
Fig. 1 is the structural representation of NandFlash in MLC framework in a kind of embodiment of the present invention.
Fig. 2 is the schematic diagram of NandFlash controller circuitry implement device in MLC framework in a kind of embodiment of the present invention.
Fig. 3 is the schematic diagram of ECC module in a kind of embodiment of the present invention.
Fig. 4 is the schematic diagram of the circuit realiration of ECC_Enc_Sx module in ECC module in Fig. 3.
Fig. 5 is the schematic diagram of the circuit realiration of DeCodeBM module in ECC module in Fig. 3.
Fig. 6 is the schematic diagram of the circuit realiration of DeCodeChien module and DeCodeCor module in ECC module in Fig. 3.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly understand, hereinafter will be described in detail to embodiments of the invention by reference to the accompanying drawings.It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combination in any mutually.
Can perform in the computer system of such as one group of computer executable instructions in the step shown in the process flow diagram of accompanying drawing.Further, although show logical order in flow charts, in some cases, can be different from the step shown or described by order execution herein.
Different vendor can supply for a long time, process stabilizing and the NandFlash of the MLC framework of volume production needed for the figure place of ECC error correction be not quite similar, for Samsung and Micron Technology, table 1 describes the amount of capacity of these two products, error correction requirement, page size (Pagesize) and redundancy size (Sparesize).In the space in capacity (Spare) district, a part is to file system use, and another part is for storing check bit.Therefore design configurable ECC according to the requirement of different NandFlash error correcting capabilities and entangle decoder module, there is important Research Significance.
Table 1
For the difference of the redundant space of current NandFlash, the present invention proposes the configurable ECC circuit implementation of one of compatible different N andFlash.
Fig. 1 is NandFlash interface diagram, and wherein AHBBUS is AdvancedHigh-performanceBus agreement, in address with between control signal and data, has the bus protocol of permanent order; DMA is direct memory access; Parctl is that register controls; Intctl controls for interrupting; P is port controlling; Fsm is state machine.
As shown in Figure 1, NandFlash controller (NFC) carries out exchanges data with Large Copacity nonvolatile memory (NandFlash) and two-way programmable storage (Dpram), and the ECC module that error correcting capability can be joined is embedded in NFC.Wherein, need certain interface sequence owing to will access NandFlash, NFC achieves the controller can accessing NandFlash; NandFlash is jumbo data-carrier store, will conduct interviews to it, mainly does the transmission of jumbo data; Dpram is used as buffer memory, stores the data needing to write Nandflash, needs the data writing nandflash to take out of from dpram chip by NFC interface, then according in the sequential write nandflash of nandflash requirement.The mode that the data exchange ways of NFC and NandFlash and Dpram uses according to different chip is different, such as, use the ram etc. of buffer, single port ram, twoport.In specific embodiments of the invention, in order to make efficiency higher, use twoport ram.
Likely can make mistakes, so NFC needs ECC error correction circuit because NandFlash writes data.When data pass on NandFlash data line, also entering ECC module carries out data encoding, DTD simultaneously, and ECC has encoded simultaneously, now transmits code word on the data line and writes together in NandFlash.Read data is also similar, as data write Dpram, also passes to ECC module simultaneously, carries out decoding computing.The control of these operations is controlled by NFC module state machine.
Fig. 2 is the structural representation of NandFlash controller.As shown in Figure 2, NandFlash controller comprises: control signal output register, system interface circuit, NFC module work register group, NFC module state machine, control signal decoder, Dpram control signal and data input/output register, NandFlash control signal and data input/output register and ECC module, wherein, NandFlash controller, for responsible parsing from the data of bus end and order, and require to send order and data to target NandFlash device according to the interface sequence of NandFlash; Register configuration module realizes the configuration feature to register all kinds of in NandFlash controller; Input into/output from cache is used for the data of buffer memory dealing NandFlash, the speed of balance ECC coder and bus.
System interface circuit, is used for the read and write access of completion system bus to NFC module work register, and produces corresponding ack signal.
Dpram control signal and data input/output register, for the control signal of Dpram and the input and output of data, the output of this group signal is register and exports.
NandFlash control signal and data input/output register, for exporting the control signal of NandFlash and providing the data that will write NandFlash, the output of this group and control signal are register and export, and input signal exports to NFC module state machine by a falling edge detectors.
NFC module state machine, for detecting the BUSY/READY state of NandFlash, to determine whether continue corresponding operation.Particularly, after NandFlash receives orders according to sequential, corresponding wiping can be done, the operations such as write-read, operation can provide BUSY signal when starting, after operation terminates, this signal becomes READY, and this signal feeds NFC by BUSY/READY, and NFC can decide the redirect of NFC state machine according to BUSY/READY signal.
Control signal output register, for resolving the clock signal realizing NandFlash, is mainly used in realizing and the process of the mutual port information of NandFlash.
NFC module work register group, for configuring enabling of NFC, interrupts enable signal of Denging.
Control signal decoder, for giving ECC module after the information analysis after the NFC module work register group in system configuration, and to NFC module work register group after the decoding of information such as state ECC module produced, for CPU inquiry etc.
ECC module is an independently module.In a particular embodiment of the present invention, this ECC module verifies error correction for the ECC calculating 512bytes or 1Kbytes, does not do other and judges.The startup of ECC module and stopping are by software design patterns, and in bus, whether data effectively need NFC module state machine to indicate equally simultaneously.The ECC coding that this ECC module finally generates exports to NFC module work register group by control signal decoder, for CPU process and access.The ECC comparison of taking out during read data and in NandFlash realizes error correction, has often inputted the data of 512bytes or 1Kbytes when write, and CPU reads an ECC value and inserted in Dpram corresponding to the corresponding data position of NandFlash.
As shown in Figure 3, ECC module comprises ECC_Enc_Sx module, DeCodeBM module, DeCodeChien module, DeCodeCor module and ECC_Flow_Ctrl module, wherein,
ECC_Enc_Sx module, try to achieve code word for carrying out coding to the data received, and calculate syndrome by the systematic code R (x) received, syndrome is also known as syndrome S (x);
DeCodeBM module, for solving key equation according to syndrome S (x), and tries to achieve error location polynomial σ (x) and improper value polynomial expression ω (x) according to key equation;
DeCodeChien module, for according to error location polynomial σ (x) and improper value polynomial expression ω (x), adopts money searching algorithm to try to achieve errors present;
DeCodeCor module, for carrying out the error correction of corresponding bit according to errors present;
ECC_Flow_Ctrl module, for controlling the duty of whole circuit.
Particularly, the circuit realiration of ECC_Enc_Sx module as shown in Figure 4.
By ECC_Enc_Sx module, coding is carried out to the data received and try to achieve code word, as shown in Figure 4, initial value is full 0, input 16 bit data nfc_ecc_data [15:0], often carry out one group of data, value in register once upgrades through combinational logic, and the data value write in late register is the code word of trying to achieve.
Solve syndrome process and be divided into two steps: the first step, complementation formula (RCDiv ψ i); Second step, substitutes into evaluation (RCEval (α i)), α i is taken in residue si (x), can try to achieve final syndrome.Detailed solution process is known to those skilled in the art, therefore repeats no more.To sum up, the circuit of ECC_Enc_Sx module is formed by with door and XOR gate, is required for model selection with door, and XOR is then the additive operation of field element.
Particularly, the circuit realiration of DeCodeBM module as shown in Figure 5.
Table 2 is the resources required for BM iterative algorithm.
Table 2
According to table 2, solve error location polynomial part and adopt the BM iterative algorithm (SiBM) of not inverting simplified.Trading off according to Area and Speed, in a particular embodiment of the present invention, selects 9 processing units (PE) and 49 registers to realize.Form the SiBM pe array of 9, each PE comprises three finite field multipliers and a Galois field addition, also has a m position MUX.SiBM algorithm, when the r time iteration, in SiBM.1, the renewal of i-th coefficient can calculate with the renewal of the i-th+1 coefficient in SiBM.2 simultaneously, and SiBM algorithm structure is even, and resource multiplex rate on hardware implementing of need not inverting is higher.
DeCodeChien modular circuit realizes as shown in Figure 6.
Particularly, error location polynomial σ (x)=1+ σ is calculated by BM iterative algorithm 1x+ σ 2x 2+ ... + σ tx t, chien search algorithm then can be utilized to obtain root of polynomial X, and root is the inverse of errors present.Chien search algorithm essence is a kind of method trying root.Because galois field GF is a Galois field, its territory interior element number is limited, is 2 14-1 (N), therefore can attempt all possible X=α 1, α 2, α 3. α nin substitution formula, after corresponding i bit strip enters polynomial expression, its value is 0, so just have found corresponding errors present 2 14-1-i.
In a particular embodiment of the present invention, money search circuit adopts four bit parallels to search root, the highest error correcting capability t=40 of this money search circuit, therefore error location polynomial is:
σ(x)＝σ 40x 40+σ 39x 39+...σ 23x 23+σ 22x 22+σ 21x 21+σ 20x 20+σ 19x 19+σ 18x 18+σ 17x 17+σ 16x 16+σ 15x 15+σ 14x 14+σ 13x 13+σ 12x 12+σ 11x 11+σ 10x 10+σ 9x 9+σ 8x 8+σ 7x 7+σ 6x 6+σ 5x 5+σ 4x 4+σ 3x 3+σ 2x 2+σ 1x+1。
By x=α isubstitute into error location polynomial σ (x):
σ(α i)＝σ 40(α i) 40+σ 39(α i) 39+...σ 24(α i) 24+σ 23(α i) 23+σ 22(α i) 22+σ 21(α i) 21+σ 20(α i) 20+σ 19(α i) 19+σ 18(α i) 18+σ 17(α i) 17+σ 16(α i) 16+σ 15(α i) 15+σ 14(α i) 14+σ 13(α i) 13+σ 12(α i) 12+σ 11(α i) 11+σ 10(α i) 10+σ 9(α i) 9+σ 8(α i) 8+σ 7(α i) 7+σ 6(α i) 6+σ 5(α i) 5+σ 4(α i) 4+σ 3(α i) 3+σ 2(α i) 2+σ 1α i+1。
By x=α i+1substitute into error location polynomial σ (x):
σ(α i+1)＝σ 40(α i) 40+σ 39(α i) 39+...σ 24(α i+1) 24+σ 23(α i+1) 23+σ 22(α i+1) 22+σ 21(α i+1) 21+σ 20(α i+1) 20+σ 19(α i+1) 19+σ 18(α i+1) 18+σ 17(α i+1) 17+σ 16(α i+1) 16+σ 15(α i+1) 15+σ 14(α i+1) 14+σ 13(α i+1) 13+σ 12(α i+1) 12+σ 11(α i+1) 11+σ 10(α i+1) 10+σ 9(α i+1) 9+σ 8(α i+1) 8+σ 7(α i+1) 7+σ 6(α i+1) 6+σ 5(α i+1) 5+σ 4(α i+1) 4+σ 3(α i+1) 3+σ 2(α i+1) 2+σ 1α i+1+1；
＝σ 40(α i) 40α 40+σ 39(α i) 39α 39+...σ 24(α i) 24α 24+σ 23(α i) 23α 23+σ 22(α i) 22α 22+σ 21(α i) 21α 21+σ 20(α i) 20α 20+σ 19(α i) 19α 19+σ 18(α i) 18α1 8+σ 17(α i) 17α 17+σ 16(α i) 16α 16+σ 15(α i) 15α 15+σ 14(α i) 14α 14+σ 13(α i) 13α 13+σ 12(α i) 12α 12+σ 11(α i) 11α 11+σ 10(α i) 10α 10+σ 9(α i) 9α 9+σ 8(α i) 8α 8+σ 7(α i) 7α 7+σ 6(α i) 6α 6+σ 5(α i) 5α 5+σ 4(α i) 4α 4+σ 3(α i) 3α 3+σ 2(α i) 2α 2+σ 1(α i)α+1。
Drawn by above-mentioned derivation, σ (α i+1) every be σ (α i) corresponding entry be multiplied by a known element-specific, σ (α i+1) n-th be σ (α i) n-th be multiplied by α n(n is integer), that is:
σ (α i+1) the 40 be σ (α i) the 40 be multiplied by α 40;
σ (α i+1) the 39 be σ (α i) the 39 be multiplied by α 39;
……
σ (α i+1) Section 24 be σ (α i) Section 24 be multiplied by α 24;
σ (α i+1) Section 23 be σ (α i) Section 23 be multiplied by α 23;
……
σ (α i+1) Section 2 be σ (α i) Section 2 be multiplied by α 2;
σ (α i+1) Section 1 be σ (α i) Section 1 be multiplied by α.
Therefore, utilize field element multiplication, error location polynomial and some field elements, just can calculate the search situation of this field element each element later, with this, money search is divided into some groups of parallel computations.
Due to the present invention's employing is BCH shorten code (one of ECC algorithm), some is 0 all the time, can not make mistakes, so before carrying out money search, first to carry out pre-service, namely need to be multiplied by α to the coefficient of error location polynomial after BM iteration (16381-14t-4096) * i(data of 512bytes), or α (16381-14t-8192) * i(data of 1kbytes), so can save the time of searching 0.
Like this, first DeCodeChien module carries out initialization to the error location polynomial coefficient lambda that BM provides, error correction mode of the present invention is configurable, mainly comprises following 2 kinds of pattern: 512byte and entangles mistake within 12bit, and 1024byte entangles mistake within 40bit, ecc_mode value 0 or 1 is set by register configuration and selects different patterns, if such as ecc_mode=1, error correction t=12, namely entangles mistake within 12bit, need search 4264 bit information altogether, need 1066 clk to complete search.If ecc_mode=0, error correction t=40, namely entangle mistake within 40bit, need search 8752 altogether, need 2188 clk to complete search.After finding mistake, corrected by DeCodeCor module.Owing to being 2 binary data, if made mistakes, directly error correction can be completed to its negate.
In the present invention, by the correctness of Matlab verification algorithm, utilize ModelSim to verify wave simulation, ensure the correctness of algorithm and sequential.The present invention is in test process, and done 1,000,000 groups of tests by ModelSim, error in data number is traveled through by 0-50, and errors present is random, and the result is all correct.
In a particular embodiment of the present invention, NandFlash control circuit with BCH codec can adopt the technique flow of Huahong 0.13 μm, successively through FPGA and board level test, adopting Flash chip to be the K9GBG08U0B of Samsung, K9G4G08X0B test speed is 10MB/s.Through actual measurement, for K9G4G08X0B, take 512byte as data cell, when mistake can normally error correction in 12bit, for K9GBG08U0B, take 1kbyte as data cell, when mistake can normally error correction in 40bit, for above-mentioned 2 sections of FLASH, can ensure that data correctly communicate in normal read-write situation.Mistake exceedes error correcting capability, can be reported an error by register.To sum up, the controller circuitry error correcting capability that the present invention realizes can be joined, and function is correct.
The existing codec for NandFlash controller, its error correcting capability is fixing, be generally 4bit or 8bit, its advantage is that specificity is good, area is little, is applicable to the NandFlash that existing redundant space (sparearea) is 16bytes/512bytes or 128bytes/4Kbytes.On the other hand, the existing demoder that can entangle 15bit or below 24bit, due to its not configurability, verification bits length is made to fix and be greater than 16bytes, can only be used for the NandFlash of MLC type of new generation, can not be applied to common NandFlash, its downward compatibility is bad.Relative to prior art, invention has been the improvement of 3 at least below:
(1) error correcting capability is configurable, and coding is real-time.
The ECC circuit that the present invention proposes has the configurable feature of error correcting capability, and error correcting capability is the 40bits mistake of correcting stochastic distribution in the 12bits mistake of stochastic distribution in 512bytes data and 1Kbytes data respectively.The coding that the present invention proposes and ask syndrome circuit to be 16 bit parallels, no matter be the NandFlash of 8 for interface bit wide, or interface bit wide is the NandFlash of 16, when data are write NandFlash, encode to it, the write operation finally achieved with NandFlash carries out real-time data encoding circuit simultaneously.
(2) money search circuit is optimized
The money search adopted when solving bit-error locations is a process of entirely searching for, and calculated amount during big data quantity verification decoding is larger.Money search is the bottleneck of verification speed, and in order to improve verification speed, the present invention, by being optimized money search, adopting grouping parallel to search for, search speed improved 4 times in the areal extent allowed.
(3) BM iteration module adopts SiBM algorithm, and hardware resource is multiplexing, saves area.
When solving errors present equation, adopt SiBM algorithm, this algorithm does not have inversion operation, and circuit structure is even, and hardware can resource multiplex, thus saving circuit area, this is the innovative point realizing BCH algorithm, present invention employs this SiBM algorithm, but is optimized it, and can be multiplexing with some arithmetic elements of money search circuit module, can saving chip area.
In the present invention, ECC circuit is embedded in NandFlash controller, the verification achieved in the transmission of NandFlash data controls, ECC error correction figure place can be joined, and can support at most to entangle 12bit mistake for 512Byte data block, 1Kbyte data block can entangle 40bit mistake at most.Thus, by adopting software and hardware combining, a transmission speed of the conceptual design based on hardware is fast, and by force compatible, reliability is high, the NandFlash controller circuitry with ECC data error correction for MLC framework NandFlash that error correcting capability is strong.
Although the embodiment disclosed by the present invention is as above, the embodiment that described content only adopts for ease of understanding the present invention, and be not used to limit the present invention.Those of skill in the art belonging to any the present invention; under the prerequisite not departing from the spirit and scope disclosed by the present invention; any amendment and change can be carried out in the form implemented and details; but scope of patent protection of the present invention, the scope that still must define with appending claims is as the criterion.

Claims (10)

1. one kind is divided Large Copacity nonvolatile memory NandFlash controller circuitry implement device in servant MLC framework at many levels, it is characterized in that, described NandFlash controller NFC and NandFlash and two-way programmable storage Dpram carries out exchanges data, the bug check that in NFC, embedded error correcting capability can be joined and correction ECC module;
Described ECC module comprises ECC_Enc_Sx module, DeCodeBM module, DeCodeChien module, DeCodeCor module and ECC_Flow_Ctrl module, wherein,
ECC_Enc_Sx module, tries to achieve code word for carrying out coding to the data received, and calculates syndrome according to the systematic code received;
DeCodeBM module, for solving key equation according to syndrome, and tries to achieve error location polynomial according to key equation;
DeCodeChien module, for according to error location polynomial, determines errors present;
DeCodeCor module, for according to errors present, carries out the error correction of corresponding data;
ECC_Flow_Ctrl module, for control ECC_Enc_Sx module, DeCodeBM module, DeCodeChien module and DeCodeCor module.
2. NandFlash controller circuitry implement device in MLC framework according to claim 1, is characterized in that, described ECC_Enc_Sx module is carried out coding to the data received and tried to achieve code word, is specially:
Initial value is full 0, inputs 16 bit data nfc_ecc_data [15:0]; Often carry out one group of data, the value in register once upgrades through combinational logic, and the data value write in late register is the code word of trying to achieve.
3. NandFlash controller circuitry implement device in MLC framework according to claim 1, it is characterized in that, described DeCodeBM module comprises the SiBM pe array that 9 processing unit PE and 49 registers are formed, wherein each PE comprises 3 finite field multipliers, 1 Galois field addition, and 1 m position MUX.
4. NandFlash controller circuitry implement device in MLC framework according to claim 3, it is characterized in that, described DeCodeBM module adopts the BM iterative algorithm SiBM do not inverted, solve key equation according to syndrome S (x), and try to achieve error location polynomial σ (x) and improper value polynomial expression ω (x) according to key equation;
Described SiBM algorithm, is specially:
When the r time iteration, the renewal of the i-th+1 coefficient in SiBM.N in the renewal of i-th coefficient and SiBM.N+1 calculates simultaneously, and in 1 SiBM processing unit, PE upgrades simultaneously i-th coefficient and the i-th+1 coefficient.
5. NandFlash controller circuitry implement device in MLC framework according to claim 1, is characterized in that, described DeCodeChien module, according to error location polynomial, is determined errors present, is specially:
Described DeCodeChien module utilizes chien search algorithm to obtain the root x of error location polynomial σ (x), and x is the inverse of errors present.
6. NandFlash controller circuitry implement device in MLC framework according to claim 5, is characterized in that, utilizes chien search algorithm to obtain the root x of error location polynomial σ (x), is specially:
Adopt chien search algorithm to territory interior element examination root, the number of territory interior element is 2 14-1 (N), by the root x=α of territory interior element 1, α 2, α 3.... α nsubstitute into the error location polynomial of chien search algorithm, after i-th root brings error location polynomial into, value is 0, then determine that corresponding errors present is 2 14-1-i.
7. NandFlash controller circuitry implement device in MLC framework according to claim 5, is characterized in that, the error location polynomial of described chien search algorithm is:
σ(x)＝σ 24x 24+σ 23x 23+σ 22x 22+σ 21x 21+σ 20x 20+σ 19x 19+σ 18x 18+σ 17x 17+σ 16x 16
+σ 15x 15+σ 14x 14+σ 13x 13+σ 12x 12+σ 11x 11+σ 10x 10+σ 9x 9+σ 8x 8+σ 7x 7
+σ 6x 6+σ 5x 5+σ 4x 4+σ 3x 3+σ 2x 2+σ 1x+1。
8. NandFlash controller circuitry implement device in MLC framework according to claim 7, is characterized in that, the root of described territory interior element is α iand α i+1time the pass of error location polynomial be:
σ (α i+1) n-th be σ (α i) n-th be multiplied by α n, n is integer;
Described DeCodeChien module is according to α iand α i+1time the relation of error location polynomial, calculate the search situation after territory interior element n-th, and territory interior element grouping parallel calculated.
9. NandFlash controller circuitry implement device in MLC framework according to claim 8, it is characterized in that, the coefficient of error location polynomial, after the error location polynomial solved, for the data of 512bytes, is multiplied by α by described DeCodeChien module (16381-14t-4096) * i; For the data of 1kbytes, the coefficient of error location polynomial is multiplied by α (16381-14t-8192) * i.
10. NandFlash controller circuitry implement device in MLC framework according to claim 1, it is characterized in that, described device also comprises: control signal output register, system interface circuit, NFC module work register group, NFC module state machine, control signal decoder, Dpram control signal and data input/output register and NandFlash control signal and data input/output register, wherein
System interface circuit, is used for the read and write access of completion system bus to NFC module work register, and produces corresponding ack signal;
Dpram control signal and data input/output register, for the control signal of Dpram and the input and output of data;
NandFlash control signal and data input/output register, for exporting the control signal of NandFlash and providing the data that will write NandFlash, input signal exports to NFC module state machine by a falling edge detectors;
NFC module state machine, for detecting the BUSY/READY state of NandFlash, and feeds back to NFC;
Control signal output register, for resolving the clock signal realizing NandFlash;
NFC module work register group, for configuring enabling of NFC, interrupts enable signal;
Control signal decoder, for giving ECC module after the information analysis after the NFC module work register group in system configuration, and to NFC module work register group after decoding of information ECC module produced.
CN201510536361.2A 2015-08-27 2015-08-27 Nand Flash controller circuitry realization device in a kind of MLC architecture Active CN105161137B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510536361.2A CN105161137B (en) 2015-08-27 2015-08-27 Nand Flash controller circuitry realization device in a kind of MLC architecture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510536361.2A CN105161137B (en) 2015-08-27 2015-08-27 Nand Flash controller circuitry realization device in a kind of MLC architecture

Publications (2)

Publication Number Publication Date
CN105161137A true CN105161137A (en) 2015-12-16
CN105161137B CN105161137B (en) 2019-04-19

Family

ID=54801965

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510536361.2A Active CN105161137B (en) 2015-08-27 2015-08-27 Nand Flash controller circuitry realization device in a kind of MLC architecture

Country Status (1)

Country Link
CN (1) CN105161137B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106776104A (en) * 2016-11-11 2017-05-31 大唐微电子技术有限公司 A kind of method of Nand Flash controllers and terminal and control Nand Flash
CN107102953A (en) * 2016-12-14 2017-08-29 威盛电子股份有限公司 Non-volatile memory device and its iterative sequencing method
CN110688249A (en) * 2019-09-20 2020-01-14 上海励驰半导体有限公司 Error injection detection circuit of error correction code circuit
CN112199308A (en) * 2020-11-26 2021-01-08 浙江大学 Low-power-consumption storage controller for special power chip and control method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101211667A (en) * 2006-12-29 2008-07-02 三星电子株式会社 Error correction circuit and method for reducing miscorrection probability and memory device including the circuit
CN101483442A (en) * 2009-02-11 2009-07-15 芯原微电子(上海)有限公司 BCH decoder for configuring error correcting capability according to Nand Flash extra space
US20110161774A1 (en) * 2009-12-24 2011-06-30 Hynix Semiconductor Inc. Semiconductor memory system having ecc circuit and method of controlling thereof
CN102969028A (en) * 2012-10-18 2013-03-13 记忆科技(深圳)有限公司 Method, system, and flash memory of ECC dynamic adjustment

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101211667A (en) * 2006-12-29 2008-07-02 三星电子株式会社 Error correction circuit and method for reducing miscorrection probability and memory device including the circuit
CN101483442A (en) * 2009-02-11 2009-07-15 芯原微电子(上海)有限公司 BCH decoder for configuring error correcting capability according to Nand Flash extra space
US20110161774A1 (en) * 2009-12-24 2011-06-30 Hynix Semiconductor Inc. Semiconductor memory system having ecc circuit and method of controlling thereof
CN102969028A (en) * 2012-10-18 2013-03-13 记忆科技(深圳)有限公司 Method, system, and flash memory of ECC dynamic adjustment

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106776104A (en) * 2016-11-11 2017-05-31 大唐微电子技术有限公司 A kind of method of Nand Flash controllers and terminal and control Nand Flash
CN107102953A (en) * 2016-12-14 2017-08-29 威盛电子股份有限公司 Non-volatile memory device and its iterative sequencing method
US10824554B2 (en) 2016-12-14 2020-11-03 Via Technologies, Inc. Method and apparatus for efficiently sorting iteration with small sorting set
CN110688249A (en) * 2019-09-20 2020-01-14 上海励驰半导体有限公司 Error injection detection circuit of error correction code circuit
CN110688249B (en) * 2019-09-20 2023-04-07 上海励驰半导体有限公司 Error injection detection circuit of error correction code circuit
CN112199308A (en) * 2020-11-26 2021-01-08 浙江大学 Low-power-consumption storage controller for special power chip and control method

Also Published As

Publication number Publication date
CN105161137B (en) 2019-04-19

Similar Documents

Publication Publication Date Title
CN101573694B (en) Method, system, and apparatus for ECC protection of small data structures
TWI594120B (en) System, method and program product for recording dwell time in a non-volatile memory system
KR101405741B1 (en) Stripe-based non-volatile multilevel memory operation
CN103544073B (en) Method for reading data of block in flash memory and related memory device
US20140258769A1 (en) Partial r-block recycling
US10461777B2 (en) Error locator polynomial decoder and method
US10097208B2 (en) Error locator polynomial decoder method
US20130304970A1 (en) Systems and methods for providing high performance redundant array of independent disks in a solid-state device
CN105161137A (en) Nand Flash controller circuit implementation apparatus in MLC framework
CN103218271B (en) A kind of data error-correcting method and device
US20150178151A1 (en) Data storage device decoder and method of operation
US11868202B2 (en) Granular error reporting on multi-pass programming of non-volatile memory
CN101634938A (en) Data migration method and data migration device of solid state disk and solid state disk
US11709733B2 (en) Metadata-assisted encoding and decoding for a memory sub-system
US20240127900A1 (en) Performing selective copyback in memory devices
US11340982B1 (en) Memory block defect detection and management
CN105027084B (en) The apparatus and method of control memory in mobile communication system
US20230034275A1 (en) Performing memory testing using error correction code values
CN112562772B (en) Adaptive low density parity check hard decoder
CN117632579B (en) Memory control method and memory storage device
US11437119B2 (en) Error read flow component
CN108574495B (en) Error locator polynomial decoder and method
WO2020015129A1 (en) Method for using error correcting code for checking in random memory without redundant storage unit
Kim et al. Unity ECC: Unified Memory Protection Against Bit and Chip Errors
CN117746959A (en) Unordered bit flip decoder for non-volatile memory device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20200730

Address after: 2505 COFCO Plaza, No.2, nanmenwai street, Nankai District, Tianjin

Patentee after: Xin Xin finance leasing (Tianjin) Co.,Ltd.

Address before: 100094 No. 6 Yongjia North Road, Beijing, Haidian District

Co-patentee before: DATANG SEMICONDUCTOR DESIGN Co.,Ltd.

Patentee before: DATANG MICROELECTRONICS TECHNOLOGY Co.,Ltd.

TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20211103

Address after: 100094 No. 6 Yongjia North Road, Beijing, Haidian District

Patentee after: DATANG MICROELECTRONICS TECHNOLOGY Co.,Ltd.

Patentee after: DATANG SEMICONDUCTOR DESIGN Co.,Ltd.

Address before: 300110 2505 COFCO Plaza, No. 2, nanmenwai street, Nankai District, Tianjin

Patentee before: Xin Xin finance leasing (Tianjin) Co.,Ltd.