CN102354535A - Logical unit multiplexing system - Google Patents
Logical unit multiplexing system Download PDFInfo
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- CN102354535A CN102354535A CN2011102225133A CN201110222513A CN102354535A CN 102354535 A CN102354535 A CN 102354535A CN 2011102225133 A CN2011102225133 A CN 2011102225133A CN 201110222513 A CN201110222513 A CN 201110222513A CN 102354535 A CN102354535 A CN 102354535A
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Abstract
The invention discloses a logical unit multiplexing system which is applicable to an error correction technology of a solid-state hard disk. The logical unit multiplexing system comprises a coding circuit and a decoding circuit. The logical unit multiplexing system is characterized in that: the coding circuit comprises a linear feedback shifting register which is used for complementing a coded/decoded information polynomial; the decoding circuit comprises a syndrome calculating module, a key equation determining module and a Chien search module; the syndrome calculating module is used for calculating to acquire a syndrome and comprises a syndrome calculating module and the linear feedback shifting register; the coding circuit and the decoding circuit multiplex the linear feedback shifting register in a time sharing mode; the key equation determining module is used for determining a key equation according to the syndrome; and the Chien search module is used for judging to acquire a root of the key equation and outputting error position information according to the root of the key equation. Therefore, a logical unit can be multiplexed in the time sharing mode, the area of an error correction code (ECC) chip can be effectively reduced, the power consumption of the ECC chip is reduced, and cost is saved.
Description
Technical field
The present invention relates to the error correcting technique of solid state hard disc, relate in particular to a kind of logical block multiplex system that is applied to the solid state hard disc error correcting technique.
Background technology
The error correcting technique that is applied to solid state hard disc at present mainly is BCH; Cataloged procedure is realized through linear feedback shift register (LFSR); Decode procedure is divided into three parts, at first is the calculating of syndrome, uses linear feedback shift register and Galois field multiplier to realize on the hardware; Following by key equation solving, is the money search procedure at last.
The syndrome computing module of cataloged procedure and decode procedure all need use linear feedback shift register to realize, both are to the polynomial expression complementation on mathematics, and difference is that divisor and dividend distinguish to some extent, on hardware, the place of coincidence is arranged.Except linear feedback shift register, syndrome computation process need be used a large amount of Galois field multipliers, realizes the multiplication of a known quantity and unknown quantity.The money search is the process of all possible known equation rooting of substitution, needs a large amount of Galois field multipliers to realize the calculating of known quantity and unknown quantity equally.It is identical that the Galois field multiplier that uses in two modules of money search and syndrome calculating has a lot of parts.Thereby the ECC implementation procedure uses a large amount of repeated logic cells.
In present designed high speed ECC, coding and decode procedure separate, and three modules of decode procedure are The pipeline design, and with raising speed, in such design, it is necessary using the logical block of repetition.ECC except the main data that needs protection, the meta data in the page or leaf that also needs protection.At present in the flash controller scheme, the read-write of meta data can divide with main data opens, and for such structure, need use different ECC protection main data and meta data respectively.Have only a metadata among the page, read or write page one time, the ECC of meta data only need carry out once, and under most situation, the ECC of meta data is idle, does not need The pipeline design.Under these circumstances, have a large amount of identical logical blocks between each module of this ECC, its power consumption is higher, and cost performance is also lower.
Can know that to sum up the error correction chip of existing solid state hard disc obviously exists inconvenience and defective, so be necessary to improve on reality is used.
Summary of the invention
To above-mentioned defective, the object of the present invention is to provide a kind of logical block multiplex system, it can the corresponding logical block of time-sharing multiplex, reduces chip area, reduces power consumption, practices thrift cost.
To achieve these goals; The present invention provides a kind of logical block multiplex system; Be applied to the solid state hard disc error correcting technique; Said logical block multiplex system comprises coding circuit and decoding scheme, and said coding circuit comprises linear feedback shift register, is used to treat the complementation of coding/decoding message polynomial;
Said decoding scheme comprises:
The syndrome module is used for calculating and obtains syndrome, and said syndrome module comprises syndrome computing module and said linear feedback shift register, said coding circuit and the said linear feedback shift register of decoding scheme time-sharing multiplex;
The key equation determination module is used for confirming key equation according to said syndrome; And
The money search module is used to judge the root that obtains said key equation, and according to the root output error positional information of said key equation.
According to logical block multiplex system of the present invention, the input end of said linear feedback shift register is connected with input and selects module, be used to control said to be encoded/decoding information imports said linear feedback shift register;
The output terminal of said linear feedback shift register is connected with output and selects module, is used to control the output mode through said linear feedback shift register information processed.
According to logical block multiplex system of the present invention, said money search module comprises:
Money Search Control module is used for the parallel control of money search, and the input information of said money Search Control module is the coefficient of said key equation, and its output information is sent to money searching and computing module;
Money searching and computing module is used for calculating the root of judging said key equation according to the output information of said money Search Control module;
Money search judge module is used for conversing errors present according to the root of said key equation, and exports said errors present information.
According to logical block multiplex system of the present invention, said syndrome computing module comprises syndrome multiplier and public multiplier; Said money searching and computing module comprises said public multiplier and money search multiplier, said syndrome computing module and the said public multiplier of money searching and computing module time-sharing multiplex.
According to logical block multiplex system of the present invention, said public multiplier is connected with a public multiplier control module, is used to control said public multiplier and works in syndrome calculating or money search condition.
The present invention reduces chip area and power consumption through the logical block of time-sharing multiplex solid state hard disc error correction chip, and is also cost-saved.Concrete, logical block multiplex system of the present invention has coding and decoding scheme, but coding circuit and decoding scheme time-sharing multiplex one linear feedback shift register.Simultaneously, decoding scheme comprises syndrome module and money search module, can this logical block of time-sharing multiplex multiplier between these two modules.Whereby, logical block multiplex system of the present invention can reduce the use of a lot of logical blocks, reduces chip power-consumption and cost, and can reduce chip area.
Description of drawings
Fig. 1 is the structural representation of the logical block multiplex system of one embodiment of the invention;
Fig. 2 is the structural representation of the money search module of one embodiment of the invention;
Fig. 3 is the structural representation of the logical block multiplex system of another embodiment of the present invention;
Fig. 4 is the structural representation of the linear feedback shift register of one embodiment of the invention.
Embodiment
In order to make the object of the invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
Referring to Fig. 1; The invention provides a kind of logical block multiplex system 100; It is mainly used in the solid state hard disc error correcting technique; This system 100 has coding circuit and decoding scheme, and solid state hard disc can carry out the coding input or the decoding output of data message by this logical block multiplex system 100, and can use the BCH error correction.
Concrete, coding circuit comprises a linear feedback shift register (LFSR) 10, is used to treat the complementation of coding/decoding message polynomial.In fact; The encoding function of coding circuit promptly realizes through linear feedback shift register 10, and for the BCH algorithm, cataloged procedure is the message polynomial process of k position to the generator polynomial complementation that move to left; Linear feedback shift register 10 of the present invention adopts shift register as shown in Figure 4; Solid state hard disc can directly be imported corresponding information data when writing data, and the value that the information input is accomplished in the late register 10 promptly is a coding result.
In one embodiment of the invention, decoding scheme comprises:
Syndrome module 20 is used for calculating and obtains syndrome, and it comprises syndrome computing module 21 and aforesaid linear feedback shift register (LFSR) 10.Concrete, solid state hard disc at first complementation among the relevant data message polynomial expression input LFSR, the root substitution remainder of primitive polynomial, calculates syndrome by syndrome computing module 21 then when carrying out sense data.
Key equation determination module 30 is used for confirming key equation according to the syndrome that syndrome module 20 calculates, and promptly can know the coefficient of key equation through this key equation determination module 30.
Money Search Control module 41 is used for the parallel control of money search, and the input information of this money Search Control module 41 is the coefficient of said key equation, and its output information is sent to money searching and computing module 42.
Money searching and computing module 42 is used for calculating the root of judging said key equation according to the output information of money Search Control module 41.
Money search judge module 43 is used for conversing errors present according to the root of key equation, and exports said errors present information, thereby carries out correction process.
For same solid state hard disc, cataloged procedure and decode procedure are that timesharing is carried out, therefore, and the coding of logical block multiplex system 100 of the present invention and decoding scheme are shared linear feedback shift register 10.Preferably, the input end of this linear feedback shift register 10 is connected with input and selects module 11, be used to control said to be encoded/the decoding information input, promptly select the coding/decoding mode of operation of linear feedback shift register 10.Simultaneously; Its output terminal is connected with output and selects module 12; Be used to control output mode through said linear feedback shift register information processed; If be cataloged procedure, then directly with the output of coded message and check information, if for decode procedure then corresponding process information is sent to other processing module.Whereby, identical logical block that coding of the present invention and decode procedure are multiplexing can reduce the use of device, thereby reduces the area and the cost of entire chip.
Another embodiment provided by the invention, as shown in Figure 3.Among this embodiment, syndrome computing module 21 comprises syndrome multiplier 211 and public multiplier 212, is used to realize multiplying each other of known quantity and unknown quantity, obtains syndrome whereby.Money searching and computing module 42 comprises said public multiplier 212 and money search multiplier 421, is used to calculate the root of judging key equation.Because the decode procedure of logical block multiplex system 100 of the present invention is divided into three flow processs in regular turn: syndrome calculates, key equation is confirmed and the money search; The iterative process that the confirming of key equation coefficient carries out according to the syndrome result; The money search arithmetic is based on key equation; Promptly realize,, otherwise be not if satisfy key equation then be the root of key equation through the mode of testing possible root substitution key equation; Equation root is corresponding with errors present information, carries out error correction thereby converse errors present based on the root of key equation.Therefore, the money search is the step of after syndrome calculates completion, just carrying out, and promptly syndrome module 20 has the time difference with money search module 40 in operation.Simultaneously all use a large amount of identical multipliers with the money search procedure,, saved chip area greatly, reduction circuit power consumption and cost so the present invention carries out time-sharing multiplex with the total multiplier of two modules because syndrome calculates.Preferably, public multiplier 212 is connected with a public multiplier control module 50, is used to control public multiplier 212 and works in syndrome calculating or money search condition.
Specify the course of work of the present invention below in conjunction with Fig. 3.
Cataloged procedure: the data message of solid state hard disc to be written; Under the control of input selection module 11, get into linear feedback shift register 10; Through obtaining coding result after the complementation processing, exporting output coding information and corresponding check information under the control of selecting module 12 then.
Decode procedure: the data message of waiting to read solid state hard disc; Under the control of input selection module 11, get into linear feedback shift register 10; Through obtaining remainder after the complementation processing; Calculate with public multiplier 212 through syndrome multiplier 211 then and obtain syndrome, key equation determination module 30 is confirmed key equation according to syndrome, and money Search Control module 41 is carried out parallel control; And carry out the root that calculation process obtains key equation with money search multiplier 421 with after the coefficient processing of key equation data being sent to public multiplier 212; This process adopts iterative processing, and money search judge module 43 converses errors present according to the root of key equation, and exports said errors present information.
In sum, the present invention reduces chip area and power consumption through the logical block of time-sharing multiplex solid state hard disc error correction chip, and is also cost-saved.Concrete, logical block multiplex system of the present invention has coding and decoding scheme, but coding circuit and decoding scheme time-sharing multiplex one linear feedback shift register.Simultaneously, decoding scheme comprises syndrome module and money search module, can this logical block of time-sharing multiplex multiplier between these two modules.Whereby, logical block multiplex system of the present invention can reduce the use of a lot of logical blocks, reduces chip power-consumption and cost, and can reduce chip area.
Certainly; The present invention also can have other various embodiments; Under the situation that does not deviate from spirit of the present invention and essence thereof; Those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (5)
1. a logical block multiplex system is applied to the solid state hard disc error correcting technique, and said logical block multiplex system comprises coding circuit and decoding scheme, it is characterized in that,
Said coding circuit comprises linear feedback shift register, is used to treat the complementation of coding/decoding message polynomial;
Said decoding scheme comprises:
The syndrome module is used for calculating and obtains syndrome, and said syndrome module comprises syndrome computing module and said linear feedback shift register, said coding circuit and the said linear feedback shift register of decoding scheme time-sharing multiplex;
The key equation determination module is used for confirming key equation according to said syndrome; And
The money search module is used to judge the root that obtains said key equation, and according to the root output error positional information of said key equation.
2. logical block multiplex system according to claim 1 is characterized in that,
The input end of said linear feedback shift register is connected with input and selects module, be used to control said to be encoded/decoding information imports said linear feedback shift register;
The output terminal of said linear feedback shift register is connected with output and selects module, is used to control the output mode through said linear feedback shift register information processed.
3. logical block multiplex system according to claim 1 is characterized in that, said money search module comprises:
Money Search Control module is used for the parallel control of money search, and the input information of said money Search Control module is the coefficient of said key equation, and its output information is sent to money searching and computing module;
Money searching and computing module is used for calculating the root of judging said key equation according to the output information of said money Search Control module;
Money search judge module is used for conversing errors present according to the root of said key equation, and exports said errors present information.
4. logical block multiplex system according to claim 3 is characterized in that,
Said syndrome computing module comprises syndrome multiplier and public multiplier;
Said money searching and computing module comprises said public multiplier and money search multiplier, said syndrome computing module and the said public multiplier of money searching and computing module time-sharing multiplex.
5. logical block multiplex system according to claim 4 is characterized in that, said public multiplier is connected with a public multiplier control module, is used to control said public multiplier and works in syndrome calculating or money search condition.
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Cited By (6)
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| CN102957437A (en) * | 2012-10-29 | 2013-03-06 | 记忆科技(深圳)有限公司 | Chien search method and device |
| CN103177769A (en) * | 2013-01-31 | 2013-06-26 | 深圳市硅格半导体有限公司 | Method and device for optimizing mistake correcting mechanism |
| CN103580700A (en) * | 2012-08-03 | 2014-02-12 | 北京兆易创新科技股份有限公司 | Syndrome solving and ECC decoding circuit and method of code word polynomials |
| CN104218957A (en) * | 2014-08-26 | 2014-12-17 | 中山大学 | RS decoder low in hardware complexity |
| CN105227192A (en) * | 2014-06-05 | 2016-01-06 | 衡宇科技股份有限公司 | The encoder of a kind of method for multi-mode BCH code coding and use the method |
| CN107688506A (en) * | 2017-08-31 | 2018-02-13 | 华中科技大学 | A kind of BCH decoding systems of flowing structure |
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| CN103580700A (en) * | 2012-08-03 | 2014-02-12 | 北京兆易创新科技股份有限公司 | Syndrome solving and ECC decoding circuit and method of code word polynomials |
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| CN103177769A (en) * | 2013-01-31 | 2013-06-26 | 深圳市硅格半导体有限公司 | Method and device for optimizing mistake correcting mechanism |
| CN105227192A (en) * | 2014-06-05 | 2016-01-06 | 衡宇科技股份有限公司 | The encoder of a kind of method for multi-mode BCH code coding and use the method |
| CN105227192B (en) * | 2014-06-05 | 2018-12-21 | 深圳衡宇芯片科技有限公司 | A kind of method encoded for multi-mode BCH code and the encoder using this method |
| CN104218957A (en) * | 2014-08-26 | 2014-12-17 | 中山大学 | RS decoder low in hardware complexity |
| CN104218957B (en) * | 2014-08-26 | 2017-07-28 | 中山大学 | A kind of RS decoders of low hardware complexity |
| CN107688506A (en) * | 2017-08-31 | 2018-02-13 | 华中科技大学 | A kind of BCH decoding systems of flowing structure |
| CN107688506B (en) * | 2017-08-31 | 2019-12-20 | 华中科技大学 | BCH decoding system with flow structure |
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Application publication date: 20120215 |