CN105227192A - The encoder of a kind of method for multi-mode BCH code coding and use the method - Google Patents

Abstract

The present invention discloses a kind of method for multi-mode BCH code coding and uses the encoder of the method.The method comprises step: set up multiple encoder matrix; With side alignment thereof in conjunction with this encoder matrix, to form an associate(d) matrix; Common subexpression is found in this associate(d) matrix; And use this associate(d) matrix to encode an information.

Description

The encoder of a kind of method for multi-mode BCH code coding and use the method

Technical field

The present invention, about a kind of encoder, particularly about a kind of multi-mode encoding device, for different B CH code, comprises the digital m in any code length, code check or GF (2m).

Background technology

Bose-Chaudhuri-Hocquenghem (BCH) code is very generally used in the error correcting code stored with communication equipment, and BCH code can be detected and revise due to the noise in memory device passage and defect, the random mistake occurred.The coding of BCH code often utilizes the combination of linear feedback shift register and some logical integrated circuit to realize.Existing linear feedback shift register circuit as shown in Figure 1.In order to accelerate computing, this circuit adopts parallel calculation patten's design usually.Symbol p in Fig. 1 represents in a jth frequency, in order to carry out the R'(j of the synchronous input calculated) p bit data.After coding, export the result Z (j) calculated.If this code length is n position, the program of coding can complete after [n/p] individual frequency.

Being described in detail as follows about Bose-Chaudhuri-Hocquenghem Code.The one encode BCH codes word with n position, has k position information, applies a generator polynomial in an encoding process:

g(x)＝x ^R+g' _R-1x ^R-1+g' _R-2x ^R-2+…+g' ₂x ²+g' ₁x ¹+g' ₀，

And wherein R=n-k+1.When use one synchronously can carry out the encoder of p parallel computation coding, in units of p position, R'(1 is cut into for initial treatment data with the n position of k position information), R'(2) ... R'(n/p) (R'(n/p) does not need for p position), and in every frequency, sequentially input to this encoder to carry out computing.Based on a general formula, in a jth frequency (1≤j≤n/p), the calculated value of output is: Z (j)=F ^p× [Z (j-1)+R'(j)].It should be noted that in Z (0), all elements is all 0.Conveniently computing, below represents

${R^{\′}}_{\left(j\right)}={[r_0^{\′}\left(j\right)r_1^{\′}\left(j\right)r_2^{\′}\left(j\right)...r_{p-1}^{\′}\left(j\right)|0...0]}_{1\mathrm{xR}}^T$

In, R'(j) be a jth p position.Z (j) has R position, is respectively expressed as Z ₀(j), Z ₁(j) ... Z _r-1(j).

In other above formula, expression further describes as follows:

$F^1=\left[\begin{array}{ccccc}{g}_{R-1}^{\′}& 1& 0& ...& 0\\ g_{R-2}^{\′}& 0& 1& ...& 0\\ .& .& .& .& .\\ .& .& .& .& .\\ .& .& .& .& .\\ g_1^{\′}& 0& 0& ...& 1\\ g_0^{\′}& 0& 0& ...& 0\end{array}\right]$

Make F'=[F ^pfront P row | F ^p], the transposed matrix of Z (j) can be obtained:

$\begin{array}{c}Z{\left(j\right)}^T={\{F^P\×[Z(j-1)+R^{\′}\left(j\right)\left]\right\}}^T\\ ={[Z(j-1)+R^{\′}\left(j\right)]}^T\×F^{p^T}\\ =\left[R^{\′}\left(j\right)Z(j-1)\right]\×F^{{\′}^T}\end{array}$

The circuit of above computing can be met, also can reach encoding operation as shown in Figure 1.The code word of one coding can obtain after [n/p] frequency.

Aforesaid method only can be used in identical Galois field GF (2m), and code check is fixing with code length.For some applications, the power m in different code lengths, code check, GF (2m) and parallel parameter p may be needed.Traditionally, these demands realize by particular B CH encoder.Thus, the complexity of hardware has uprised.In order to reduce hardware complexity, some designer may add in some multiplexers to linear feedback shift register with shared buffer would.But the area cost had more because adding these multiplexers and time delay can undermine the value of product itself.

Therefore, need a kind of for different B CH code, the method for a linear feedback shift register and the encoder using the method can be shared.In addition, the method can strengthen common subexpression search space in a matrix, to reduce hardware logic area.

Summary of the invention

As mentioned above, in the existing scheme of the design circuit of the coding of BCH code, the complexity of hardware is higher and area cost is large.Therefore a kind of for different B CH code, the encoder of the method and use the method that can share a linear feedback shift register be very in the urgent need to.

Therefore, according to a kind of aspect of the present invention, a kind of method for multi-mode BCH code coding, comprises step: set up multiple encoder matrix; With side alignment thereof in conjunction with this encoder matrix, to form an associate(d) matrix; Common subexpression is found in this associate(d) matrix; And use this associate(d) matrix to encode an information, wherein each encoder matrix has following form

And $F^1=\left[\begin{array}{ccccc}{g}_{R-1}^{\′}& 1& 0& ...& 0\\ g_{R-2}^{\′}& 0& 1& ...& 0\\ .& .& .& .& .\\ .& .& .& .& .\\ .& .& .& .& .\\ g_1^{\′}& 0& 0& ...& 1\\ g_0^{\′}& 0& 0& ...& 0\end{array}\right],$ The initial treatment data wherein having the n position of k position information for one are cut in units of p position, and R is defined as R=n-k+1; G' _r-1, g' _r-2and g' ₀be a generator polynomial g (x)=x ^r+ g' _r-1x ^r-1+ g' _r-2x ^r-2+ ... + g' ₂x ²+ g' ₁x ¹+ g' ₀coefficient; Any two encoder matrixs have identical or different n and/or k.

According to this case conception, in associate(d) matrix, for shared the sentencing of encoder matrix element 0 is supplied.Encoder matrix sequential is in the side of this associate(d) matrix.In this associate(d) matrix, at least one encoder matrix is used in the common subexpression of another encoder matrix in this associate(d) matrix.When encoder matrix minimum in associate(d) matrix can be contained in other encoder matrix contiguous form the part of 0 part, this minimum encoder matrix is arranged at this place and both sides each vicinity one encoder matrix.Preferably two adjacent encoder matrixes are separated with multiple 0.

In addition, according to another kind of aspect of the present invention, a kind of encoder for multi-mode BCH code coding, comprise: an associate(d) matrix unit, in order to provide multiple encoder matrix, input data in order to the element in one of them encoder matrix and to be had p position are multiplied, and Output rusults is a calculated data in a first frequency; One linear feedback shift register is output data in order to this calculated data that is shifted linearly, and in a second frequency, export these output data; And an adder, there is in order to receive these output data and one deal with data of the cutting of p position, these output data are added with the deal with data of cutting, and in this second frequency, export this addition result for another input data are to this associate(d) matrix unit, wherein initial treatment data with the n position of k position information are cut in units of p position, and the process data as cutting inputs this adder in order; The code word of one coding obtains in [n/p] individual frequency; Second frequency lags behind first frequency frequency.

This encoder matrix forms an associate(d) matrix in this associate(d) matrix unit with side alignment thereof, and this associate(d) matrix unit is according to the BCH code of correspondence, use an encoder matrix interior element or an encoder matrix interior element together with the common subexpression in another encoder matrix, carry out multiplying.And wherein each encoder matrix has following form

$F^1=\left[\begin{array}{ccccc}{g}_{R-1}^{\′}& 1& 0& ...& 0\\ g_{R-2}^{\′}& 0& 1& ...& 0\\ .& .& .& .& .\\ .& .& .& .& .\\ .& .& .& .& .\\ g_1^{\′}& 0& 0& ...& 1\\ g_0^{\′}& 0& 0& ...& 0\end{array}\right],$

The initial treatment data wherein having the n position of k position information for this are cut in units of p position, and R is defined as R=n-k+1; G' _r-1, g' _r-2and g' ₀be a generator polynomial g (x)=x ^r+ g' _r-1x ^r-1+ g' _r-2x ^r-2+ ... + g' ₂x ²+ g' ₁x ¹+ g' ₀coefficient; Any two encoder matrixs have identical or different n and/or k.

Accompanying drawing explanation

Fig. 1 is the conventional codec for a BCH code;

Fig. 2 is the encoder for multi-mode BCH code of encoding provided by the invention;

Fig. 3 display is used for the structure in the associate(d) matrix portion in an embodiment;

Fig. 4 display is used for the structure in the associate(d) matrix portion in another embodiment;

Fig. 5 display is used for the structure in the associate(d) matrix portion in another embodiment;

Fig. 6 display is used for the structure in the associate(d) matrix portion in an embodiment again;

Fig. 7 is the flow chart of a coding method provided by the invention.

Description of reference numerals: 10-encoder; 100-associate(d) matrix unit; 110-associate(d) matrix portion; 120-logical operation portion; 200-linear feedback shift register; 300-adder.

Embodiment

The present invention more specifically describes with reference to following embodiment.

Refer to Fig. 2 to Fig. 4, use and illustrate according to one embodiment of the invention.One encoder 10 being used for coding multi-mode BCH code comprises associate(d) matrix unit 100, linear feedback shift register 200 and an adder 300.The pattern of each BCH code can have the power m in different code checks, code length or Galois field GF (2m).By this encoder 10, the combination of any magnitude mode all may realize.

Associate(d) matrix unit 100 is used to provide multiple encoder matrix, in order to by an encoder matrix interior element or an encoder matrix interior element together with the common subexpression in another encoder matrix, the input data having a p position with, carry out multiplying.It also can further in a first frequency, and exporting aforementioned result is a calculated data.Encoder matrix forms an associate(d) matrix in this associate(d) matrix unit 100 with side alignment thereof.Associate(d) matrix unit 100, according to the BCH code of correspondence, carries out multiplying.Associate(d) matrix is stored in an associate(d) matrix portion 110.In order to have clearer and more definite understanding to associate(d) matrix portion 110, refer to Fig. 3.

Fig. 3 display is used in an embodiment, the structure in associate(d) matrix portion 110.It should be noted that this associate(d) matrix portion 110 can for any electronic component, such as read-only memory (ROM) array, to remember the element (0 or 1) of this encoder matrix.In figure 3,3 squares are used for representing 3 encoder matrixs separately.Associate(d) matrix portion 110 represents with R1x (R1+R2+R3) in the entire area of associate(d) matrix unit 100.Each sub-area F1 (having the encoder matrix 1 of length of side R1), F2 (having the encoder matrix 2 of length of side R2) and F3 (having the encoder matrix 3 of length of side R3) are used for the relative position of description encoding matrix in associate(d) matrix portion 110.The element placement of each encoder matrix is in corresponding sub-area.

As shown in Figure 3, sentencing in associate(d) matrix not shared by encoder matrix element 0 is supplied.Comparatively ideal situation be encoder matrix sequential in the side of this associate(d) matrix, preferably sequential from large to small.Certainly, other sequences such as from small to large or insert minimum between two large persons, are also feasible modes.At the upper side of associate(d) matrix, encoder matrix R1, R2 and R3 are arranged to right by left bank.Have any it should be noted, the opposite side length of associate(d) matrix should be identical with the length of side of maximum encoder matrix R1.This is the method maintaining associate(d) matrix area minimization (saving area cost) and reduce space waste.

According to the present invention, each encoder matrix can be used to input data with a p position and is multiplied and then exports its result.The one initial treatment data with the n position of k position information are cut in units of p position, and input this adder in order as the process data of cutting.These steps described in prior art, repeated no more herein.Thus, each encoder matrix has following form

and

$F^1=\left[\begin{array}{ccccc}{g}_{R-1}^{\′}& 1& 0& ...& 0\\ g_{R-2}^{\′}& 0& 1& ...& 0\\ .& .& .& .& .\\ .& .& .& .& .\\ .& .& .& .& .\\ g_1^{\′}& 0& 0& ...& 1\\ g_0^{\′}& 0& 0& ...& 0\end{array}\right]$

R is defined as R=n-k+1; G' _r-1, g' _r-2and g' ₀be a generator polynomial g (x)=x ^r+ g' _r-1x ^r-1+ g' _r-2x ^r-2+ ... + g' ₂x ²+ g' ₁x ¹+ g' ₀coefficient.Be understandable that any two encoder matrixs can have identical or different n and/or k.This means the power m that can have from the code word of the coding of each encoder matrix in different code checks, code length or Galois field GF (2m).In brief, associate(d) matrix according to its design, can provide the BCH code of different mode.

Associate(d) matrix unit 100 has a logical operation portion 120 further, to carry out multiplying.According to spirit of the present invention, some the common subexpression in two or more encoder matrixs, can be found and utilize.For example, if F1 and F2 has common subexpression, for the calculating of the multiplying of two different B CH codes, by logical operation portion 120, common subexpression in F1 is utilized to carry out.That is at least one encoder matrix employs the common subexpression of another encoder matrix in associate(d) matrix in associate(d) matrix.Thus, multiplexer just can be avoided being used in linear feedback shift register 200.The benefit of such design is can avoid because inserting multiplexer, and causes the time delay using extra area and therefore cause.According to the present invention, the not common subexpression of tool of other encoder matrix, such as F3, also can exist.All encoder matrixs do not need all have common subexpression.

As conventional linear feedback shift register, linear feedback shift register 200 this calculated data that can be shifted linearly is output data, and in a second frequency, export these output data.Adder 300 receives these output data (as Suo Shi Z (j) in Fig. 2) and and has p position, from the deal with data (as Suo Shi R ' (j) in Fig. 2) of the cutting of initial treatment data, these output data are added with the deal with data of cutting, and in this second frequency, export this addition result for another input data are to this associate(d) matrix unit.Second frequency falls behind first frequency frequency.Associate(d) matrix unit 100 is input to again with the use for calculating in second frequency by the input data of adder 300.The code word Z (as shown in Figure 2) of one coding can obtain in [n/p] individual frequency.

In another embodiment, these two encoder matrixs can occupy identical space.Ask for an interview Fig. 4.F1 and F2 in Fig. 4 has identical area and occupies the space of formed objects, but functionally not identical.According to spirit of the present invention, the arrangement of encoder matrix by arranged together for the encoder matrix of two formed objects, as shown in F1 and F2.Less F3 is placed in by F2.The remainder of associate(d) matrix fills up with 0.

Certainly, the quantity of encoder matrix is not limited to 3.It can be any be more than or equal to 2 number.In Figure 5,4 encoder matrixs (F1, F2, F3 and F4) are applied.Encoder matrix (F4) minimum in associate(d) matrix unit 110 can be contained in other encoder matrix (F2 and F3) contiguous formed in a part for 0 part.Minimum encoder matrix (F4) be positioned at 0 position and each vicinity in both sides two encoder matrixs (F2 and F3).F4 need not be arranged in close to F3, the upper side of associate(d) matrix.

By the angle of designer, 0 may be added and recognize each encoder matrix, can carry out more easily except working between two adjacent encoder matrixes.In this case, two adjacent encoder matrixes are just separated by multiple 0.Ask for an interview Fig. 6.As mentioned above, the embodiment of Fig. 6 is described between F1 and F2 by arrangement F3.That is minimum encoder matrix formula is arranged in the middle of two larger matrixes.This is again the arrangement mode that another kind is different from other embodiment.

From above explanation, a kind of method for multi-mode BCH code coding can be found.Refer to Fig. 7.The method has following steps: set up multiple encoder matrix (S01); With side alignment thereof in conjunction with this encoder matrix, to form an associate(d) matrix (S02); In this associate(d) matrix, find common subexpression (S03), and use this associate(d) matrix to encode an information (S04).Each encoder matrix should have following form:

and

$F^1=\left[\begin{array}{ccccc}{g}_{R-1}^{\′}& 1& 0& ...& 0\\ g_{R-2}^{\′}& 0& 1& ...& 0\\ .& .& .& .& .\\ .& .& .& .& .\\ .& .& .& .& .\\ g_1^{\′}& 0& 0& ...& 1\\ g_0^{\′}& 0& 0& ...& 0\end{array}\right]$

N, k, R, g' _r-1, g' _r-2and g' ₀definition illustrated as above.In associate(d) matrix, for shared the sentencing of encoder matrix element 0 is supplied.Encoder matrix sequential is in the side of this associate(d) matrix.In this associate(d) matrix, at least one encoder matrix is used in the common subexpression of another encoder matrix in this associate(d) matrix.When encoder matrix minimum in associate(d) matrix can be contained in other encoder matrix contiguous form the part of 0 part, this minimum encoder matrix is arranged at this place and both sides each vicinity one encoder matrix.Two adjacent encoder matrixes are separated with multiple 0.

Although the present invention discloses as above with embodiment; so itself and be not used to limit the present invention; have in any art and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is as the criterion when the claim depending on this case defines.

Claims (15)

1., for a method for multi-mode BCH code coding, it is characterized in that, comprise step:

Set up multiple encoder matrix;

With side alignment thereof in conjunction with this encoder matrix, to form an associate(d) matrix;

Common subexpression is found in this associate(d) matrix; And

This associate(d) matrix is used to encode an information,

Wherein, each encoder matrix has following form

And $F^1=\left[\begin{array}{ccccc}{g}_{R-1}^{\′}& 1& 0& ...& 0\\ g_{R-2}^{\′}& 0& 1& ...& 0\\ .& .& .& .& .\\ .& .& .& .& .\\ .& .& .& .& .\\ g_1^{\′}& 0& 0& ...& 1\\ g_0^{\′}& 0& 0& ...& 0\end{array}\right],$

The initial treatment data wherein having the n position of k position information for one are cut in units of p position, and R is defined as R=n-k+1; G' _r-1, g' _r-2and g' ₀be a generator polynomial g (x)=x ^r+ g' _r-1x ^r-1+ g' _r-2x ^r-2+ ... + g' ₂x ²+ g' ₁x ¹+ g' ₀coefficient; Any two encoder matrixs have identical or different n and/or k.

2. as claimed in claim 1 for the method for multi-mode BCH code coding, wherein in associate(d) matrix, for shared the sentencing of encoder matrix element 0 is supplied.

3., as claimed in claim 1 for the method for multi-mode BCH code coding, wherein encoder matrix sequential is in the side of this associate(d) matrix.

4., as claimed in claim 1 for the method for multi-mode BCH code coding, wherein in this associate(d) matrix, at least one encoder matrix is used in the common subexpression of another encoder matrix in this associate(d) matrix.

5. as claimed in claim 1 for the method for multi-mode BCH code coding, wherein when encoder matrix minimum in associate(d) matrix can be contained in other encoder matrix contiguous form the part of 0 part, this minimum encoder matrix is arranged at this place and both sides each vicinity one encoder matrix.

6., as claimed in claim 1 for the method for multi-mode BCH code coding, wherein two adjacent encoder matrixes are separated with multiple 0.

7., for an encoder for multi-mode BCH code coding, it is characterized in that, comprise:

One associate(d) matrix unit, in order to provide multiple encoder matrix, be multiplied, and Output rusults is a calculated data in a first frequency in order to the input data element in one of them encoder matrix and with p position;

One linear feedback shift register is output data in order to this calculated data that is shifted linearly, and in a second frequency, export these output data; And

One adder, has the deal with data of the cutting of p position in order to receive these output data and one, these output data be added with the deal with data of cutting, and in this second frequency, exports this addition result for another input data are to this associate(d) matrix unit,

Wherein initial treatment data with the n position of k position information are cut in units of p position, and the deal with data as cutting inputs this adder in order; The code word of one coding obtains in [n/p] individual frequency; Second frequency lags behind first frequency frequency.

8. as claimed in claim 7 for the encoder of multi-mode BCH code coding, wherein this encoder matrix forms an associate(d) matrix in this associate(d) matrix unit with side alignment thereof, and this associate(d) matrix unit is according to the BCH code of correspondence, use an encoder matrix interior element or an encoder matrix interior element together with the common subexpression in another encoder matrix, carry out multiplying.

9., as claimed in claim 8 for the encoder of multi-mode BCH code coding, wherein each encoder matrix has following form and

$F^1=\left[\begin{array}{ccccc}{g}_{R-1}^{\′}& 1& 0& ...& 0\\ g_{R-2}^{\′}& 0& 1& ...& 0\\ .& .& .& .& .\\ .& .& .& .& .\\ .& .& .& .& .\\ g_1^{\′}& 0& 0& ...& 1\\ g_0^{\′}& 0& 0& ...& 0\end{array}\right],$

The initial treatment data wherein having the n position of k position information for this are cut in units of p position, and R is defined as R=n-k+1; G' _r-1, g' _r-2and g' ₀be a generator polynomial g (x)=x ^r+ g' _r-1x ^r-1+ g' _r-2x ^r-2+ ... + g' ₂x ²+ g' ₁x ¹+ g' ₀coefficient; Any two encoder matrixs have identical or different n and/or k.

10., as claimed in claim 8 for the encoder of multi-mode BCH code coding, wherein this associate(d) matrix unit has a logical operation portion further, to carry out multiplying.

11. as claimed in claim 7 for the encoders of multi-mode BCH code coding, wherein in associate(d) matrix, for shared the sentencing of encoder matrix element 0 is supplied.

12. as claimed in claim 7 for the encoder of multi-mode BCH code coding, and wherein encoder matrix sequential is in the side of this associate(d) matrix.

13. as claimed in claim 7 for the encoder of multi-mode BCH code coding, and wherein in this associate(d) matrix, at least one encoder matrix is used in the common subexpression of another encoder matrix in this associate(d) matrix.

14. as claimed in claim 7 for the encoder of multi-mode BCH code coding, wherein when encoder matrix minimum in associate(d) matrix can be contained in other encoder matrix contiguous form the part of 0 part, this minimum encoder matrix is arranged at this place and both sides each vicinity one encoder matrix.

15. as claimed in claim 7 for the encoder of multi-mode BCH code coding, and wherein two adjacent encoder matrixes are separated with multiple 0.