CN104218957A - RS decoder low in hardware complexity - Google Patents

Abstract

The invention discloses an RS decoder low in hardware complexity. Received code words are stored; syndrome polynomial coefficient of the code words is calculated by utilizing Horner rules and used for time division to realize a chien searching function, and an error position is determined; polynomial coefficient of the error position is iteratively calculated according to the syndrome polynomial coefficient through a decomposed non-inversion Berlekamp-Massey algorithm, and polynomial calculation of an error estimated value is realized according to syndrome polynomial and error position polynomial time division; an error value on the error position is calculated; corresponding code words in a synchronous FIFO are corrected according to the error position and the error value. According to an iBM algorithm in the form of decomposition, inversion operation is eliminated during iterative solving of error position polynomial, and iteration is performed through decomposition, so that number of finite field multipliers is reduced, hardware complexity is lowered, hardware resources are saved to a great extent, and area and power consumption of a decoder chip is reduced.

Description

A kind of RS decoder of low hardware complexity

Technical field

The present invention relates to communication channel coding and decoding technical field, more specifically, relate to a kind of RS decoder of low hardware complexity.

Background technology

RS code is non-binary BCH (the Bose Chaudhuri Hocquenghem) code that a class has very strong error correcting capability, and it applies MS (Mattson-Solomon) polynomial construction out by Reed (Reed) and Suo Luomeng (Solomon) in nineteen sixty.RS code can be corrected random mark mistake and random burst error effectively, is one of modal channel coding schemes, is widely used in various communication and data-storage system to carry out error control.

RS code is based on finite field gf (2 ^m) construct, namely each symbol in RS code is GF (2 ^m) in element, the arithmetic operation between symbol carries out according to finite field operations rule.The general RS (n, n-2t) that uses represents a kind of RS code, the symbol numbers after n presentation code, and the information symbol number before n-2t presentation code, t represents the mismark number that can entangle.

Traditional RS decoder as shown in Figure 1, generally comprises five steps below:

(1) according to the codeword polynome receiving, calculate syndrome;

(2) according to syndrome, adopt BM algorithm or Euclid algorithm to calculate error location polynomial;

(3) utilize money search to obtain the root of error location polynomial, determine thus errors present;

(4) utilize good fortune Buddhist nun algorithm to obtain improper value corresponding on errors present;

(5) utilize known errors present and corresponding improper value to correct the mistake in the code word receiving.

Therefore, traditional RS decoder comprises: synchronization fifo, syndrome polynomial computation module, error location polynomial computing module, money search module, good fortune Buddhist nun's algoritic module and code word correction module.Owing to having the inversion operation of confinement in BM algorithm, in Euclid algorithm, there is polynomial division arithmetic, it is slow that these two kinds of computings all can consume a large amount of hardware resources and arithmetic speed, can not meet the requirement of modern wireless communication systems low cost or two-forty, traditional RS decoder is improved with optimization and seems particularly important.

Summary of the invention

For above deficiency, the object of this invention is to provide a kind of RS decoder of low hardware complexity, traditional RS decoder is improved and optimized, thereby reduce the hardware complexity of RS decoder, further reduce area and the power consumption of chip, reduce costs.

In order to realize this purpose, the invention provides a kind of RS decoder of low hardware complexity, comprising:

Synchronization fifo, the code word arriving for storing received;

Syndrome polynomial computation/money search multifunction module, utilizes Horner criterion to calculate the polynomial coefficient of syndrome by the code word receiving, and realizes money function of search for the time-division, determines errors present;

Error location polynomial/wrong estimate polynomial computation module, according to the polynomial coefficient of syndrome by decompose without the polynomial coefficient in contrary Berlekamp-Massey (DiBM) algorithm iteration mistake in computation position, and realize the polynomial calculating of wrong estimate according to syndrome multinomial and error location polynomial time-division;

Improper value computing module, adopts the locational improper value of good fortune Buddhist nun's algorithm mistake in computation;

Code word correction module, for according to errors present and improper value, corrects code word corresponding in synchronization fifo.

Further, syndrome polynomial computation/money search multifunction module comprises t the first computing unit and t the second computing unit, and wherein the structure of the first computing unit is as follows, comprising:

The first multiplexer M1, three inputs of the first multiplexer M1 are respectively the code word r receiving _p, 0 and Λ _q, Λ wherein _qbe the error location polynomial coefficient of error location polynomial/wrong estimate polynomial computation module output, the first finite field adder is sent in its output; P is the numeral in 0 to n-1, and q is the numeral in 1 to t;

The first Galois field multiplier, two inputs of the first Galois field multiplier are respectively α ^qwith the output of the second multiplexer M2, the first finite field adder is sent in its output;

The first finite field adder, two inputs of the first finite field adder are respectively the output of the first multiplexer M1 and the output of the first Galois field multiplier, and D is sent in its output ₁register;

The second multiplexer M2, two inputs of the second multiplexer M2 are respectively 0 and D ₁the output of register, the first Galois field multiplier is sent in its output;

D ₁register, D ₁the output that is input as the first finite field adder of register, the second finite field adder is sent in its output;

The 3rd multiplexer M3, two inputs of the 3rd multiplexer M3 be respectively 0 and upper first computing unit in the output of the second finite field adder, the second finite field adder is sent in its output;

The second finite field adder, two inputs of the second finite field adder are respectively D ₁the output of the output of register and the 3rd multiplexer M3, the second multiplexer M2 in next the first computing unit is sent in its output;

The structure of the second computing unit is as follows, comprising:

The 4th multiplexer M4, two input is respectively the code word r receiving _pwith 0, the 3rd finite field adder is sent in its output;

The second Galois field multiplier, two input is respectively α ^mwith the output of the 5th multiplexer M5, the 3rd finite field adder is sent in its output; M is that t+1 is to the numeral of 2t;

The 3rd finite field adder, two input is respectively the output of the 4th multiplexer M4 and the output of the second Galois field multiplier, and D is sent in its output ₂register;

The 5th multiplexer M5, two input is respectively 0 and D ₂the output of register, the second Galois field multiplier is sent in its output;

D ₂register, it is input as the output of the 3rd finite field adder, and the 5th multiplexer M5 is sent in its output;

N represents the incoming symbol number of decoder, and t represents the mismark number that can entangle of decoder.

Further, error location polynomial/wrong estimate polynomial computation module specifically comprises:

A plurality of multiplexers, for selecting corresponding input to come mistake in computation position multinomial or wrong estimate multinomial;

Many group registers, for storing all kinds of numerical value and the polynomial front t coefficient of syndrome of DiBM algorithm iteration process;

3 Galois field multipliers, ask the multiplying in improper value process for the multiplying of error location polynomial and the polynomial coefficient of syndrome in the multiplying of DiBM algorithm iteration process, wrong estimate polynomial computation and error location polynomial and wrong estimate multinomial;

2 finite field adders, for the add operation of the product of error location polynomial and the polynomial coefficient of syndrome in the add operation of DiBM algorithm iteration process and wrong estimate polynomial computation.

Further, a plurality of multiplexers comprise:

The 6th multiplexer M6, two input is respectively the polynomial coefficient S of syndrome _k-j+3with the output of the 15 multiplexer M15, the 3rd Galois field multiplier is sent in its output; K is 0 to 2t-1 numeral, and j is 0 to t numeral;

The 7th multiplexer M7, its t-1 input is respectively D ₄the coefficient Λ of error location polynomial Λ (x) after the output of register and DiBM algorithm iteration complete ₂, Λ ₃..., Λ _t-1, the 3rd Galois field multiplier is sent in its output;

The 8th multiplexer M8, two input is respectively the output of t+1 coefficient register of Λ (x) and the output of t+1 the coefficient register of T (x), and t+1 the coefficient register of T (x) sent in its output;

The 9th multiplexer M9, two input is respectively D ₃the output of the output of register and the 5th finite field adder, the 4th finite field adder is sent in its output;

The tenth multiplexer M10, two input is respectively the coefficient Λ of the error location polynomial Λ (x) after DiBM algorithm iteration completes ₁and the output of t+1 the coefficient register of T (x), the 4th Galois field multiplier is sent in its output;

The 11 multiplexer M11, two input is respectively storage S _t..., S ₂, S ₁t linear shift register in output and the D of second register ₅the output of register, the 4th Galois field multiplier is sent in its output;

The 12 multiplexer M12, the form derivative Λ ' that its three inputs are respectively error location polynomial Λ (x) contrary 1/ Λ ' (α (x) ^p), the coefficient Λ of the error location polynomial Λ (x) of DiBM algorithm iteration after completing ₀and the output of t+1 the coefficient register of Λ (x), the 5th Galois field multiplier is sent in its output;

The 13 multiplexer M13, its three inputs are respectively the value Ω (α of wrong estimate multinomial Ω (x) ^p), storage S _t..., S ₂, S ₁t linear shift register in output and the D of first register ₆the output of register, the 5th Galois field multiplier is sent in its output;

The 14 multiplexer M14, two input is respectively D ₅the output of register and D ₆the output of register, D is sent in its output ₆register;

The 15 multiplexer M15, its t-2 input is respectively storage S _t..., S ₂, S ₁t linear shift register in the output of the 3rd register to a t register, the 6th multiplexer M6 is sent in its output;

Many group registers comprise:

T+1 the coefficient register of Λ (x), it is input as D ₄the output of register, the 8th multiplexer M8 and the 12 multiplexer M12 are sent in its output; Be used for storing the coefficient of DiBM algorithm iteration process error location polynomial Λ (x);

T+1 the coefficient register of T (x), it is input as the output of the 8th multiplexer M8, and the 8th multiplexer M8 and the tenth multiplexer M10 are sent in its output; Be used for storing the coefficient of DiBM algorithm iteration process Auxiliary polynomial T (x);

Storage S _t..., S ₂, S ₁t linear shift register, it is input as the syndrome S of syndrome polynomial computation/money search multifunction module output ₁, S ₂..., S _t, the 11 multiplexer M11, the 13 multiplexer M13 and the 15 multiplexer M15 are sent in its output; For storing the S of displacement serial input ₁, S ₂..., S _t;

D ₃register, it is input as the output of the 4th finite field adder, and the 9th multiplexer M9 is sent in its output; Be used for storing multinomial increment Delta in the k time iterative process of DiBM algorithm iteration process ^(k+1)part and ${\mathrm{\Δ}}_{j-1}^{(k+1)}.$

D ₄register, it is input as the output of the 5th finite field adder, and t+1 coefficient register and the 7th multiplexer M7 of Λ (x) sent in its output; Be used for storing error location polynomial Λ in the k time iteration of DiBM algorithm iteration process ^(k)(x) coefficient

D ₅register, it is input as the output of the 4th finite field adder, and the 11 multiplexer M11 and the 14 multiplexer M14 are sent in its output; For storing the multinomial increment Delta in the k-1 time iterative process of DiBM algorithm iteration process ^(k).

D ₆register, it is input as the output of the 14 multiplexer M14, and the 13 multiplexer M13 and the 14 multiplexer M14 are sent in its output; For keeping or upgrade the multinomial increment of DiBM algorithm iteration process.

D ₇register, it is input as the output of the 4th finite field adder, and its output is the coefficient Ω of wrong estimate multinomial Ω (x) ₀, Ω ₁..., Ω _t-1; Coefficient for cache misses valuation multinomial Ω (x);

D ₈register, it is input as the output of the 5th Galois field multiplier, and its output is improper value; For the locational improper value of cache misses;

3 Galois field multipliers comprise:

The 3rd Galois field multiplier, two input is respectively the output of the 6th multiplexer M6 and the output of the 7th multiplexer M7, and the 4th finite field adder is sent in its output;

The 4th Galois field multiplier, two input is respectively the tenth output of multiplexer M10 and the output of the 11 multiplexer M11, and the 5th finite field adder is sent in its output;

The 5th Galois field multiplier, two input is respectively the 12 output of multiplexer M12 and the output of the 13 multiplexer M13, and the 5th finite field adder is sent in its output;

2 finite field adders comprise:

The 4th finite field adder, two input is respectively the output of the 9th multiplexer M9 and the output of the 3rd Galois field multiplier, and D is sent in its output ₃register, D ₅register and D ₇register;

The 5th finite field adder, two input is respectively the output of the 4th Galois field multiplier and the output of the 5th Galois field multiplier, and D is sent in its output ₄register and the 9th multiplexer M9.

Further, when syndrome polynomial computation/money search multifunction module is realized the polynomial calculating of syndrome, complete following operation: the first multiplexer M1 selects r _pas input, the second multiplexer M2 selects D ₁the output of register is as input, and the 3rd multiplexer M3 selects 0 as input, and the 4th multiplexer M4 selects r _pas input, the 5th multiplexer M5 selects D ₂the output of register, as input, is carried out iterative computation: establish a code word r who receives of each clock cycle input _p, calculate syndrome and often adopt Horner criterion:

S _l＝((…(r _n-1a ^l+r _n-2)a ^l+r _n-3)a ^l+…+r ₁)a ^l+r ₀,l＝1,2,…,2t，

D ₁register and D ₂value in register is multiplied by α through the first Galois field multiplier ^lafter again by the first finite field adder and r _pbe added, the result of addition is deposited into D ₁register and D ₂in register, repeat said process, until r ₀after input, D at this moment ₁register and D ₂value in register is the every coefficient of syndrome multinomial.

6, according to the RS decoder of the low hardware complexity of claim 2, it is characterized in that, when syndrome polynomial computation/money search multifunction module is realized money function of search, complete following operation: first pass through the first multiplexer M1 Λ _qcoefficient deposits D in ₁register, then selects 0, the second multiplexer M2 that is input as of the first multiplexer M1 to select D ₁the output of register is as input, and the 3rd multiplexer M3 selects the output of the second finite field adder in first computing unit as input, and each clock cycle, continuous iteration was multiplied by α ^q, when mistake is designated as 1, find errors present.

7, according to the RS decoder of the low hardware complexity of claim 3, it is characterized in that, error location polynomial/wrong estimate polynomial computation module, when carrying out the polynomial calculating of wrong estimate, completes following operation: storage S _t..., S ₂, S ₁t linear shift register be initialized as 0, the ten three multiplexer M13 and select storage S _t..., S ₂, S ₁t linear shift register in the output of first register as input, the 12 multiplexer M12 selects the coefficient Λ of error location polynomial Λ (x) ₀as input, the 11 multiplexer M11 selects storage S _t..., S ₂, S ₁t linear shift register in the output of second register as input, the tenth multiplexer M10 selects the coefficient Λ of error location polynomial Λ (x) ₁as input, the 9th multiplexer M9 selects the output of the 5th finite field adder as input, and the 7th multiplexer M7 selects the coefficient Λ of error location polynomial Λ (x) ₂as input, the 6th multiplexer M6 selects the output of the 15 multiplexer M15 as input, and the 15 multiplexer M15 selects storage S _t..., S ₂, S ₁t linear shift register in the output of the 3rd register as input; Then every t-2 clock cycle moves into a polynomial coefficient S of syndrome item by item _l, move into S _lafter t-3 clock cycle in each clock period selection of the 15 multiplexer M15 storage S _t..., S ₂, S ₁t linear shift register in the output of next register as input,, by the 4th to t, the next bit coefficient of each clock period selection error location polynomial Λ (x) of the 7th multiplexer M7 is as input, by Λ ₃to Λ _t-1, the 9th multiplexer M9 selects D ₃the output of register, as input, completes the calculating of a coefficient in wrong estimate multinomial Ω (x) after t-3 clock cycle; Repeat said process, work as S ₁, S ₂..., S _tall input is complete, just can complete t coefficient Ω in wrong estimate multinomial Ω (x) ₀, Ω ₁..., Ω _t-1calculating, Ω ₀, Ω ₁..., Ω _t-1will be successively by D ₇register output.

The present invention, owing to having adopted technique scheme, has such beneficial effect:

(1) syndrome polynomial computation/money search multifunction module is used same hardware by time-multiplexed method, to complete the function of calculating and the money search of syndrome multinomial coefficient, has saved significantly hardware resource;

(2) in error location polynomial/wrong estimate polynomial computation module, while adopting DiBM algorithm iteration to solve error location polynomial, eliminated inversion operation, compare with iBM algorithm, reduced in a large number Galois field multiplier, reduced hardware complexity, and utilize the Galois field multiplier time-division in DiBM algorithm to realize the polynomial calculating of wrong estimate, only use 3 Galois field multipliers just to complete error location polynomial and the polynomial calculating of wrong estimate, reduced significantly area and the power consumption of decoder chip.

Accompanying drawing explanation

Fig. 1 is the structured flowchart of traditional RS decoder.

Fig. 2 is the structured flowchart of the RS decoder of low hardware complexity of the present invention.

Fig. 3 is the electrical block diagram of syndrome polynomial computation of the present invention/money search multifunction module.

Fig. 4 is the structural representation of the first computing unit in syndrome polynomial computation/money search multifunction module.

Fig. 5 is the structural representation of the second computing unit in syndrome polynomial computation/money search multifunction module.

Fig. 6 is the flow chart of iBM algorithm.

Fig. 7 is Λ in DiBM algorithm iteration process ^(k)and Δ (x) ^(k+1)data Update schematic diagram.

Fig. 8 is the electrical block diagram of error location polynomial/wrong estimate polynomial computation module.

Fig. 9 is for calculating 1/ Λ ' (α ^p) circuit structure block diagram.

Figure 10 is for calculating Ω (α ^p) circuit structure block diagram.

Embodiment

Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further illustrated:

The structured flowchart of the RS decoder of low hardware complexity of the present invention as shown in Figure 2, comprises synchronization fifo, syndrome polynomial computation/money search multifunction module, error location polynomial/wrong estimate polynomial computation module, good fortune Buddhist nun's algoritic module and code word correction module.Wherein, syndrome polynomial computation/money search multifunction module is used same hardware by time-multiplexed method, to complete the function of calculating and the money search of syndrome multinomial coefficient, has saved significantly hardware resource; In error location polynomial/wrong estimate polynomial computation module, while adopting DiBM algorithm iteration to solve error location polynomial, eliminated inversion operation, compare with iBM algorithm, reduced in a large number Galois field multiplier, reduced hardware complexity, and utilize the Galois field multiplier time-division in DiBM algorithm to realize the polynomial calculating of wrong estimate, only use 3 Galois field multipliers just to complete error location polynomial and the polynomial calculating of wrong estimate, reduced significantly area and the power consumption of decoder chip.

If the codeword polynome receiving is:

R(x)＝r _n-1x ^n-1+r _n-2x ^n-2+…+r ₁x+r ₀ (1)

The computing formula of the polynomial coefficient of syndrome is:

$S_l=R\left({\mathrm{\α}}^l\right)=\underset{i=0}{\overset{n-1}{\mathrm{\Σ}}}{r}_i{\mathrm{\α}}^{\mathrm{il}},l=\mathrm{1,2},...,2t---\left(2\right)$

Adopt Horner criterion to calculate S _lcan realize by nested multiply accumulating computing, make money search can use same circuit structure with the polynomial calculating of syndrome simultaneously, this circuit structure is carried out to the use that time division multiplexing can reduce hardware resource, Horner criterion is calculated S _lshown in (3):

S _l＝((…(r _n-1a ^l+r _n-2)a ^l+r _n-3)a ^l+…+r ₁)a ^l+r ₀,l＝1,2,…,2t (3)

Can obtain thus the electrical block diagram of syndrome polynomial computation/money search multifunction module as shown in Figure 3, and the structural representation of each the first computing unit as shown in Figure 4, the structural representation of each the second computing unit as shown in Figure 5.The operation principle of syndrome polynomial computation/money search multifunction module is as follows: when calculating syndrome multinomial, the first multiplexer M1 selects r _pas input, the second multiplexer M2 selects D ₁the output of register is as input, and the 3rd multiplexer M3 selects 0 as input, and the 4th multiplexer M4 selects r _pas input, the 5th multiplexer M5 selects D ₂the output of register, as input, is carried out iterative computation: establish a code word r who receives of each clock cycle input _p, calculate syndrome according to following Horner criterion: S _l=((... (r _n-1a ^l+ r _n-2) a ^l+ r _n-3) a ^l+ ... + r ₁) a ^l+ r ₀, l=1,2 ..., 2t, so D ₁register and D ₂value in register is multiplied by α via the first Galois field multiplier ^lafter again by the first finite field adder and r _pbe added, the result of addition is deposited into D ₁register and D ₂in register, repeat said process, until r always ₀after input, D at this moment ₁register and D ₂value in register is the every coefficient of syndrome multinomial, wherein D ₁value in register is S ₁, S ₂..., S _t, D ₂value in register is S _t+1, S _t+2..., S _2t.When realizing money function of search, complete following operation: first pass through the first multiplexer M1 Λ _qcoefficient deposits D in ₁register, then selects 0, the second multiplexer M2 that is input as of the first multiplexer M1 to select D ₁the output of register is as input, and the 3rd multiplexer M3 selects the output of the second finite field adder in first computing unit as input, and each clock cycle, continuous iteration was multiplied by α ^q, when mistake is designated as 1, find errors present, realized the function of money search.

In order to solve error location polynomial, the present invention adopts the iBM algorithm of decomposed form, this algorithm is compared and has been eliminated inversion operation with general BM algorithm, thereby simplified circuit structure, in addition, this algorithm is compared with iBM algorithm, reduced a large amount of Galois field multipliers, and the number of Galois field multiplier is weighed an important parameter of its hardware complexity often in RS decoding algorithm, general iBM algorithm needs 3t+2 Galois field multiplier, and DiBM algorithm only needs 3 Galois field multipliers can complete the calculating of error location polynomial, reduced more further hardware complexity.

Error location polynomial/wrong estimate polynomial computation module is that 2t the syndrome of exporting by syndrome polynomial computation/money search multifunction module comes mistake in computation position polynomial, and the flow chart of iBM algorithm as shown in Figure 6, in iBM algorithm, use formula (4) is calculated Δ as shown in Figure 6 ^(k+1):

${\mathrm{\Δ}}^{(k+1)}=S_{k+2}{\mathrm{\Λ}}_0^{\left(k\right)}+S_{k+1}{\mathrm{\Λ}}_1^{\left(k\right)}+...+S_{k-t+2}{\mathrm{\Λ}}_t^{\left(k\right)}---\left(4\right)$

In iBM algorithm, use formula (5) is calculated Λ ^(k)(x), as follows:

Λ ^(k)(x)＝δ·Λ ^(k-1)(x)+Δ ^(k)T ^(k-1)(x)x (5)

IBM algorithm needs iteration altogether 2t time, DiBM algorithm will be each time iteration decompose to t+1 clock cycle and carry out, so DiBM algorithm iteration to complete the required clock cycle be that 2t (t+1) is individual, convolution (4) and formula (5), by Λ ^(k)and Δ (x) ^(k+1)decompose to t+1 clock cycle, can be expressed as:

${\mathrm{\Λ}}_j^{\left(k\right)}=\left\{\begin{array}{cc}\mathrm{\δ}\·{\mathrm{\Λ}}_0^{(k-1)}& j=0\\ \mathrm{\δ}\·{\mathrm{\Λ}}_j^{(k-1)}+{\mathrm{\Δ}}^{\left(k\right)}{T}_{j-1}^{(k-1)}& 1\≤j\≤t\end{array}\right.---\left(6\right)$

${\mathrm{\Δ}}_j^{(k+1)}=\left\{\begin{array}{cc}0& j=0\\ {\mathrm{\Δ}}_{j-1}^{(k+1)}+S_{k-j+3}{\mathrm{\Λ}}_{j-1}^{\left(k\right)}& 1\≤j\≤t\end{array}\right.---\left(7\right)$

Formula (6) refer to Λ ^(k)(x) coefficient, t ^(k-1)(x) coefficient, in formula (7) to calculate Δ in the k time iterative process ^(k+1)part and.Article two, formula shows that 3 Galois field multipliers of needs calculate respectively within a clock cycle with compare with iBM algorithm, thereby reduce hardware complexity by reducing a large amount of Galois field multipliers.

Complete DiBM algorithm, the input of syndrome will meet certain requirement.In DiBM algorithm, in each iterative process, calculate Δ ^(k)needed syndrome is all different, and concrete condition is as shown in table 1.

In table 1DiBM algorithm, calculate Δ ^(k)the syndrome of input

By formula (6) and formula (7), know calculating Δ ^(k+1)need Λ ^(k)(x) coefficient, so Λ ^(k)(x) compare Δ ^(k+1)early a clock cycle calculates, Λ ^(k)(x) be to complete during j=t in the k time iteration, and Δ ^(k+1)to complete during j=0 in the k+1 time iteration, namely:

${\mathrm{\Δ}}^{(k+1)}={\mathrm{\Δ}}_t^{(k+1)}+S_{k-t+2}{\mathrm{\Λ}}_t^{\left(k\right)}=S_{k+2}{\mathrm{\Λ}}_0^{\left(k\right)}+S_{k+1}{\mathrm{\Λ}}_1^{\left(k\right)}+...+S_{k-t+2}{\mathrm{\Λ}}_1^{\left(k\right)}---\left(8\right)$

Λ ^(k)and Δ (x) ^(k+1)data decomposition situation as shown in table 2.

Table 2 Λ ^(k)and Δ (x) ^(k+1)data decomposition information slip

According to table 2, can obtain Fig. 7, his-and-hers watches 2 and Fig. 7 analyze known, in the k time iteration, in the clock cycle of j=0, obtain Δ ^(k), while Λ ^(k)(x) coefficient of minimum power the δ producing in the k-1 time iteration with multiply each other and obtain, by Δ ^(k)with the δ obtaining in the k-1 time iteration, Λ ^(k-1)and T (x) ^(k-1)(x) can calculate Λ remaining t clock cycle ^(k)(x) t remaining coefficient, j clock cycle the syndrome S being inputted by current time _k-j+3calculate with j-1 clock cycle multiply each other, then calculate with j-1 clock cycle addition obtains.

Can be in the hope of error location polynomial Λ (x) by DiBM algorithm, and the computing formula of wrong estimate multinomial Ω (x) is as follows:

Ω(x)＝S(x)Λ(x)(mod x ^2t) (9)

＝Ω ₀+Ω ₁x+…+Ω _t-1x ^t-1

And the relation of coefficient meets between syndrome multinomial S (x), error location polynomial Λ (x) and wrong estimate multinomial Ω (x) three:

$\left\{\begin{array}{c}{\mathrm{\Ω}}_0={\mathrm{\Λ}}_0{S}_1\\ {\mathrm{\Ω}}_1={\mathrm{\Λ}}_0{S}_2+{\mathrm{\Λ}}_1{S}_1\\ .\\ .\\ .\\ {\mathrm{\Ω}}_{t-1}={\mathrm{\Λ}}_0{S}_t+{\mathrm{\Λ}}_1{S}_{t-1}+...+{\mathrm{\Λ}}_{t-1}{S}_1\end{array}\right.---\left(10\right)$

According to DiBM, solve error location polynomial Λ (x) and solve wrong estimate multinomial Ω (x) by formula (10), for further reducing the use of hardware resource, can carry out time division multiplexing to the Galois field multiplier using in DiBM algorithm, so the present invention adopts the circuit structure block diagram of error location polynomial/wrong estimate polynomial computation module as shown in Figure 8 to come the time-division to realize error location polynomial and the polynomial calculating of wrong estimate.

The operation principle of error location polynomial/wrong estimate polynomial computation module is as follows: when using DiBM algorithm mistake in computation position multinomial, t+1 coefficient register of Λ (x) and t+1 the coefficient register of T (x) be all initialized as (1,0 ... 0), D ₆initialization of register is 1, and all the other initialization of register are that 0, the six multiplexer M6 selects the polynomial coefficient S of syndrome _k-j+3as input, the 7th multiplexer M7 selects D ₄the output of register is as input, and the 8th multiplexer M8 is according to control signal: if Δ ^(k)=0 or 2L ^(k-1)>=k+1 selects the output of t+1 coefficient register of T (x) as input, otherwise selects the output of t+1 coefficient register of Λ (x) as input, the 9th multiplexer M9 selection D ₃the output of register is as input, and the output of t+1 the coefficient register of the tenth multiplexer M10 selection T (x) is as input, and the 11 multiplexer M11 selects D ₅the output of register is as input, and the output of t+1 the coefficient register of the 12 multiplexer M12 selection Λ (x) is as input, and the 13 multiplexer M13 selects D ₆the output of register is as input, and the 14 multiplexer M14 is according to control signal: if Δ ^(k)=0 or 2L ^(k-1)>=k+1 selects D ₆the output of register is as input, otherwise selection D ₅the output of register is as input, the polynomial coefficient of syndrome all in t+1 the clock cycle after input t+1 the coefficient of error location polynomial Λ (x) calculate one by one completely, and be stored in t+1 the coefficient register of Λ (x).

After using DiBM algorithm to calculate error location polynomial, just can start mistake in computation valuation multinomial.Error location polynomial/wrong estimate polynomial computation module, when carrying out the polynomial calculating of wrong estimate, completes following operation: storage S _t..., S ₂, S ₁t linear shift register be initialized as 0, the ten three multiplexer M13 and select storage S _t..., S ₂, S ₁t linear shift register in the output of first register as input, the 12 multiplexer M12 selects the coefficient Λ of error location polynomial Λ (x) ₀as input, the 11 multiplexer M11 selects storage S _t..., S ₂, S ₁t linear shift register in the output of second register as input, the tenth multiplexer M10 selects the coefficient Λ of error location polynomial Λ (x) ₁as input, the 9th multiplexer M9 selects the output of the 5th finite field adder as input, and the 7th multiplexer M7 selects the coefficient Λ of error location polynomial Λ (x) ₂as input, the 6th multiplexer M6 selects the output of the 15 multiplexer M15 as input, and the 15 multiplexer M15 selects storage S _t..., S ₂, S ₁t linear shift register in the output of the 3rd register as input; Then every t-2 clock cycle moves into a polynomial coefficient S of syndrome item by item _l, move into S _lafter t-3 clock cycle in each clock period selection of the 15 multiplexer M15 storage S _t..., S ₂, S ₁t linear shift register in the output of next register as input,, by the 4th to t, the next bit coefficient of each clock period selection error location polynomial Λ (x) of the 7th multiplexer M7 is as input, by Λ ₃to Λ _t-1, the 9th multiplexer M9 selects D ₃the output of register, as input, completes the calculating of a coefficient in wrong estimate multinomial Ω (x) after t-3 clock cycle; Repeat said process, work as S ₁, S ₂..., S _tall input is complete, just can complete t coefficient Ω in wrong estimate multinomial Ω (x) ₀, Ω ₁..., Ω _t-1calculating, Ω ₀, Ω ₁..., Ω _t-1will be successively by D ₇register output.

In order further to reduce hardware complexity, after completing the calculating of wrong estimate multinomial Ω (x), utilize good fortune Buddhist nun algorithm to ask improper value to need a Galois field multiplier, the 5th Galois field multiplier in error location polynomial/wrong estimate polynomial computation module is carried out to time division multiplexing can meet the demands.During mistake in computation value, the form derivative Λ ' of the 12 multiplexer M12 selection error location polynomial Λ (x) contrary 1/ Λ ' (α (x) ^p) as input, the 13 multiplexer M13 selects the value Ω (α of wrong estimate multinomial Ω (x) ^p) as input, improper value will be by D ₈register is exported.1/ Λ ' (α ^p) and Ω (α ^p) counting circuit respectively as shown in Figure 9 and Figure 10, the m in Fig. 9 refers to the maximum odd number that is not more than t.

In the present invention, when the RS decoder using as shown in Figure 2, and work as the structure of described syndrome polynomial computation/money search multifunction module as shown in Figure 3, the structure of described error location polynomial/wrong estimate polynomial computation module is as shown in Figure 8 time, and the decode procedure of this RS decoder is as described below:

(1) calculate syndrome multinomial: the codeword polynome R (x) receiving is input to syndrome polynomial computation/money search multifunction module item by item, and stores synchronization fifo simultaneously into, after all code words that receive are all inputted, be stored in D ₁register and D ₂value in register is exactly the polynomial every coefficient of syndrome.Judge whether the polynomial every coefficient of syndrome is 0, if be all 0, illustrate that the codeword polynome R (x) receiving does not have mistake, the code word that directly output receives, decoding finishes.Otherwise enter (2) step.

(2) mistake in computation position multinomial: by the polynomial coefficient S of syndrome _laccording to the input requirements of DiBM algorithm, be input to error location polynomial/wrong estimate polynomial computation module, adopt DiBM algorithm to complete the calculating of error location polynomial, and by each coefficient storage of error location polynomial to t+1 the coefficient register of Λ (x), enter (3) step.

(3) mistake in computation valuation multinomial: every t-2 clock cycle moves into a polynomial coefficient S of syndrome item by item _l, S of every immigration _lcan complete the calculating of a coefficient in wrong estimate multinomial Ω (x), work as S ₁, S ₂..., S _tall input is complete, just can complete t coefficient Ω in wrong estimate multinomial Ω (x) ₀, Ω ₁..., Ω _t-1calculating.

(4) money search and good fortune Buddhist nun algorithm: by syndrome polynomial computation/money search multifunction module, realize money search, determine errors present, and by improper value corresponding on good fortune Buddhist nun algoritic module mistake in computation position, mistake is designated as to 1 errors present number simultaneously and counts.

(5) code word error correction: when the mistake of syndrome polynomial computation/money search multifunction module output is designated as 1, the improper value of trying to achieve in the code word of reading from synchronization fifo and good fortune Buddhist nun algorithm is carried out to finite field add operation, can obtain correct code word, until money search is all verified all codeword positions, decoding finishes.If the number of errors present is different from the highest order of error location polynomial, illustrate in the codeword polynome R (x) receiving and have the mistake more than t symbol, can not realize correct error correction, provide and exceed the indication that can entangle scope.

The foregoing is only better embodiment of the present invention, the present invention is not limited to above-mentioned execution mode, in implementation process, may there is local small structural modification, if various changes of the present invention or modification are not departed to the spirit and scope of the present invention, and within belonging to claim of the present invention and equivalent technologies scope, the present invention is also intended to comprise these changes and modification.

Claims (7)

1. a RS decoder for low hardware complexity, is characterized in that, comprising:

Synchronization fifo, the code word arriving for storing received;

Syndrome polynomial computation/money search multifunction module, utilizes Horner criterion to calculate the polynomial coefficient of syndrome by the code word receiving, and realizes money function of search for the time-division, determines errors present;

Error location polynomial/wrong estimate polynomial computation module, according to the polynomial coefficient of syndrome, pass through the polynomial coefficient in DiBM algorithm iteration mistake in computation position, and realize the polynomial calculating of wrong estimate according to syndrome multinomial and error location polynomial time-division;

Improper value computing module, adopts the locational improper value of good fortune Buddhist nun's algorithm mistake in computation;

Code word correction module, for according to errors present and improper value, corrects code word corresponding in synchronization fifo.

2. the RS decoder of low hardware complexity according to claim 1, is characterized in that, syndrome polynomial computation/money search multifunction module comprises t the first computing unit and t the second computing unit, and wherein the structure of the first computing unit is as follows, comprising:

The first multiplexer M1, three inputs of the first multiplexer M1 are respectively the code word r receiving _p, 0 and Λ _q, Λ wherein _qbe the error location polynomial coefficient of error location polynomial/wrong estimate polynomial computation module output, the first finite field adder is sent in its output; P is the numeral in 0 to n-1, and q is the numeral in 1 to t;

The first Galois field multiplier, two inputs of the first Galois field multiplier are respectively α ^qwith the output of the second multiplexer M2, the first finite field adder is sent in its output;

The first finite field adder, two inputs of the first finite field adder are respectively the output of the first multiplexer M1 and the output of the first Galois field multiplier, and D is sent in its output ₁register;

The second multiplexer M2, two inputs of the second multiplexer M2 are respectively 0 and D ₁the output of register, the first Galois field multiplier is sent in its output;

D ₁register, D ₁the output that is input as the first finite field adder of register, the second finite field adder is sent in its output;

The 3rd multiplexer M3, two inputs of the 3rd multiplexer M3 be respectively 0 and upper first computing unit in the output of the second finite field adder, the second finite field adder is sent in its output;

The second finite field adder, two inputs of the second finite field adder are respectively D ₁the output of the output of register and the 3rd multiplexer M3, the second multiplexer M2 in next the first computing unit is sent in its output;

The structure of the second computing unit is as follows, comprising:

The 4th multiplexer M4, two input is respectively the code word r receiving _pwith 0, the 3rd finite field adder is sent in its output;

The second Galois field multiplier, two input is respectively α ^mwith the output of the 5th multiplexer M5, the 3rd finite field adder is sent in its output; M is that t+1 is to the numeral of 2t;

The 3rd finite field adder, two input is respectively the output of the 4th multiplexer M4 and the output of the second Galois field multiplier, and D is sent in its output ₂register;

The 5th multiplexer M5, two input is respectively 0 and D ₂the output of register, the second Galois field multiplier is sent in its output;

D ₂register, it is input as the output of the 3rd finite field adder, and the 5th multiplexer M5 is sent in its output;

N represents the incoming symbol number of decoder, and t represents the mismark number that can entangle of decoder.

3. the RS decoder of low hardware complexity according to claim 2, is characterized in that, error location polynomial/wrong estimate polynomial computation module specifically comprises:

A plurality of multiplexers, for selecting corresponding input to come mistake in computation position multinomial or wrong estimate multinomial;

Many group registers, for storing all kinds of numerical value and the polynomial front t coefficient of syndrome of DiBM algorithm iteration process;

3 Galois field multipliers, ask the multiplying in improper value process for the multiplying of error location polynomial and the polynomial coefficient of syndrome in the multiplying of DiBM algorithm iteration process, wrong estimate polynomial computation and error location polynomial and wrong estimate multinomial;

2 finite field adders, for the add operation of the product of error location polynomial and the polynomial coefficient of syndrome in the add operation of DiBM algorithm iteration process and wrong estimate polynomial computation.

4. the RS decoder of low hardware complexity according to claim 3, is characterized in that, a plurality of multiplexers comprise:

The 6th multiplexer M6, two input is respectively the polynomial coefficient S of syndrome _k-j+3with the output of the 15 multiplexer M15, the 3rd Galois field multiplier is sent in its output; K is 0 to 2t-1 numeral, and j is 0 to t numeral;

The 7th multiplexer M7, its t-1 input is respectively D ₄the coefficient Λ of error location polynomial Λ (x) after the output of register and DiBM algorithm iteration complete ₂, Λ ₃..., Λ _t-1, the 3rd Galois field multiplier is sent in its output;

The 8th multiplexer M8, two input is respectively the output of t+1 coefficient register of Λ (x) and the output of t+1 the coefficient register of T (x), and t+1 the coefficient register of T (x) sent in its output;

The 9th multiplexer M9, two input is respectively D ₃the output of the output of register and the 5th finite field adder, the 4th finite field adder is sent in its output;

The tenth multiplexer M10, two input is respectively the coefficient Λ of the error location polynomial Λ (x) after DiBM algorithm iteration completes ₁and the output of t+1 the coefficient register of T (x), the 4th Galois field multiplier is sent in its output;

The 11 multiplexer M11, two input is respectively storage S _t..., S ₂, S ₁t linear shift register in output and the D of second register ₅the output of register, the 4th Galois field multiplier is sent in its output;

The 12 multiplexer M12, the form derivative Λ ' that its three inputs are respectively error location polynomial Λ (x) contrary 1/ Λ ' (α (x) ^p), the coefficient Λ of the error location polynomial Λ (x) of DiBM algorithm iteration after completing ₀and the output of t+1 the coefficient register of Λ (x), the 5th Galois field multiplier is sent in its output;

The 13 multiplexer M13, its three inputs are respectively the value Ω (α of wrong estimate multinomial Ω (x) ^p), storage S _t..., S ₂, S ₁t linear shift register in output and the D of first register ₆the output of register, the 5th Galois field multiplier is sent in its output;

The 14 multiplexer M14, two input is respectively D ₅the output of register and D ₆the output of register, D is sent in its output ₆register;

The 15 multiplexer M15, its t-2 input is respectively storage S _t..., S ₂, S ₁t linear shift register in the output of the 3rd register to a t register, the 6th multiplexer M6 is sent in its output;

Many group registers comprise:

T+1 the coefficient register of Λ (x), it is input as D ₄the output of register, the 8th multiplexer M8 and the 12 multiplexer M12 are sent in its output; Be used for storing the coefficient of DiBM algorithm iteration process error location polynomial Λ (x);

T+1 the coefficient register of T (x), it is input as the output of the 8th multiplexer M8, and the 8th multiplexer M8 and the tenth multiplexer M10 are sent in its output; Be used for storing the coefficient of DiBM algorithm iteration process Auxiliary polynomial T (x);

Storage S _t..., S ₂, S ₁t linear shift register, it is input as the syndrome S of syndrome polynomial computation/money search multifunction module output ₁, S ₂..., S _t, the 11 multiplexer M11, the 13 multiplexer M13 and the 15 multiplexer M15 are sent in its output; For storing the S of displacement serial input ₁, S ₂..., S _t;

D ₃register, it is input as the output of the 4th finite field adder, and the 9th multiplexer M9 is sent in its output; Be used for storing multinomial increment Delta in the k time iterative process of DiBM algorithm iteration process ^(k+1)part and ${\mathrm{\Δ}}_{j-1}^{(k+1)}.$

D ₄register, it is input as the output of the 5th finite field adder, and t+1 coefficient register and the 7th multiplexer M7 of Λ (x) sent in its output; Be used for storing error location polynomial Λ in the k time iteration of DiBM algorithm iteration process ^(k)(x) coefficient

D ₅register, it is input as the output of the 4th finite field adder, and the 11 multiplexer M11 and the 14 multiplexer M14 are sent in its output; For storing the multinomial increment Delta in the k-1 time iterative process of DiBM algorithm iteration process ^(k).

D ₆register, it is input as the output of the 14 multiplexer M14, and the 13 multiplexer M13 and the 14 multiplexer M14 are sent in its output; For keeping or upgrade the multinomial increment of DiBM algorithm iteration process.

D ₇register, it is input as the output of the 4th finite field adder, and its output is the coefficient Ω of wrong estimate multinomial Ω (x) ₀, Ω ₁..., Ω _t-1; Coefficient for cache misses valuation multinomial Ω (x);

D ₈register, it is input as the output of the 5th Galois field multiplier, and its output is improper value; For the locational improper value of cache misses;

3 Galois field multipliers comprise:

The 3rd Galois field multiplier, two input is respectively the output of the 6th multiplexer M6 and the output of the 7th multiplexer M7, and the 4th finite field adder is sent in its output;

The 4th Galois field multiplier, two input is respectively the tenth output of multiplexer M10 and the output of the 11 multiplexer M11, and the 5th finite field adder is sent in its output;

The 5th Galois field multiplier, two input is respectively the 12 output of multiplexer M12 and the output of the 13 multiplexer M13, and the 5th finite field adder is sent in its output;

2 finite field adders comprise:

The 4th finite field adder, two input is respectively the output of the 9th multiplexer M9 and the output of the 3rd Galois field multiplier, and D is sent in its output ₃register, D ₅register and D ₇register;

The 5th finite field adder, two input is respectively the output of the 4th Galois field multiplier and the output of the 5th Galois field multiplier, and D is sent in its output ₄register and the 9th multiplexer M9.

5. the RS decoder of low hardware complexity according to claim 2, is characterized in that, when syndrome polynomial computation/money search multifunction module is realized the polynomial calculating of syndrome, completes following operation: the first multiplexer M1 selects r _pas input, the second multiplexer M2 selects D ₁the output of register is as input, and the 3rd multiplexer M3 selects 0 as input, and the 4th multiplexer M4 selects r _pas input, the 5th multiplexer M5 selects D ₂the output of register, as input, is carried out iterative computation: establish a code word r who receives of each clock cycle input _p, calculate syndrome and often adopt Horner criterion:

S _l＝((…(r _n-1a ^l+r _n-2)a ^l+r _n-3)a ^l+…+r ₁)a ^l+r ₀,l＝1,2,…,2t，

D ₁register and D ₂value in register is multiplied by α through the first Galois field multiplier ^lafter again by the first finite field adder and r _pbe added, the result of addition is deposited into D ₁register and D ₂in register, repeat said process, until r ₀after input, D at this moment ₁register and D ₂value in register is the every coefficient of syndrome multinomial.

6. the RS decoder of low hardware complexity according to claim 2, is characterized in that, when syndrome polynomial computation/money search multifunction module is realized money function of search, completes following operation: first pass through the first multiplexer M1 Λ _qcoefficient deposits D in ₁register, then selects 0, the second multiplexer M2 that is input as of the first multiplexer M1 to select D ₁the output of register is as input, and the 3rd multiplexer M3 selects the output of the second finite field adder in first computing unit as input, and each clock cycle, continuous iteration was multiplied by α ^q, when mistake is designated as 1, find errors present.

7. the RS decoder of low hardware complexity according to claim 3, is characterized in that, error location polynomial/wrong estimate polynomial computation module, when carrying out the polynomial calculating of wrong estimate, completes following operation: storage S _t..., S ₂, S ₁t linear shift register be initialized as 0, the ten three multiplexer M13 and select storage S _t..., S ₂, S ₁t linear shift register in the output of first register as input, the 12 multiplexer M12 selects the coefficient Λ of error location polynomial Λ (x) ₀as input, the 11 multiplexer M11 selects storage S _t..., S ₂, S ₁t linear shift register in the output of second register as input, the tenth multiplexer M10 selects the coefficient Λ of error location polynomial Λ (x) ₁as input, the 9th multiplexer M9 selects the output of the 5th finite field adder as input, and the 7th multiplexer M7 selects the coefficient Λ of error location polynomial Λ (x) ₂as input, the 6th multiplexer M6 selects the output of the 15 multiplexer M15 as input, and the 15 multiplexer M15 selects storage S _t..., S ₂, S ₁t linear shift register in the output of the 3rd register as input; Then every t-2 clock cycle moves into a polynomial coefficient S of syndrome item by item _l, move into S _lafter t-3 clock cycle in each clock period selection of the 15 multiplexer M15 storage S _t..., S ₂, S ₁t linear shift register in the output of next register as input,, by the 4th to t, the next bit coefficient of each clock period selection error location polynomial Λ (x) of the 7th multiplexer M7 is as input, by Λ ₃to Λ _t-1, the 9th multiplexer M9 selects D ₃the output of register, as input, completes the calculating of a coefficient in wrong estimate multinomial Ω (x) after t-3 clock cycle; Repeat said process, work as S ₁, S ₂..., S _tall input is complete, just can complete t coefficient Ω in wrong estimate multinomial Ω (x) ₀, Ω ₁..., Ω _t-1calculating, Ω ₀, Ω ₁..., Ω _t-1will be successively by D ₇register output.