CN101079640A - Reed-Solomon code decoder - Google Patents

Abstract

The invention discloses a Reed-Solomon code decoder (12), which comprises the following parts from input to output connected electrically: adjoint calculating mode, MEA algorism mode (22), money searching mode (23), Funi algorism mode (24) and correction output mode (25) and data buffer mode (26) between the output end and correction output mode, wherein the input is multi-byte bus input; the MEA algorism mode contains one or more paralleling 8-bit MEA algorism submode (41) between calculating mode and money searching mode, which divides time and processes respective 16-bit data through consolidating to halve each iterative time. The decoder saves resource because the broad bus band is more than 1 byte, which reduces the designing difficulty.

Description

A kind of Reed-Solomon sign indicating number decoder

Technical field

The present invention relates to digital fiber communication, be specifically related to a kind of Reed-Solomon Reed-Solomon (being called for short RS) sign indicating number decoder.

Background technology

In present digital fiber communication system, forward error correction technique has obtained using widely.In optical fiber telecommunications system, FEC at first is applied to extra large cableless communication system.ITU-T has adopted the part of FEC function as extra large cableless communication standard in the G.975 suggestion of promulgation in 1996, and in the new draft that passes through in April, 2000, the FEC function that has increased the 10Gbit/s system newly is as option.Because bandwidth bottleneck is transferred to the access part by backbone network, the FTTx technology is becoming the hot spot technology in the communication network day by day.In the technology that FTTH adopted, EPON (PON) technology is the most potential a kind of technology.In the PON technology, the most attractive two kinds of technology are Ethernet passive optical network (EPON) and the above operating rate gigabit passive optical network of 1Gbps (GPON) at present.EPON uses the ethernet technology that extensively adopts as link layer protocol, meets the development trend of professional IPization.GPON is the standard that an operator drives, and speed is higher, can effectively support the professional and service quality assurance (QOS) of Time Division Multiplexing, has very strong operation, management, maintenance function (OAM), has higher efficiency of transmission.Along with the development of FTTx, the GPON technology is more and more paid close attention to.The standard I TU-T of GPON G.984.3 in, adopt the FEC technology of RS (255,239) coding.

Forward error correction coding in communication system (FEC) sends data with a kind of coded format, is used in the transport layer usually.By when encoding, introducing some redundant codes, make decoder can detect and correct the mistake of transmission.If the BER of decoder input data is 10-4, the BER of decoder output will be reduced to 10-15 so.By using the FEC technology, just can realize that low error rate sends data, thereby avoid using retransmission mechanism.

Reed-Solomon (RS) is a kind of block encoding, as shown in Figure 1, use RS encoder 11 and use RS decoder 12 can realize that low error rate transmits at transmitting terminal at receiving terminal, the RS coding uses a kind of data block of constant size, and add that at the end some redundancy bytes, data block add that redundancy bytes has just constituted a code word.By these redundant codes, the fec decoder device just can detect, correct a mistake in data streams and recover initial data.The Reed-Solomon sign indicating number has specified in more detail in ITU-T Rec.J.8.The most frequently used RS sign indicating number is RS (255,239).Long 255 bytes of the code word of this sign indicating number add that by the data of 239 bytes the redundant code of 16 bytes constitutes.RS (255,239) G.975 and G.709 all has use at ITU-T Recs.When FEC has used block encoding, as RS (255,239), original data have been retained, just preceding 239 bytes of code word.Therefore, even the situation that the other end is not supported FEC occurred, neglect check code and can handle initial data too.

The decoder of RS sign indicating number generally is made up of (referring to document H.Lee following four parts, A High-SpeedLow-Complexity Reed-Solomon Decoder for Optical Communications, [J] IEEETrans.Circuit Syst.-II:Express briefs, vol.52, no.8, pp461-465, Aug 2005): (1) syndrome computing module (SC) (2) key equation solving module, generally adopt and be convenient to improved euclidean (MEA) algorithm realized in hardware.(3) errors present and error value solving module adopt money search (Chien Search) algorithm to find the solution errors present, adopt good fortune Buddhist nun (Forney) algorithm to carry out finding the solution of improper value.(4) metadata cache, control and error correction output module.This algorithm is applicable to the processing of optical communication high speed data (10/40Gbit/s etc.), realizes with application-specific integrated circuit (ASIC) (ASIC) technology.But adopt this technology in now as GPON, have following problem: 1) the syndrome computing module adopts the data/address bus in a byte broadband, adopts wideer bus to reduce clock rate and the middle realization of programmable gate array (FPGA) is normal at the scene.As the line speed of 2.5Gbit/s, adopt 32 buses, clock frequency is 77.76MHz.2) the ME algoritic module of finding the solution key equation is to take the maximum modules of logical resource, will adopt 4 parallel processing modules under 32 bus situations, and resource consumption is bigger.

Summary of the invention

The technical issues that need to address of the present invention provide a kind of Reed-Solomon sign indicating number decoder, can reduce the ME algoritic module that needs, further can be with wideer bus to reduce the hardware effort clock frequency.

Above-mentioned technical problem of the present invention solves like this, a kind of Reed-Solomon sign indicating number decoder is provided, comprise from being input to the syndrome computing module that output is electrically connected successively, the MEA algoritic module, the money search module, data buffering module between good fortune Buddhist nun's algoritic module and error correction output module and input and the described error correction output module, described input is multibyte bus input, and described MEA algoritic module comprises that one or more reduce by half time-sharing multiplexs that are used for of iterations separately of merging that pass through that are connected in parallel between described syndrome computing module and the money search module handle 8 MEA algorithm submodules that 16 bit data are separately imported.

According to decoder provided by the invention, described MEA algoritic module also comprises one or more processing common 8 MEA algorithm submodules of 8 bit data inputs separately that are connected in parallel between described syndrome computing module and the money search module, as: decoder (two).

According to decoder provided by the invention, described decoder includes, but are not limited to following three kinds:

Decoder (one), described multibyte is four bytes, and described MEA algoritic module is that two reduce by half time-sharing multiplexs that are used for of iterations separately of merging that pass through that are connected in parallel between described syndrome computing module and the money search module are handled 8 MEA algorithm submodules of 16 bit data input separately.

Decoder (two), described multibyte is three bytes, described MEA algoritic module is two 8 MEA algorithm submodules that are connected in parallel between described syndrome computing module and the money search module, wherein at least one is used for realizing time-sharing multiplex by the merging iterations that reduces by half, processing 16 a bit data input that realizes time-sharing multiplex, another realization or do not realize time-sharing multiplex be used to handle remaining 8 bit data input.

Decoder (three), described multibyte are two bytes, described MEA algoritic module be one by reduce by half 8 the MEA algorithm submodules that time-sharing multiplex is handled 16 bit data inputs that are used for of iterations of merging.

According to decoder provided by the invention, described 8 MEA algorithm submodules comprise control unit, polynomial computation unit and grade estimation unit, wherein: between described control unit and the polynomial computation unit and two-way electrical connection between described polynomial computation unit and the grade estimation unit.But described 8 MEA algorithm submodules comprise 8 MEA algorithm submodules of common 8 MEA algorithm submodules and time-sharing multiplex, and their hardware cells are identical, only are algorithm (software) differences.

According to decoder provided by the invention, described merging reduces by half separately, and iterations realization time-sharing multiplex concrete way is: the computing cycle of each iterative computation of ME algorithm is 16, need 16 iteration to finish calculating under the worst case, the time delay of therefore finding the solution key equation is 256 clock cycle.Under worst case, R _i(x) and Q _i(x) the following variation of high reps of multinomial: $\left(\mathrm{16,15}\right)\stackrel{1}{\→}\left(\mathrm{15,15}\right)\stackrel{2}{\→}\left(\mathrm{14,15}\right)$

$\stackrel{3}{\→}\left(\mathrm{14,14}\right)\stackrel{4}{\→}\left(\mathrm{13,14}\right)\stackrel{5}{\→}\left(\mathrm{13,13}\right)\stackrel{6}{\→}\left(\mathrm{12,13}\right)\stackrel{7}{\→}\left(\mathrm{12,12}\right)\stackrel{8}{\→}$

$\left(\mathrm{11,12}\right)\stackrel{9}{\→}\left(\mathrm{11,11}\right)\stackrel{10}{\→}\left(\mathrm{10,11}\right)\stackrel{11}{\→}\left(\mathrm{10,10}\right)\stackrel{12}{\→}\left(\mathrm{9,10}\right)\stackrel{13}{\→}\left(\mathrm{9,9}\right)$

$\stackrel{14}{\→}\left(\mathrm{8,9}\right)\stackrel{15}{\→}\left(\mathrm{8,8}\right)\stackrel{16}{\→}\left(\mathrm{7,8}\right).$ Therefrom as can be seen the 2nd, 4 ..., 16 times iteration is just done computing, does not have the process of exchange.(from iterative formula, can see, if deg is (R _I-1(x))＜deg (Q _I-1(x)), R then _i(x) and Q _i(x) need exchange, carry out computing then.) so the 2nd, 4 ..., 16 times iteration can be the 1st, 3,5 ..., direct computing on 15 iteration results' the basis, and need not be synchronous again, exchange.Through after such processing, the maximum delay of ME module is 8 iteration only just.Polynomial high reps following variation under worst case in these 8 iteration: $\left(\mathrm{16,15}\right)$

$\stackrel{1}{\→}\left(\mathrm{14,15}\right)\stackrel{2}{\→}\left(\mathrm{13,14}\right)\stackrel{3}{\→}\left(\mathrm{12,13}\right)\stackrel{4}{\→}\left(\mathrm{11,12}\right)\stackrel{5}{\→}\left(\mathrm{10,11}\right)\stackrel{6}{\→}\left(\mathrm{9,10}\right)$

$\stackrel{7}{\→}\left(\mathrm{8,9}\right)\stackrel{8}{\→}\left(\mathrm{7,8}\right).$ The following variation of polynomial memory space length: $16\stackrel{1}{\→}16\stackrel{2}{\→}$ $15\stackrel{3}{\→}14\stackrel{4}{\→}13\stackrel{5}{\→}12\stackrel{6}{\→}11\stackrel{7}{\→}10\stackrel{8}{\→}9.$ Adopt the shift register of every grade of band output tap, then every iteration once, the fixedly progression that the use progression of shift register subtracts one, iteration is 11 grades, therefore total delay is 119 (16+16+15+14+13+12+11+11+11).A code word in the cycle, this module can be carried out twice derivation like this.

According to decoder provided by the invention, described syndrome computing module is a syndrome computing module that adopts multibyte parallel computation mode, and described multibyte is consistent with described bus input; The bit wide conversion is avoided in this calculating, does not need a plurality of computing modules, and the number of logic cells that is consumed reduces, and the processing delay of data reduces.

According to decoder provided by the invention, described syndrome computing module includes, but are not limited to 32 of corresponding decoder (), 24 or 16 syndrome computing modules of decoder (three) of decoder (two).

According to decoder provided by the invention, described money search module, good fortune Buddhist nun's algoritic module and error correction output module are to be formed in parallel by a plurality of 8 corresponding submodules that are used for parallel processing consistent with multibyte, can be to cooperate 4 of decoder (), 3 or 28 corresponding submodules of decoder (three) of decoder (two).

According to decoder provided by the invention, described decoder application is in the GPON network.

According to decoder provided by the invention, described decoder is realized by field programmable gate array or application-specific integrated circuit (ASIC).

According to decoder provided by the invention, a described byte is 8 a/bit.

A kind of Reed-Solomon sign indicating number decoder provided by the invention, merge the iterations that reduces by half and improve existing MEA algorithm realization time-sharing multiplex, further adopt parallel syndrome to calculate, saved hardware resource, reduced complexity, make this decoder can save the hardware logic resource during greater than a byte, obtained the effect of saving circuit resource, reducing design difficulty in the bus broadband.

Description of drawings

Further the present invention is described in detail below in conjunction with the drawings and specific embodiments.

Fig. 1 is a RS decoder application schematic diagram.

Fig. 2 is a RS decoder circuit structural representation.

Fig. 3 is traditional syndrome and MEA algorithm structure figure.

Fig. 4 is syndrome and the MEA algorithm structure figure among the present invention.

Fig. 5 is a RS decoder circuit structural representation.

Fig. 6 is RS decoder input/output interface figure shown in Figure 5

Fig. 7 is 32 syndrome computing module input/output interface figure among Fig. 5.

Fig. 8 is syndrome polynomial computation figure.

Fig. 9 is 32 parallel-by-bit syndrome computing module circuit unit schematic diagrames among Fig. 5.

Figure 10 is a MEA algorithm submodule interface schematic diagram among Fig. 5.

Figure 11 is MEA algorithm submodule figure among Fig. 5.

Figure 12 is a money searching algorithm submodule interface schema among Fig. 5.

Figure 13 is a good fortune Buddhist nun algorithm submodule interface schematic diagram among Fig. 5.

Embodiment

At first, basis-decoding algorithm of the present invention is described:

For RS (255,239) coding, its generator polynomial is $G\left(x\right)=\underset{j=0}{\overset{15}{\mathrm{\Π}}}(x-{\mathrm{\α}}^j).$ α produces GF (2 ⁸) primitive polynomial p (the x)=x in territory ⁸+ x ⁴+ x ³+ x ²+ 1 root.

The syndrome calculating formula is

$S_j=R\left({\mathrm{\α}}^i\right)=\underset{i=0}{\overset{254}{\mathrm{\Σ}}}{R}_i{\left({\mathrm{\α}}^j\right)}^i,0\≤j\≤15$

Find the solution the ME algorithm of key equation

Key equation:

S(x)·σ(x)＝ω(x)mod?x ¹⁶

Wherein, $\mathrm{\σ}\left(x\right)={\mathrm{\Π}}_{l=0}^7(1-X_{l}x)$ Be error location polynomial, $S\left(x\right)=\underset{j=0}{\overset{15}{\mathrm{\Σ}}}{S}_j{x}^j$ Be the syndrome multinomial, ω (x) is the erroneous calculations multinomial.Under the known situation of S (x), adopt the ME algorithm to find the solution ω (x) and σ (x).Algorithm is as follows:

Initialization

R ₀(x)＝x ^2t；Q ₀(x)＝S(x)；L ₀(x)＝0；U ₀(x)＝1.

Next begin iteration:

$R_i\left(x\right)=[{\mathrm{\σ}}_{i-1}{b}_{i-1}{R}_{i-1}\left(x\right)+{\stackrel{\‾}{\mathrm{\σ}}}_{i-1}{a}_{i-1}{Q}_{i-1}\left(x\right)]-x^{\left|1_{i-1}\right|}[{\mathrm{\σ}}_{i-1}{a}_{i-1}{Q}_{i-1}\left(x\right)+{\stackrel{\‾}{\mathrm{\σ}}}_{i-1}{b}_{i-1}{R}_{i-1}\left(x\right)]$

$Q_i\left(x\right)={\mathrm{\σ}}_{i-1}{Q}_{i-1}\left(x\right)+{\stackrel{\‾}{\mathrm{\σ}}}_{i-1}{R}_{i-1}\left(x\right)$

$L_i\left(x\right)=[{\mathrm{\σ}}_{i-1}{b}_{i-1}{L}_{i-1}\left(x\right)+{\stackrel{\‾}{\mathrm{\σ}}}_{i-1}{a}_{i-1}{U}_{i-1}\left(x\right)]-x^{\left|1_{i-1}\right|}[{\mathrm{\σ}}_{i-1}{a}_{i-1}{U}_{i-1}\left(x\right)+{\stackrel{\‾}{\mathrm{\σ}}}_{i-1}{b}_{i-1}{L}_{i-1}\left(x\right)]$

$U_i\left(x\right)={\mathrm{\σ}}_{i-1}{U}_{i-1}\left(x\right)+{\stackrel{\‾}{\mathrm{\σ}}}_{i-1}{L}_{i-1}\left(x\right)$

Wherein, a _I-1, b _I-1Be R _I-1(x) and Q _I-1The coefficient of high reps (x).And

l _i-1＝deg(R _i-1(x))-deg(Q _i-1(x))

${\mathrm{\&sigma;}}_{i-1}=\left\{\begin{array}{c}1;\mathrm{if}{1}_{i-1}\&GreaterEqual;0\\ 0;\mathrm{if}{1}_{i-1}<0\end{array}\right.$

Deg () represents polynomial number of times.

If deg (R after each iteration _iOr deg (Q (x)) _i(x)) less than 8, then algorithm iteration finishes.This moment ω (x)=R _i(x) σ (x)=L _i(x)

In second step, key of the present invention is described:

(1) MEA algoritic module

ME algorithm to key equation solving is improved on the basis of the streamline loop iteration algorithm of routine, make this module can be by two decoding process time-sharing multiplexs, calculate with 4 road MEA below time-sharing multiplex processing how to carry out the MEA algorithm is described: (data are imported in the following manner, ' 0 ' represents that this byte is filled to 0 value, R ₂₅₄To R ₀Be a coding codeword)

0 R ₂₅₁……R ₃ 0 R ₂₅₁……R ₃……

R ₂₅₄ R ₂₅₀……R ₂ R ₂₅₄ R ₂₅₀…… R ₂……

R ₂₅₃ R ₂₄₉……R ₁ R ₂₅₃ R ₂₄₉…… R ₁……

R ₂₅₂ R ₂₄₈……R ₀ R ₂₅₂ R ₂₄₈…… R ₀……

The computing cycle of each iterative computation of ME algorithm is 16, needs 16 iteration to finish calculating under the worst case, and the time delay of therefore finding the solution key equation is 256 clock cycle.Under worst case, R _i(x) and Q _i(x) the following variation of high reps of multinomial: $\left(\mathrm{16,15}\right)\stackrel{1}{\&RightArrow;}\left(\mathrm{15,15}\right)\stackrel{2}{\&RightArrow;}\left(\mathrm{14,15}\right)\stackrel{3}{\&RightArrow;}$

$\left(\mathrm{14,14}\right)\stackrel{4}{\&RightArrow;}\left(\mathrm{13,14}\right)\stackrel{5}{\&RightArrow;}\left(\mathrm{13,13}\right)\stackrel{6}{\&RightArrow;}\left(\mathrm{12,13}\right)\stackrel{7}{\&RightArrow;}\left(\mathrm{12,12}\right)\stackrel{8}{\&RightArrow;}\left(\mathrm{11,12}\right)$

$\stackrel{9}{\&RightArrow;}\left(\mathrm{11,11}\right)\stackrel{10}{\&RightArrow;}\left(\mathrm{10,11}\right)\stackrel{11}{\&RightArrow;}\left(\mathrm{10,10}\right)\stackrel{12}{\&RightArrow;}(9,10)\stackrel{13}{\&RightArrow;}(9,9)\stackrel{14}{\&RightArrow;}\left(\mathrm{8,9}\right)$

$\stackrel{15}{\&RightArrow;}\left(\mathrm{8,8}\right)\stackrel{16}{\&RightArrow;}\left(\mathrm{7,8}\right).$ Therefrom as can be seen the 2nd, 4 ..., 16 times iteration is just done computing, does not have the process of exchange.(from iterative formula, can see, if deg is (R _I-1(x))＜deg (Q _I-1(x)), R then _i(x) and Q _i(x) need exchange, carry out computing then.) so the 2nd, 4 ..., 16 times iteration can be the 1st, 3,5 ..., direct computing on 15 iteration results' the basis, and need not be synchronous again, exchange.Through after such processing, the maximum delay of ME module is 8 iteration only just.Polynomial high reps following variation under worst case in these 8 iteration: $\left(\mathrm{16,15}\right)\stackrel{1}{\&RightArrow;}\left(\mathrm{14,15}\right)\stackrel{2}{\&RightArrow;}\left(\mathrm{13,14}\right)$

$\stackrel{3}{\&RightArrow;}\left(\mathrm{12,13}\right)\stackrel{4}{\&RightArrow;}\left(\mathrm{11,12}\right)\stackrel{5}{\&RightArrow;}\left(\mathrm{10,11}\right)\stackrel{6}{\&RightArrow;}\left(\mathrm{9,10}\right)\stackrel{7}{\&RightArrow;}\left(\mathrm{8,9}\right)\stackrel{8}{\&RightArrow;}(7,8).$

The following variation of polynomial memory space length: $16\stackrel{1}{\&RightArrow;}16\stackrel{2}{\&RightArrow;}$ $15\stackrel{3}{\&RightArrow;}14\stackrel{4}{\&RightArrow;}13\stackrel{5}{\&RightArrow;}12\stackrel{6}{\&RightArrow;}11\stackrel{7}{\&RightArrow;}10\stackrel{8}{\&RightArrow;}9.$ Adopt the shift register of every grade of band output tap, then every iteration once, the fixedly progression that the use progression of shift register subtracts one, iteration is 11 grades, therefore total delay is 119 (16+16+15+14+13+12+11+11+11).A code word in the cycle, this module can be carried out twice derivation like this, as under the situation of 32 bus datas inputs, needs 4 ME computing modules with conventional method, uses improved algorithm only to need 2 computing modules.

(2) syndrome module

Traditional syndrome calculates and adopts byte/8 bit serials input calculation mode, and when input data rate was 2.5Gb/s, the clock frequency of processing was 311MHz, and difficulty is very big in hardware designs.If the data/address bus broadening is reduced the processing clock frequency, as be converted to 4 bytes/32 bit bus, clock frequency is reduced to 77.76MHz, by traditional method, as shown in Figure 3, need to increase this moment and be used for 32 data are converted to 8 bit wide translation circuit 31, and 48 syndrome computing modules 32 of needs, and the while also needs 48 MEA algoritic modules 33, that is: the calculating of syndrome additionally needs many computing modules, the number of logic cells that is consumed is many, and the processing delay of data reduces simultaneously.

Among the present invention, in the syndrome computing module, the calculating of syndrome adopts the direct parallel computation of multibyte parallel computation mode to avoid the bit wide conversion, does not need the bit wide translation circuit, also only needs a computing module.

Therefore, in conjunction with key of the present invention () and (two), corresponding diagram 3 shown devices, corresponding intrument of the present invention comprise the MEA algorithm submodule 41 of 32 syndrome computing modules 21 and two the present invention's energy time-sharing multiplexs as shown in Figure 4.

At last, the RS decoder of the present invention in conjunction with the input of nybble bus describes the present invention in detail:

As shown in Figure 2, this RS decoder comprises from being input to 32 syndrome computing modules 21, MEA algoritic module 22, money search module 23, good fortune Buddhist nun's algoritic module 24 and error correction output module 25 that output is electrically connected successively and the data buffering fifo module 26 between input and the described error correction output module 25;

This RS decoder particular circuit configurations as shown in Figure 5, wherein: MEA algoritic module 22 is formed in parallel by 8 MEA algorithm submodules 41 of two energy time-sharing multiplexs, money search module 23 is formed in parallel by four 8 search submodules 231, good fortune Buddhist nun's algoritic module 24 is formed in parallel by four 8 good fortune Buddhist nun algorithm submodules 241, and error correction output module 25 is formed in parallel by four 8 error correction output sub-modules 251.

This RS decoder input/output interface as shown in Figure 6, wherein:

Input interface:

Clk: system clock

A_rst: asynchronous reset signal

Code_vld: the data useful signal, with the same width of valid data

Data_start: the data commencing signal occurs simultaneously with first valid data

Rn:32 bit data input, the most-significant byte of first data of each code word is 0 (as filling), last 16 bytes are error correction encoded data.

Output interface:

Right: pulse output signals, expression receives a correct code word

Fail: pulse output signals, expression receives the code word that a mistake exceeds error correcting capability, former state output

Dout_vld: data output useful signal, with the same width of effective output code word

Dout_start: data output commencing signal occurs simultaneously with first effective dateout

The output of Dout:32 bit data, first byte of each code word is not valid data, only exports 239 byte valid data.

In this RS decoder 32 syndrome computing module 21 input/output interfaces as shown in Figure 7, wherein, 32 input interface Rn are exactly the input interface of decoder; Export R, S, L, U corresponding R respectively for 8 ₀(x), S ₀(x), L ₀(x) and U ₀(x), be the required initial value of ME algoritic module.Owing to have only the syndrome multinomial to need to calculate, other is fixed value output, calculates so this module functions is a syndrome; 32 syndrome computing module circuit as shown in Figure 8, wherein the particular circuit configurations of each computing unit S0～S15 as shown in Figure 9, wherein plus sige is an XOR, multiplication sign is the finite field multiplier computing; " select " signal be used for computing and finish after 16 coefficients of serial output associated polynomial; " select2 " signal is used for result of calculation directly being sent into register in first input of each code word during data, thereby avoids the register clear operation of a clock cycle.Finite field multiplier computing " * α ⁱ" be definite value to each syndrome index " i ", can be reduced to the add operation of finite field according to operation rule.

MEA algorithm submodule 41 input/output interfaces as shown in figure 10 in this RS decoder, the result of calculation of the associated polynomial of 32 syndrome computing modules is delivered to two MEA algorithm submodules 41 in turn and is found the solution key equation, and wherein input signal comes from the output of the syndrome computing module of prime.In the output signal, X0 ..., X8 is the polynomial coefficient of σ (x) that calculates, W0 ..., W7 is the polynomial coefficient of ω (x) that calculates.Other two output signals are the data output indications to the back level.Two MEA algorithm submodule 41 circuit structures as shown in figure 11, and are consistent with 8 MEA algoritic modules that can not time-sharing multiplex on the hardware, comprise control unit 51, polynomial computation unit 52 and grade estimation unit 53.

Money searching algorithm submodule 23l input/output interface as shown in figure 12 in this RS decoder, the data of each MEA algorithm submodule 41 output are delivered in the follow-up money searching algorithm of two-way submodule 231 and the Fu Ni algorithm submodule 241 in turn, wherein importing data is X0, X8, signal " start " be used to indicate the beginning of input data; Dateout " Xout " expression σ (α ⁱ) result of calculation, represent that when it equals 0 correspondence position is wrong.Dateout " deriXout ", represent x σ ' (x) | _{X=α i}Result of calculation provides good fortune Buddhist nun algoritic module to use.Dateout " err " represents that this code word comprises the code word that exceeds error correcting capability.Exceeding the code word that error correcting capability uses judges with following method: the polynomial high reps of input σ (x) equates that with the errors present number then this code word then contains the mistake that can not correct as not waiting in the error correction scope.

In this RS decoder good fortune Buddhist nun algorithm submodule 241 input/output interfaces as shown in figure 13, wherein importing data is W0 ..., W8, signal " and start " be used to indicate the beginning of input data.Dateout " errorvalue " expression improper value.

Claims (10)

1, a kind of Reed-Solomon sign indicating number decoder, comprise from being input to the syndrome computing module that output is electrically connected successively, MEA algoritic module (22), money search module (23), data buffering module (26) between good fortune Buddhist nun's algoritic module (24) and error correction output module (25) and input and the described error correction output module, it is characterized in that, described input is multibyte bus input, and described MEA algoritic module (22) comprises that one or more reduce by half time-sharing multiplexs that are used for of iterations separately of merging that pass through that are connected in parallel between described syndrome computing module and the money search module (23) handle 8 MEA algorithm submodules (41) that 16 bit data are separately imported.

2, according to the described decoder of claim 1, it is characterized in that, described multibyte is four bytes, and described MEA algoritic module (22) is that two reduce by half time-sharing multiplexs that are used for of iterations separately of merging that pass through that are connected in parallel between described syndrome computing module and the money search module are handled 8 MEA algorithm submodules (41) of 16 bit data input separately.

3, according to the described decoder of claim 1, it is characterized in that, described multibyte is three bytes, described MEA algoritic module (22) is two 8 MEA algorithm submodules that are connected in parallel between described syndrome computing module and the money search module, wherein at least one (41) are used for realizing time-sharing multiplex by the merging iterations that reduces by half, what processing 16 a bit data input that realizes time-sharing multiplex, another realization (41) or did not realize (33) time-sharing multiplex is used to handle remaining 8 bit data input.

4, according to the described decoder of claim 1, it is characterized in that, described multibyte is two bytes, described MEA algoritic module (22) be one by reduce by half 8 the MEA algorithm submodules (41) that time-sharing multiplex is handled 16 bit data inputs that are used for of iterations of merging.

5, according to each described decoder of claim 1-4, it is characterized in that, described 8 MEA algorithm submodules (41 or 33) comprise control unit, polynomial computation unit and grade estimation unit, wherein: between described control unit and the polynomial computation unit and two-way electrical connection between described polynomial computation unit and the grade estimation unit.

According to the described decoder of claim 1, it is characterized in that 6, described syndrome computing module is a syndrome computing module that adopts multibyte parallel computation mode, described multibyte is consistent with described bus input.

According to the described decoder of claim 2, it is characterized in that 7, described syndrome computing module can be 16,24 or 32 syndrome computing modules (21).

According to the described decoder of claim 1, it is characterized in that 8, described money search module (23), good fortune Buddhist nun's algoritic module (24) and error correction output module (25) are to be formed in parallel by a plurality of 8 corresponding submodules that are used for parallel processing consistent with multibyte.

According to the described decoder of claim 1, it is characterized in that 9, described decoder (12) is applied in the GPON network.

According to the described decoder of claim 1, it is characterized in that 10, described decoder (12) is realized by field programmable gate array or application-specific integrated circuit (ASIC).

Images