CN102857234A - Reed Solomon decoder and decoding method - Google Patents
Reed Solomon decoder and decoding method Download PDFInfo
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Abstract
The invention discloses a Reed Solomon decoder and a decoding method. The decoder comprises a syndrome computation module, a decoding FIFO (first in first out) memorizer, a solving key equation module and a Chien searching and miscalculation module, wherein the syndrome computation module is provided with 2T syndrome calculation subunits and is used for generating 2T syndrome multinomial coefficients according to code current to be decoded, and the decoding FIFO memorizer is used for buffering the code current to be decoded; the solving key equation module is used for obtaining an error position polynomial coefficient and an error value polynomial coefficient; and the Chien searching and miscalculation module is used for calculating an error value and an error location, and can carry out error correction on the code current to be buffered in the decoding FIFO memorizer according to the error value and the error location so as to generate the code current after decoding. The Reed Solomon decoder provided by the invention has the advantages that the time delay between the input and output of data is small, and the error correction digit is configurable. The decoding method provided by the invention has the advantages that the decoding speed is rapid, and the decoding efficiency is high.
Description
Technical field
The present invention relates to the encoding and decoding technique field, particularly a kind of Reed Solomon decoder and coding/decoding method.
Background technology
Integrated circuit has developed on the single chips of being integrated in of the telotism of one or more systems, becomes system level chip (System on a Chip is referred to as SoC).Along with the progress of semiconductor technology, and market is to the lifting of high-performance, high integration, low-power consumption, low-cost chip demand, and the integrated level of SoC improves constantly.Satisfy the requirement of multiple application, portable good, reusable standard I P will save time and cost for the exploitation of SOC.Industry has been generally acknowledged the important technology that has become complicated SoC design based on IP (Intellectual Property is hereinafter to be referred as IP) multiplex technique.This designing technique is on a large amount of standard I P module integration to a chip that producer is provided, and makes it to form the system of an independent completion.
In the fields such as memory device, radio communication, Digital Television, satellite communication, Reed Solomon encoding and decoding extensive use.Yet the shortcoming of existing Reed Solomon encoding and decoding is, the input and output of data postpone larger, and the error correction figure place can not configure.
Summary of the invention
The present invention is intended to one of solve the problems of the technologies described above at least.
For this reason, one object of the present invention is to propose a kind of Reed Solomon decoder, and this decoder has little, the configurable advantage of error correction figure place of time delay between the input of data and the output.
Another object of the present invention is to propose the Reed Solomon coding/decoding method that a kind of error correction figure place is configurable, code is very easily expanded, the method has advantages of that decoding speed is fast.
To achieve these goals, the Reed Solomon decoder that first aspect present invention embodiment proposes, comprise: the syndrome computing module, described syndrome computing module has 2T syndrome computation subunit, wherein, T is the error correction number of characters, and described syndrome computing module is used for generating 2T syndrome multinomial coefficient according to code stream to be decoded; Decoding FIFO memory, described decoding FIFO memory is used for described code stream to be decoded is carried out buffer memory; Find the solution the key equation module, the described key equation module of finding the solution is for coefficient and the polynomial coefficient of improper value of 2T the syndrome multinomial coefficient acquisition error location polynomial that generates according to described syndrome computing module; With chien search and erroneous calculations module, described chien search and erroneous calculations module are used for according to described coefficient of finding the solution the error location polynomial that the key equation module obtains and the polynomial coefficient of improper value respectively mistake in computation value and errors present, and according to described improper value and errors present the code stream to be decoded of buffer memory in the described decoding FIFO memory are carried out error correction to generate decoded code stream.
Reed Solomon decoder according to the embodiment of the invention, by default error correction figure place T, stream to be decoded calculates 2T syndrome multinomial coefficient with 2T syndrome computation subunit respectively in the syndrome computing module, then find the solution the key equation module and calculate error location polynomial and the polynomial coefficient of improper value according to this 2T syndrome multinomial coefficient, then chien search and erroneous calculations module obtain improper value and errors present according to this error location polynomial and the polynomial coefficient calculations of improper value, at last the stream to be decoded that is buffered in the decoding FIFO memory is carried out error correction, thereby obtain decoding rear code stream.Can be to default error correction figure place flexible configuration by this decoder, thus can realize the various error correcting of this decoder, and the input of this decoder with data with export between time delay little.
The Reed Solomon coding/decoding method of second aspect present invention embodiment may further comprise the steps: treat decoded bit stream and carry out buffer memory; Generate 2T syndrome multinomial coefficient according to described code stream to be decoded; Obtain coefficient and the polynomial coefficient of improper value of error location polynomial according to described 2T syndrome multinomial coefficient; Coefficient and the polynomial coefficient difference mistake in computation value of improper value and errors present according to described error location polynomial; With according to described improper value and errors present the code stream to be decoded of described buffer memory is carried out error correction to generate decoded code stream.
According to the Reed Solomon coding/decoding method of the embodiment of the invention, can carry out flexible configuration and have advantages of that code very easily expands the error correction figure place.In addition, the input that the method is treated before and after the decoding of decoded stream is relatively short with the time delay between the output, and then the raising decoding efficiency.
The aspect that the present invention adds and advantage in the following description part provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Description of drawings
Above-mentioned and/or the additional aspect of the present invention and advantage are from obviously and easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:
Fig. 1 is the structure chart of the Reed Solomon decoder of the embodiment of the invention;
Fig. 2 is the structure chart of the syndrome computing module of the embodiment of the invention;
Fig. 3 is the structure chart of function calculating subelement of the syndrome computing module of the embodiment of the invention;
Fig. 4 is the structure chart of finding the solution the key equation module of the embodiment of the invention;
Fig. 5 is the structure chart of the first kind iterative processing unit of finding the solution the key equation module of the embodiment of the invention;
Fig. 6 is the structure chart of the Equations of The Second Kind iterative processing unit of finding the solution the key equation module of the embodiment of the invention;
Fig. 7 is the structure chart of the 3rd class iterative processing unit of finding the solution the key equation module of the embodiment of the invention;
Fig. 8 is the chien search of the embodiment of the invention and the structure chart of erroneous calculations module;
Fig. 9 is the structure chart of the chien search computing unit 0 of the embodiment of the invention;
Figure 10 is the structure chart of the chien search computing unit 1 to T of the embodiment of the invention;
Figure 11 is the structure chart of good fortune Buddhist nun's formula computing unit 0 of the embodiment of the invention;
Figure 12 is the structure chart of good fortune Buddhist nun's formula computing unit 1 to T-1 of the present invention;
Figure 13 is the state configuration and conversion schematic diagram of decoder master controller of the present invention; With
Figure 14 is the flow chart of the Reed Solomon coding/decoding method of the embodiment of the invention,
Wherein, the t shown in Fig. 2, Fig. 4 and Fig. 8 is the error correction number of characters.
Embodiment
The below describes embodiments of the invention in detail, and the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or the element with identical or similar functions from start to finish.Be exemplary below by the embodiment that is described with reference to the drawings, only be used for explaining the present invention, and can not be interpreted as limitation of the present invention.
In description of the invention, need to prove, unless clear and definite regulation and restriction are arranged in addition, term " installation ", " linking to each other ", " connection " should be done broad understanding, for example, can be to be fixedly connected with, and also can be to removably connect, or connect integratedly; Can be mechanical connection, also can be to be electrically connected; Can be directly to link to each other, also can indirectly link to each other by intermediary, can be the connection of two element internals.For the ordinary skill in the art, can concrete condition understand above-mentioned term concrete meaning in the present invention.
Below in conjunction with accompanying drawing 1-13 Reed Solomon decoder according to the embodiment of the invention is described at first.
As shown in Figure 1, be the structure chart of the Reed Solomon decoder of the embodiment of the invention.Reed Solomon decoder 100 according to the embodiment of the invention comprises syndrome computing module 110, decoding FIFO memory 120, finds the solution key equation module 130 and chien search and erroneous calculations module 140.
Decoding FIFO memory 120 is used for described code stream to be decoded is carried out buffer memory.In the time of needs code stream to be decoded, the speed that obtains code stream to be decoded from decoding FIFO memory 120 is fast, saves time.
Find the solution key equation module 130 for coefficient and the polynomial coefficient of improper value of 2T the syndrome multinomial coefficient acquisition error location polynomial that generates according to described syndrome computing module 110.As a concrete example, in examples more of the present invention, find the solution key equation module 130 and can adopt the RiBM algorithm to carry out iterative computation, thereby obtain coefficient and the polynomial coefficient of improper value of error location polynomial.
Chien search and erroneous calculations module 140 is used for according to described coefficient of finding the solution the error location polynomial that key equation module 130 obtains and the polynomial coefficient of improper value respectively mistake in computation value and errors present, and according to described improper value and errors present the code stream to be decoded of buffer memory in the described decoding FIFO memory 120 carried out error correction to generate decoded code stream.
Reed Solomon decoder 100 according to the embodiment of the invention, by default error correction figure place T, stream to be decoded calculates 2T syndrome multinomial coefficient with 2T syndrome computation subunit respectively in syndrome computing module 110, then find the solution key equation module 130 and calculate error location polynomial and the polynomial coefficient of improper value according to this 2T syndrome multinomial coefficient, then chien search and erroneous calculations module 140 obtain improper value and errors present according to this error location polynomial and the polynomial coefficient calculations of improper value, at last the stream to be decoded that is buffered in the decoding FIFO memory 110 is carried out error correction, thereby obtain decoding rear code stream.Can carry out flexible configuration to default error correction figure place T by this decoder 100, thereby can realize the various error correcting of this decoder, and the input of this decoder with data with export between time delay little, and then improved decoding efficiency.
As a concrete example, the Reed Solomon decoder of the embodiment of the invention for example also comprises decoder master controller 150.Decoder master controller 150 links to each other with erroneous calculations module 140 with described chien search with decoding FIFO memory 120, syndrome computing module 110, the described key equation module 130 of finding the solution respectively, and 110 of sub-computing moulds, described 150 collaborative work of key equation module 130, described chien search and erroneous calculations module 140 and the described FIFO of decoding memory module and the state of input and output of finding the solution are followed in the control that act as of this decoder master controller 150.For example, when control starts, stops the operation of above-mentioned modules etc.Like this, by the control of decoder master controller 150, can guarantee the continual execution of each functional module, improve decoding efficiency.Simultaneously, when each functional module does not have data to process, can stop the operation of the corresponding function module, and then reduce energy consumption.
Each functional module to the Reed Solomon decoder of the embodiment of the invention is described in detail as follows:
As shown in Figure 2, be the structure chart of the syndrome computing module of the embodiment of the invention.
In conjunction with Fig. 1, in one embodiment of the invention, this syndrome computing module 110 can also be according to the result of calculation generation error flag bit of 2T syndrome computation subunit (syndrome computing unit 0 is to syndrome computing unit 2T-1).For example, syndrome computing unit 0 to 2T the result of calculation (the polynomial coefficient of syndrome) of syndrome computing unit 2T-1 if entirely be 0 value, then thinking does not have mistake, at this moment, corresponding error flag position 0, if 2T result of calculation is not 0 value partly wherein, then error flag position correspondence position is put 1.
In conjunction with Fig. 2, the syndrome computing module 110 of some embodiments of the invention has 2T syndrome computation subunit (syndrome computing unit 0 is to syndrome computing unit 2T-1) and syndrome state machine 210.
T is the error correction number of characters, can be by T be worth pre-configured, realize the different error correcting capability of this decoder, like this, syndrome computing module 110 is with Automatically invoked 2T syndrome computation subunit (syndrome computing unit 0 is to syndrome computing unit 2T-1).Syndrome state machine 210 links to each other with each of 2T syndrome computation subunit, and this syndrome state machine 210 also links to each other with decoder master controller 150.
2T syndrome computation subunit generates 2T syndrome multinomial coefficient according to described code stream to be decoded respectively under the control of described syndrome state machine;
Like this, syndrome state machine 210 receives the control signal that comes from decoder master controller 150 and carries out with it mutual, then control the work schedule of described 2T syndrome computation subunit by the control signal after mutual, as when starting, when stop etc., thus, 2T syndrome computation subunit is under the control of syndrome state machine 150 and utilize code stream to be decoded to generate 2T syndrome multinomial coefficient.
Simultaneously, 2T syndrome computation subunit sends to syndrome state machine 210 with 2T the syndrome multinomial coefficient that generates, thereby judges whether to exist mistake, to generate described error flag position.If 2T syndrome multinomial coefficient is 0 value entirely, then thinking does not have mistake, and at this moment, corresponding error flag position 0 if 2T result of calculation is not 0 value partly wherein, then puts 1 with error flag position correspondence position.
Further, as shown in Figure 3, the syndrome computation subunit includes confinement adder 310, constant term Galois field multiplier 320 and register 330.Constant term Galois field multiplier 320 links to each other with finite field adder 310.Register 330 links to each other with described constant term Galois field multiplier 320 respectively at finite field adder 310.
Constant term Galois field multiplier 320 is used for the syndrome multinomial coefficient of the output of register 330 and default finite field constant are carried out multiplication process.
Register 330 has loading and keeps function, this register 330 is according to loading and the output to the syndrome multinomial coefficient of the control signal of syndrome state machine 210, wherein, when register 330 is inhibit signal in the control signal that receives, the output of maintenance itself is constant, when receiving control signal and be load signal, be used for loading and exporting corresponding syndrome multinomial coefficient.That is to say, register keeps output constant when inhibit signal is effective, loads when load signal is effective and is input to output.
As shown in Figure 4, be the structure chart of finding the solution the key equation module of the embodiment of the invention.
In conjunction with Fig. 1, in examples more of the present invention, find the solution key equation module 130 and comprise 2T first kind iterative processing unit (first kind iterative processing unit 0 among Fig. 4 is to first kind iterative processing unit 2T-1) that links to each other successively, T Equations of The Second Kind iterative processing unit (the Equations of The Second Kind iterative processing unit 2T among Fig. 4 is to Equations of The Second Kind iterative processing unit 3T-1) that links to each other successively, 1 the 3rd class iterative processing unit and respectively with described first kind iterative processing unit, the solving key equation state machine 410 that Equations of The Second Kind iterative processing unit links to each other with the 3rd class iterative processing unit.
First kind iterative processing unit is used for the control signal according to described solving key equation state machine 410, coefficient and the polynomial coefficient of described improper value of processing to obtain described error location polynomial to the syndrome multinomial coefficient, from delta and the gamma of decoder master controller, wherein, delta and gamma are the intermediate data that produces in the interative computation process, the generation of intermediate data and acquisition all are known in those skilled in the art, do not repeat them here.
Wherein, i processing unit in the first kind iterative processing unit receives the result that comes from described i+1 processing unit, and i is the integer between [0,2T-2].In conjunction with Fig. 4, that is to say, first kind iterative processing unit 0 is to first kind iterative processing unit 2T-1, the output conduct that is in the first kind iterative processing unit of below is in the input of the first kind iterative processing unit of next-door neighbour top, pass successively, until be coefficient and the polynomial coefficient of improper value of error location polynomial from the execution result of first kind iterative processing unit 0.
Equations of The Second Kind iterative processing unit is used for the control signal according to described solving key equation state machine 410, described delta and gamma is processed to upgrade the errors present of stream to be decoded in the iterative process.J processing unit in the described Equations of The Second Kind iterative processing unit receive from the result of described j+1 processing unit, j is [0, T-2] between integer, the result of the 0th processing unit in the described Equations of The Second Kind iterative processing unit sends to 2T-1 processing unit in the described first kind iterative processing unit, and T-1 processing unit in the described Equations of The Second Kind iterative processing unit receives the operation result that comes from the tired processing unit of described the 3rd class.Wherein, Equations of The Second Kind iterative processing unit is exported to described first kind iterative processing unit every a clock cycle with operation result in the interative computation process, i.e. the first kind iterative processing unit 2T-1 adjacent with Equations of The Second Kind iterative processing unit.
Described the 3rd class iterative processing unit is used for the control signal according to described solving key equation state machine 410, data-signal, delta and the gamma (intermediate data) of described solving key equation state machine processed to finish the initialization of described the 3rd class iterative processing unit interative computation desired data, wherein, operation result is exported to T-1 processing unit in the described Equations of The Second Kind iterative processing unit, i.e. Equations of The Second Kind iterative processing unit 3T-1 every a clock cycle in described the 3rd class iterative processing unit in the interative computation process.
Described solving key equation state machine 410 is used for controlling according to the control signal of described decoder master controller 150 operating state of described first kind iterative processing unit, described Equations of The Second Kind iterative processing unit and the 3rd class iterative processing unit.For example, when control first kind iterative processing unit, described Equations of The Second Kind iterative processing unit and the 3rd class iterative processing unit start, and when stop, and can also control in the same class iterative processing unit work schedule of each.
In conjunction with Fig. 4, as can be known, the iterative processing unit that is positioned at the below sends to result the iterative processing unit of the side of being located thereon, like this, the polynomial coefficient of form while mistake in computation position Sum of coefficients of a polynomial improper value with single array, improve and to find the solution the arranging rule of key equation module 130, thereby maintain easily and expand.
More specifically, the structure of first kind iterative processing unit, Equations of The Second Kind iterative processing unit and the 3rd class iterative processing unit is respectively shown in Fig. 5-7.
In conjunction with Fig. 5, Fig. 6 and Fig. 7, apparently, first kind iterative processing unit, Equations of The Second Kind iterative processing unit are identical with the structure of the 3rd class iterative processing unit, and difference is that the parameter of inputting is different, and the result of output is different.Take Fig. 5 as example, first kind iterative processing unit comprises MUX 510, the register 520 with loading, maintenance, function of initializing, Galois field multiplier 530 and finite field adder 540.Advantageously, Galois field multiplier 530 is Bit Parallel Multiplier, like this, can reduce the door number of multiplier, thereby reduce computation complexity.
The register 520 that is positioned at the below receives data and the polynomial coefficient of syndrome that is deposited in by MUX, the Galois field multiplier 530 that is positioned at the below links to each other with the register 520 that is positioned at the below, be used for the data and the delta that come from the register 520 that is positioned at the below are carried out finite field multiplier, and operation result is sent to the finite field adder 540 that is attached thereto.The multiplier 530 that is positioned at the top receives data and the gamma (intermediate data) of this processing unit below processing unit, and do multiplication and move, operation result is sent in the adder 540 that is attached thereto equally, 540 pairs of adders come from the data of two multipliers and carry out add operation, deposit the result in be positioned at the top register 520, wait for output.
Significantly, the structure of Equations of The Second Kind iterative processing unit and the 3rd class iterative processing unit is identical with the structure of first kind iterative processing unit, just the parameter of input is different, the as a result difference of final output, and input and output are set forth at above embodiment, in order to reduce redundancy, do not do and give unnecessary details.
In an example of the present invention, error location polynomial is: ∧ (z)=1+ λ
1Z+ λ
2z
2+ ... .+ λ
rz
r
Described improper value multinomial can be expressed as: Ω (z)=ω
0+ ω
1Z+ ω
2z
2+ ... .+ ω
R-1z
R-1
Described key equation polynomial table is shown: ∧ (z) S (z)=Ω (z) mod z
2r,
Wherein, r is the error correction number of characters, and S (z) is the syndrome multinomial, and z is the finite field variable, and λ 1 to λ r is the coefficient of error location polynomial, ω
1To ω
rBe the polynomial coefficient of improper value.
Find the solution key equation module 130 and by the RiBM algorithm above-mentioned error location polynomial, improper value multinomial are carried out iterative computation, thereby obtain coefficient and the polynomial coefficient of improper value of error location polynomial.Adopt the RiBM algorithm to only have the time delay sum of a multiplier and an adder at critical path delay, reduce computing time.In addition, control structure also is simplified.
As shown in Figure 8, be the chien search of the embodiment of the invention and the structure chart of erroneous calculations module.In one embodiment of the invention, this chien search and erroneous calculations module can also be used for coefficient and the polynomial coefficient calculations number of errors of improper value according to described error location polynomial.Change sentence and change, after this chien search and erroneous calculations module calculate the coefficient and the polynomial coefficient of improper value of error location polynomial, then can obtain according to these two coefficient calculations the number of errors of stream to be decoded.In conjunction with Fig. 8, for example this chien search and erroneous calculations module comprise (T+1) individual chien search computing unit (the chien search computing unit 0 among the figure is to chien search computing unit T), a T good fortune Buddhist nun formula computing unit (the good fortune Buddhist nun's formula computing unit 0 beatitude Buddhist nun formula computing unit T-1 among the figure), the chien search and good fortune Buddhist nun formula computing mode machine 810 and the false judgment submodule 820 that link to each other with Fu Ni formula computing unit with described chien search computing unit respectively.
Chien search computing unit 0 is to chien search computing unit T collaborative work under the control of the control signal of chien search and good fortune Buddhist nun formula computing mode machine 810, and according to coming from the coefficient calculations errors present of finding the solution key equation module 130 error location polynomials.
As shown in Figure 9, be the concrete structure figure of chien search computing unit 0.Chien search computing unit 0 comprises a register 910 and a MUX 920.MUX 920 is controlled the coefficient lambda of error location polynomial under the control of chien search and good fortune Buddhist nun formula computing mode machine 810 control signals
0Give register 910.Register 910 is inputted the result of calculation of chien search computing unit 0 under the effect of control signal.
As shown in figure 10, be the concrete structure figure of chien search computing unit 1 to T.Chien search computing unit 1 to T comprises respectively 1 register 1010, constant Galois field multiplier 1020 and MUX 1030.Constant Galois field multiplier 1020 is used for the output of register 1010 and finite field constant are multiplied each other and export operation result to MUX 1030.MUX 1030 is with the coefficient lambda of operation result and the error location polynomial of constant Galois field multiplier 1020
1To λ
TSend to respectively the register 1010 of chien search computing unit 1 to T.The register 1010 of chien search computing unit 1 to T is inputted chien search value 1 to the result of calculation of chien search value T under the effect of control signal.
Good fortune Buddhist nun's formula computing unit 0 beatitude Buddhist nun formula computing unit T-1 is according to the polynomial coefficient calculations improper value of improper value.That is to say, good fortune Buddhist nun's formula computing unit 0 beatitude Buddhist nun formula computing unit T-1 collaborative work under the control of the control signal of chien search and good fortune Buddhist nun formula computing mode machine 810 is then found the solution the polynomial coefficient calculations of key equation module 130 improper values and is obtained improper value according to coming from.As shown in figure 11, be the structure chart of good fortune Buddhist nun formula computing unit 0.The structure of good fortune Buddhist nun formula computing unit 0 is identical with the structure of chien search computing unit 0 as can be known, and what difference was MUX is input as the polynomial coefficient ω of improper value
0, output is also corresponding different.Concrete structure is described referring to above-described embodiment.
As shown in figure 12, arrive the structure chart of T-1 for good fortune Buddhist nun formula computing unit 1.The structure of good fortune Buddhist nun formula computing unit 0 is identical with the structure of chien search computing unit 1-T as can be known.Difference is that the input of MUX is respectively the polynomial coefficient ω of improper value
1To ω
T-1, similarly, output is also corresponding different.Concrete structure is described referring to above-described embodiment.
Described chien search and good fortune Buddhist nun formula computing mode machine 810 are used for controlling according to the control signal of described decoder master controller 150 operating state of described chien search computing unit and described good fortune Buddhist nun's formula computing unit.For example, control the collaborative work of each chien search computing unit and good fortune Buddhist nun formula computing unit, control each chien search computing unit and when good fortune Buddhist nun formula computing unit starts, when stop etc.
Described false judgment module 820 obtains number of errors and exports described improper value, number of errors and errors present according to described errors present and described improper value.
Particularly, false judgment module 820 receives the errors present value that comes from chien search computing unit and Fu Ni formula computing unit and produce (jointly being produced to chien search value T by chien search value 0) and good fortune Buddhist nun formula value (0 beatitude Buddhist nun formula value T obtains jointly by good fortune Buddhist nun formula value).Then false judgment module 820 can be determined according to these two kinds values improper value and then output error value, number of errors and the errors present etc. of stream to be decoded.
In one embodiment of the invention, as shown in figure 13, be the control chart of the decoder master controller 150 of one embodiment of the invention.Decoder master controller 150 each functional modules of control are carried out between 15 states alternately.Like this, guarantee each functional module according to the expection requirement carry out work, increase work efficiency.
Reed Solomon decoder according to the embodiment of the invention, by default error correction figure place T, stream to be decoded calculates 2T syndrome multinomial coefficient with 2T syndrome computation subunit respectively in the syndrome computing module, then find the solution the key equation module and calculate error location polynomial and the polynomial coefficient of improper value according to this 2T syndrome multinomial coefficient, then chien search and erroneous calculations module obtain improper value and errors present according to this error location polynomial and the polynomial coefficient calculations of improper value, at last the stream to be decoded that is buffered in the decoding FIFO memory is carried out error correction, thereby obtain decoding rear code stream.Can be to default error correction figure place flexible configuration by this decoder, thus can realize the various error correcting of this decoder, and the input of this decoder with data with export between time delay little.
Below in conjunction with the Reed Solomon coding/decoding method of accompanying drawing 14 descriptions according to the embodiment of the invention.
As shown in figure 14, be the flow chart of the Reed Solomon coding/decoding method of the embodiment of the invention.Reed Solomon coding/decoding method according to the embodiment of the invention may further comprise the steps:
Step S101 treats decoded bit stream and carries out buffer memory.
Step S102 generates 2T syndrome multinomial coefficient according to described code stream to be decoded.
Step S103 is according to coefficient and the polynomial coefficient of improper value of described 2T syndrome multinomial coefficient acquisition error location polynomial.
In one embodiment of the invention, for example can also generate each and every one syndrome multinomial coefficient generation error flag bit of 2T according to described code stream to be decoded.For example, if 2T the polynomial coefficient of syndrome is 0 value entirely, then thinking does not have mistake, and at this moment, corresponding error flag position 0 if 2T result of calculation is not 0 value partly wherein, then puts 1 with error flag position correspondence position.
Step S104 is according to coefficient and the polynomial coefficient difference mistake in computation value of improper value and the errors present of described error location polynomial.
Particularly, carry out iterative computation to obtain coefficient and the polynomial coefficient of improper value of error location polynomial according to the RiBM algorithm.Wherein, error location polynomial is expressed as: ∧ (z)=1+ λ
1Z+ λ
2z
2+ ... .+ λ rz
r
The improper value polynomial table is shown: Ω (z)=ω
0+ ω
1Z+ ω
2z
2+ ... .+ ω
R-1z
R-1
The key equation polynomial table is shown: ∧ (z) S (z)=Ω (z) mod z
2r
Wherein, r is the error correction number of characters, and S (z) is the syndrome multinomial, and z is the finite field variable, λ
1... λ
rBe the coefficient of error location polynomial, ω
1... ω
rBe the polynomial coefficient of improper value.
Step S105 carries out error correction to generate decoded code stream according to described improper value and errors present to the code stream to be decoded of described buffer memory.
In one embodiment of the invention, this Reed Solomon coding/decoding method also comprises coefficient and the polynomial coefficient calculations number of errors of improper value according to described error location polynomial.
According to the Reed Solomon coding/decoding method of the embodiment of the invention, can carry out flexible configuration and have advantages of that code very easily expands the error correction figure place.In addition, the input that the method is treated before and after the decoding of decoded stream is relatively short with the time delay between the output, and then the raising decoding efficiency.
To sum up, the present invention compared with prior art has the following advantages and effect:
1, the circuit systematicness of the decoder of the embodiment of the invention is good, easily expands.For example, (the error correction number of characters is M, and the change work of doing during M ≠ N) is very little, only need do parameter configuration, will automatically generate desired circuit changed to another kind of error correcting capability by a kind of error correcting capability (the error correction number of characters is N).
2, effectively reduced the gate number that multiplier produces.The algorithm of finding the solution key equation commonly used needs a large amount of Galois field multipliers, and the gate number of Galois field multiplier consumption ratio in the total door of the circuit of finding the solution key equation module number is higher.For this point, adopt low complex degree, Bit Parallel Multiplier, consider from the door number that reduces single multiplier, and then reduce whole total number of finding the solution the multiplier of key equation module.
3, the multiplier of the syndrome computing module of the embodiment of the invention adopts the constant Galois field multiplier, like this, effectively reduced the time of the single position that produces product, thereby the input and output that reduced the syndrome computing module postpones.
4, the time delay of the critical path of finding the solution the key equation module of the embodiment of the invention only has T
Multiplifier+ T
Adder(the time delay sum of a multiplier and an adder).And the time delay of the critical path of traditional BM algorithm without inversion operation (IBM algorithm) is greater than 2 (T
Multiplifier+ T
Adder).The time delay of comparing the critical path of the circuit that euclidean, amended Euclidean algorithm realize is generally T
Multiplifier+ T
Adder+ T
Mux, also significantly reduce.
In the description of this specification, the description of reference term " embodiment ", " some embodiment ", " example ", " concrete example " or " some examples " etc. means to be contained at least one embodiment of the present invention or the example in conjunction with specific features, structure, material or the characteristics of this embodiment or example description.In this manual, the schematic statement of above-mentioned term not necessarily referred to identical embodiment or example.And the specific features of description, structure, material or characteristics can be with suitable mode combinations in any one or more embodiment or example.
Although illustrated and described embodiments of the invention, for the ordinary skill in the art, be appreciated that without departing from the principles and spirit of the present invention and can carry out multiple variation, modification, replacement and modification to these embodiment, scope of the present invention is by claims and be equal to and limit.
Claims (15)
1. a Reed Solomon decoder is characterized in that, comprising:
The syndrome computing module, described syndrome computing module has 2T syndrome computation subunit, and wherein, T is the error correction number of characters, and described syndrome computing module is used for generating 2T syndrome multinomial coefficient according to code stream to be decoded;
Decoding FIFO memory, described decoding FIFO memory is used for described code stream to be decoded is carried out buffer memory;
Find the solution the key equation module, the described key equation module of finding the solution is for coefficient and the polynomial coefficient of improper value of 2T the syndrome multinomial coefficient acquisition error location polynomial that generates according to described syndrome computing module; With
Chien search and erroneous calculations module, described chien search and erroneous calculations module are used for according to described coefficient of finding the solution the error location polynomial that the key equation module obtains and the polynomial coefficient of improper value respectively mistake in computation value and errors present, and according to described improper value and errors present the code stream to be decoded of buffer memory in the described decoding FIFO memory are carried out error correction to generate decoded code stream.
2. Reed Solomon decoder as claimed in claim 1 is characterized in that, also comprises:
The decoder master controller, described decoder master controller links to each other with the erroneous calculations module with described chien search with described decoding FIFO memory, described syndrome computing module, the described key equation module of finding the solution respectively, and described decoder master controller is used for controlling described sub-computing module, the described operating state of finding the solution key equation module, described chien search and erroneous calculations module and described decoding FIFO memory module followed.
3. Reed Solomon decoder as claimed in claim 1 is characterized in that, described syndrome computing module also is used for the result of calculation generation error flag bit according to described 2T syndrome computation subunit.
4. Reed Solomon decoder as claimed in claim 3 is characterized in that, described syndrome computing module further comprises 2T syndrome computation subunit and the syndrome state machine that links to each other with described 2T syndrome computation subunit,
Described 2T syndrome computation subunit is used for generating 2T syndrome multinomial coefficient according to described code stream to be decoded respectively under the control of described syndrome state machine;
Described syndrome state machine, be used for controlling according to the control signal of described decoder master controller the work schedule of described 2T syndrome computation subunit, and judge whether to exist mistake according to described 2T syndrome multinomial coefficient, to generate described error flag position.
5. Reed Solomon decoder as claimed in claim 4, it is characterized in that, the constant term Galois field multiplier that described syndrome computation subunit further includes the confinement adder, links to each other with described finite field adder, the register that links to each other with described constant term Galois field multiplier with described finite field adder respectively
Described finite field adder is used for the Output rusults of described code stream to be decoded and described constant term Galois field multiplier is carried out the finite field addition process to generate the syndrome multinomial coefficient;
Described constant term Galois field multiplier is used for multinomial coefficient and the finite field constant of the output of described register are carried out multiplication process;
Described register has loading and keeps function, described register root is carried out loading and the output of described syndrome multinomial coefficient according to the control signal of described syndrome state machine, wherein, when described register is inhibit signal in described control signal, keep the output of described register constant, when described control signal was load signal, described controller loaded and exports corresponding syndrome multinomial coefficient.
6. Reed Solomon decoder as claimed in claim 1 is characterized in that, the described key equation module of finding the solution is carried out iterative computation to obtain coefficient and the polynomial coefficient of improper value of error location polynomial according to the RiBM algorithm.
7. Reed Solomon decoder as claimed in claim 6, it is characterized in that, described first kind iterative processing unit that the key equation module comprises that further 2T links to each other successively, a T Equations of The Second Kind iterative processing unit that links to each other successively, 1 the 3rd class iterative processing unit and the solving key equation state machine that links to each other with described first kind iterative processing unit, Equations of The Second Kind iterative processing unit and the 3rd class iterative processing unit respectively of finding the solution, wherein
Described first kind iterative processing unit is used for the control signal according to described solving key equation state machine, to described syndrome multinomial coefficient, from the decoder master controller, the intermediate data that produces in the interative computation process processes to obtain coefficient and the polynomial coefficient of described improper value of described error location polynomial;
Described Equations of The Second Kind iterative processing unit is used for the control signal according to described solving key equation state machine, described intermediate data is processed to upgrade errors present in the iterative process, wherein, described Equations of The Second Kind iterative processing unit is exported to described first kind iterative processing unit every a clock cycle with operation result in the interative computation process;
Described the 3rd class iterative processing unit is used for the control signal according to described solving key equation state machine, the data-signal of described solving key equation state machine, described intermediate data are processed to finish the initialization of described the 3rd class iterative processing unit interative computation desired data, wherein, described the 3rd class iterative processing unit is exported to described Equations of The Second Kind iterative processing unit every a clock cycle with operation result in the interative computation process;
Described solving key equation state machine is used for controlling according to the control signal of described decoder master controller the operating state of described first kind iterative processing unit, described Equations of The Second Kind iterative processing unit and the 3rd class iterative processing unit,
Wherein, i processing unit in the described first kind iterative processing unit receives the result that comes from described i+1 processing unit, i is [0,2T-2] between integer, j processing unit in the described Equations of The Second Kind iterative processing unit receive from the result of described j+1 processing unit, j is [0, T-2] between integer, 2T-1 processing unit in the described first kind iterative processing unit receives the result that comes from the 0th processing unit in the described Equations of The Second Kind iterative processing unit, and T-1 processing unit in the described Equations of The Second Kind iterative processing unit receives the operation result that comes from the tired processing unit of described the 3rd class.
8. Reed Solomon decoder as claimed in claim 6 is characterized in that, wherein,
Described error location polynomial can be expressed as: ∧ (z)=1+ λ
1Z+ λ
2z
2+ ... .+ λ
rz
r
Described improper value multinomial can be expressed as: Ω (z)=ω
0+ ω
1Z+ ω
2z
2+ ... .+ ω
R-1z
R-1
Described key equation polynomial table is shown: ∧ (z) S (z)=Ω (z) mod z
2r,
Wherein, r is the error correction number of characters, and S (z) is the syndrome multinomial, and z is the finite field variable, λ
1To λ
rBe the coefficient of error location polynomial, ω
1... ω
rBe the polynomial coefficient of improper value.
9. Reed Solomon decoder as claimed in claim 1 is characterized in that, described chien search and erroneous calculations module also are used for coefficient and the polynomial coefficient calculations number of errors of improper value according to described error location polynomial.
10. Reed Solomon decoder as claimed in claim 9, it is characterized in that, described chien search and erroneous calculations module further comprise (T+1) individual chien search computing unit, a T good fortune Buddhist nun formula computing unit, the chien search and good fortune Buddhist nun formula computing mode machine and the false judgment submodule that link to each other with Fu Ni formula computing unit with described chien search computing unit respectively
Described chien search computing unit is used for the coefficient calculations errors present according to error location polynomial;
Described good fortune Buddhist nun's formula computing unit is used for according to the polynomial coefficient calculations improper value of improper value;
Described chien search and good fortune Buddhist nun formula computing mode machine are used for controlling according to the control signal of described decoder master controller the operating state of described chien search computing unit and described good fortune Buddhist nun's formula computing unit.
Described false judgment module is used for obtaining number of errors and exporting described improper value, number of errors and errors present according to described errors present and described improper value.
11. a Reed Solomon coding/decoding method is characterized in that, may further comprise the steps:
Treat decoded bit stream and carry out buffer memory;
Generate 2T syndrome multinomial coefficient according to described code stream to be decoded;
Obtain coefficient and the polynomial coefficient of improper value of error location polynomial according to described 2T syndrome multinomial coefficient;
Coefficient and the polynomial coefficient difference mistake in computation value of improper value and errors present according to described error location polynomial; With
According to described improper value and errors present the code stream to be decoded of described buffer memory is carried out error correction to generate decoded code stream.
12. Reed Solomon coding/decoding method as claimed in claim 11 is characterized in that, also comprises:
According to described 2T syndrome multinomial coefficient generation error flag bit.
13. Reed Solomon coding/decoding method as claimed in claim 11 is characterized in that,
Carry out iterative computation to obtain coefficient and the polynomial coefficient of improper value of error location polynomial according to the RiBM algorithm.
14. Reed Solomon coding/decoding method as claimed in claim 13 is characterized in that, wherein,
Described error location polynomial is expressed as: ∧ (z)=1+ λ
1Z+ λ
2z
2+ ... .+ λ rz
r
Described improper value polynomial table is shown: Ω (z)=ω
0+ ω
1Z+ ω
2z
2+ ... .+ ω
R-1z
R-1
Described key equation polynomial table is shown: ∧ (z) S (z)=Ω (z) mod z
2r,
Wherein, r is the error correction number of characters, and S (z) is the syndrome multinomial, and z is the finite field variable, λ
1... λ
rBe the coefficient of error location polynomial, ω
1... ω
rBe the polynomial coefficient of improper value.
15. Reed Solomon coding/decoding method as claimed in claim 11 is characterized in that, also comprises:
Coefficient and the polynomial coefficient calculations number of errors of improper value according to described error location polynomial.
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