CN101834615B - Implementation method of Reed-Solomon encoder - Google Patents

Abstract

The invention discloses an implementation method of a Reed-Solomon encoder, the compute mode of a check code is as follows: Ei is calculated according to a primitive element alpha of a finite field GF (2m) and then stored in a memory; information codes are sent to an accompanied calculation circuit that multi-symbols are input in parallel to calculate f (alpha i); and the product of Ei and f (alpha i) are read from the memory to obtain the final check code. The implementation method of the Reed-Solomon encoder can realize Reed-Solomon encoding for inputting parallel multiple-symbol data, and shorten time delay that the data passes through the encoder on the basis that the work clock frequency of a system is not improved.

Description

The Reed-Solomon encoder implementation method

Technical field

The present invention relates to digital communication technology, particularly a kind of Reed-Solomon encoder implementation method.

Background technology

Reed-Solomon code (Reed-Solomon sign indicating number; The RS sign indicating number) is a kind of linear error correction sign indicating number; Because it has the ability of while burst-error-correction and random error, and burst-correcting ability is very strong, thereby is widely used in the error control of data communication and data-storage system.

The RS sign indicating number is a kind of polynary BCH code, is defined in Galois finite field gf (2 ^m) on, m is the figure place of the binary sequence that comprises of a symbol, the parameter of entangling t wrong RS sign indicating number is following:

Code length: n=2 ^m-1 symbol

Information code: a k=n-2t symbol

Check code: a z=2t=n-k symbol

Minimum distance: a d=2t+1 symbol

For the RS sign indicating number that a length is n symbol, each symbol all is Galois finite field gfs (2 ^m) in an element.The generator polynomial that can entangle t wrong RS sign indicating number is:

$g\left(x\right)=\underset{i=0}{\overset{2t-1}{\mathrm{\&Pi;}}}(x-{\mathrm{\&alpha;}}^i)={\mathrm{<figure-callout\; id="0"\; label="g"\; filenames="H200910056944XE00022.png,H200910056944XE00032.png"\; state="\{\{state\}\}">g</figure-callout>}}_0+g_{1}x+g_2{x}^2+\&CenterDot;\&CenterDot;\&CenterDot;+g_{2t-1}{x}^{2t-1}+x^{2t}$

α wherein ⁱBe the root of g (x), and be GF (2 ^m) in an element.

Need supposing the information encoded sign indicating number is m (x), and check code is p (x), and the data block that final formation will be sent is made up of information code and check code, and is called as code word c (x).This code word is shown with the polynomial table on n-1 rank:

c(x)＝x ^2tm(x)+p(x)

Wherein p (x) is the multinomial on 2t-1 rank, and it is generated by following formula

P (x)=x ^2tM (x) modg (x) wherein g (x) is a generator polynomial

The RS encoder is exactly to adopt special circuit to be used to calculate p (x), and a numeral c (x) is formed in the back that the check code p (x) that will finally calculate acquisition is placed on information code.

Usually, one (n, k) realization of RS encoder all adopts the feedback shift register (FSR) of a 2t level to realize that typical R S coder structure is as shown in Figure 1:

Can see traditional RS encoder from Fig. 1 existing the global feedback signal to deliver to each Galois field multiplier that when needs use can correct the RS sign indicating number of more mistake the time, because the feedback path in the circuit is oversize, this can limit the switching speed of encoder.Secondly the information code in the input coding device must be the symbol of m bits bit wide in traditional RS encoder.Therefore when to occur sending into information encoder in the system be a plurality of parallel symbol (n * m bits bit wide), just can only carry out and go here and there and change the requirement of satisfying coding circuit through raising encoder working clock frequency or information code.

Can see that from top description traditional RS encoder comes with some shortcomings.

1. because the global feedback signal is arranged in circuit, along with the raising of the RS sign indicating number correctable error ability of using, the feedback path of circuit is just longer, and the working clock frequency of encoder just can not run too soon, can't satisfy the needs of high-speed digital transmission system.

2. because the input bit wide of traditional RS encoder is a symbol, therefore when the symbol of sending into encoder simultaneously during greater than one, can only be through improving the encoder working clock frequency or carrying out information code and go here and there and change the requirement of satisfying system.But raising encoder operating frequency and feedback path farm labourer above-mentioned make clock and can not have contradiction too soon; And carry out information and go here and there conversion can increase the complexity and the resource of system; And cause information code very big through the time-delay of encoder, bigger in some applications encoding time delay is not allowed to.

Summary of the invention

The technical problem that the present invention will solve provides a kind of Reed-Solomon encoder implementation method, on the basis of not improving the system works clock frequency, realizes the Reed-Solomon coding of parallel many symbol data inputs, reduces the time delay of data through encoder.

For solving the problems of the technologies described above, Reed-Solomon encoder implementation method of the present invention through circuit calculation check sign indicating number, will be calculated code word of back composition that the check code that obtains is placed on information code then; It is characterized in that the account form of check code is following,

One. use Lagrange interpolation to calculate E _i,

$E_i=\frac{\underset{j\&NotEqual;i}{\mathrm{\&Pi;}}(x-{\mathrm{\&alpha;}}^j)}{\underset{j\&NotEqual;i}{\mathrm{\&Pi;}}({\mathrm{\&alpha;}}^i-{\mathrm{\&alpha;}}^j)}$

E _iData format do

E _i＝e _i，n-k-1x ^n-k-1+e _i，n-k-2x ^n-k-2+…+e _i，1x+e _i，0

With the E that calculates _iDeposit in the memory and preserve,

Two. send into the syndrome counting circuit that many symbol parallels are imported to information code, calculate f (1), f (α) ... .f (α ^2t-1), calculate f (1), f (α) ... .f (α ^2t-1) formula following:

$f\left({\mathrm{\&alpha;}}^i\right)=\underset{u=0}{\overset{M-1}{\mathrm{\&Sigma;}}}\underset{V=0}{\overset{N-1}{\mathrm{\&Sigma;}}}{\mathrm{din}}_{\mathrm{Nu}+v}{\mathrm{\&alpha;}}^{(\mathrm{Nu}+v)i}=\left(\underset{u=0}{\overset{M-1}{\mathrm{\&Sigma;}}}\left({\left({\mathrm{\&alpha;}}^i\right)}^{\mathrm{Nu}}\underset{v=0}{\overset{N-1}{\mathrm{\&Sigma;}}}{\mathrm{din}}_{\mathrm{Nu}+v}{\left({\mathrm{\&alpha;}}^i\right)}^v\right)\right){\mathrm{\&alpha;}}^{32}$

If the symbolic number k of an information code is not equal to M * N, just before information code input coding device, adds numerical value and be 0 symbol and make the final symbolic number of information code equal M * N in the information code front;

Three. from memory, read E _iWith f (α ⁱ) multiply each other, obtaining final check code, computing formula is following:

$p\left(x\right)=p_{n-k-1}{x}^{n-k-1}+p_{n-k-2}{x}^{n-k-2}+\&CenterDot;\&CenterDot;\&CenterDot;+{\mathrm{<figure-callout\; id="0"\; label="p"\; filenames="H200910056944XE00022.png,H200910056944XE00032.png"\; state="\{\{state\}\}">p</figure-callout>}}_0=\underset{i=0}{\overset{n-k-1}{\mathrm{\&Sigma;}}}f\left({\mathrm{\&alpha;}}^i\right)E_i\left(x\right)$

Wherein, m (x) is an information code, and p (x) is a check code, din _Nu+vBe the information code symbol of input, E _iBe with 1, α, α ²α ^2t-1Be 2t-1 interpolation basic function of node, α is a finite field gf (2 ^m) primitive element, α ⁱ(α ^j) be 2t the root of RS sign indicating number generator polynomial g (x), t is the maximum error correction number of encoder, n is the symbolic number of a Reed-Solomon coding codeword; K is the symbolic number of information code, and m is the figure place of the binary sequence that comprises of a symbol, and i, j are zero or positive integer; And 0≤j≤n-k-1,0≤i≤n-k-1, n-k-1=2t-1; M, N are positive integer, and u, v are integer and 0≤u≤M-1,0≤v≤N-1.

Reed-Solomon encoder implementation method of the present invention; During encoder is realized owing to need not use long feedback circuit; Can on the basis of not improving the system works clock frequency, realize parallel many symbol data inputs, work in the higher clock circuit; Reduce the time delay of data, be specially adapted to high-speed digital transmission system through encoder.

Description of drawings

Below in conjunction with accompanying drawing and embodiment the present invention is done further explain.

Fig. 1 is traditional typical R S coder structure sketch map;

Fig. 2 is the syndrome counting circuit structure chart of many symbol parallel inputs;

Fig. 3 is a syndrome computing module internal frame diagram;

Fig. 4 is a Reed-Solomon encoder implementation method sketch map of the present invention;

Fig. 5 is the syndrome computing block diagram of Reed-Solomon encoder implementation method one execution mode of the present invention;

Fig. 6 is the syndrome computing module internal frame diagram of Reed-Solomon encoder implementation method one execution mode of the present invention;

Fig. 7 is the check code computation structure figure of Reed-Solomon encoder implementation method one execution mode of the present invention.

Embodiment

Should there be a finite field gf (2 in code word c (x) for obtaining behind the RS coding ^m) on check matrix H, make that code word c (x) and check matrix H multiply each other to syndrome S be 0.

The definition check matrix H does

$H=\left[\begin{array}{ccccc}1& 1& 1& \&CenterDot;\&CenterDot;\&CenterDot;& 1\\ 1& \mathrm{\&alpha;}& {\mathrm{\&alpha;}}^2& \&CenterDot;\&CenterDot;\&CenterDot;& {\mathrm{\&alpha;}}^{n-1}\\ 1& {\mathrm{\&alpha;}}^2& {\left({\mathrm{\&alpha;}}^2\right)}^2& \&CenterDot;\&CenterDot;\&CenterDot;& {\left({\mathrm{\&alpha;}}^2\right)}^{n-1}\\ \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;\\ \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;\\ \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;\\ 1& {\mathrm{\&alpha;}}^{2t-1}& {\left({\mathrm{\&alpha;}}^{2t-1}\right)}^2& \&CenterDot;\&CenterDot;\&CenterDot;& {\left({\mathrm{\&alpha;}}^{2t-1}\right)}^{n-1}\end{array}\right]$

α wherein ⁱ2t root for generator polynomial g (x).

Order

c(x)＝[c ₀?c ₁…c _n-2?c _n-1]＝[p ₀?p ₁…p _n-k-1?m ₀?m ₁…m _k-1]

$S=\left[\begin{array}{cccccccc}{p}_0& {\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="H200910056944XE00012.png,H200910056944XE00041.png"\; state="\{\{state\}\}">p</figure-callout>}}_1& \&CenterDot;\&CenterDot;\&CenterDot;& p_{n-k-1}& m_0& {\mathrm{<figure-callout\; id="1"\; label="m"\; filenames="H200910056944XE00012.png,H200910056944XE00041.png"\; state="\{\{state\}\}">m</figure-callout>}}_1& \&CenterDot;\&CenterDot;\&CenterDot;& m_{k-1}\end{array}\right]\&times;{\left[\begin{array}{ccccc}1& 1& 1& \&CenterDot;\&CenterDot;\&CenterDot;& 1\\ 1& \mathrm{\&alpha;}& {\mathrm{\&alpha;}}^2& \&CenterDot;\&CenterDot;\&CenterDot;& {\mathrm{\&alpha;}}^{n-1}\\ 1& {\mathrm{\&alpha;}}^2& {\left({\mathrm{\&alpha;}}^2\right)}^2& \&CenterDot;\&CenterDot;\&CenterDot;& {\left({\mathrm{\&alpha;}}^2\right)}^{n-1}\\ \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;\\ \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;\\ \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;\\ 1& {\mathrm{\&alpha;}}^{2t-1}& {\left({\mathrm{\&alpha;}}^{2t-1}\right)}^2& \&CenterDot;\&CenterDot;\&CenterDot;& {\left({\mathrm{\&alpha;}}^{2t-1}\right)}^{n-1}\end{array}\right]}^T=\left[\begin{array}{c}0\\ 0\\ 0\\ \&CenterDot;\\ \&CenterDot;\\ \&CenterDot;\\ 0\end{array}\right]$

Because α ⁱWe can know in advance, so can obtain following equality

$\left[\begin{array}{cccc}1& 1& \&CenterDot;\&CenterDot;\&CenterDot;& 1\\ 1& \mathrm{\&alpha;}& \&CenterDot;\&CenterDot;\&CenterDot;& {\mathrm{\&alpha;}}^{n-k-1}\\ \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;\\ \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;\\ \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;\\ 1& {\mathrm{\&alpha;}}^{2t-1}& \&CenterDot;\&CenterDot;\&CenterDot;& {\left({\mathrm{\&alpha;}}^{2t-1}\right)}^{n-k-1}\end{array}\right]\&times;\left[\begin{array}{c}{p}_0\\ {\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="H200910056944XE00012.png,H200910056944XE00041.png"\; state="\{\{state\}\}">p</figure-callout>}}_1\\ \&CenterDot;\\ \&CenterDot;\\ \&CenterDot;\\ p_{n-k-1}\end{array}\right]=\left[\begin{array}{cccc}1& 1& \&CenterDot;\&CenterDot;\&CenterDot;& 1\\ {\mathrm{\&alpha;}}^{n-k}& {\mathrm{\&alpha;}}^{n-k+1}& \&CenterDot;\&CenterDot;\&CenterDot;& {\mathrm{\&alpha;}}^{n-1}\\ \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;\\ \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;\\ \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;\\ {\left({\mathrm{\&alpha;}}^{2t-1}\right)}^{n-k}& {\left({\mathrm{\&alpha;}}^{2t-1}\right)}^{n-k+1}& \&CenterDot;\&CenterDot;\&CenterDot;& {\left({\mathrm{\&alpha;}}^{2t-1}\right)}^{n-1}\end{array}\right]\&times;\left[\begin{array}{c}{m}_0\\ {\mathrm{<figure-callout\; id="1"\; label="m"\; filenames="H200910056944XE00012.png,H200910056944XE00041.png"\; state="\{\{state\}\}">m</figure-callout>}}_1\\ \&CenterDot;\\ \&CenterDot;\\ \&CenterDot;\\ m_{k-1}\end{array}\right]$

Because information code m (x) is known, above right-hand component in the equality can under the known situation of information code, adopt the method for calculating syndrome in the RS decoding circuit to calculate, so following formula can be expressed as

$\left[\begin{array}{cccc}1& 1& \&CenterDot;\&CenterDot;\&CenterDot;& 1\\ 1& \mathrm{\&alpha;}& \&CenterDot;\&CenterDot;\&CenterDot;& {\mathrm{\&alpha;}}^{n-k-1}\\ \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;\\ \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;\\ \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;\\ 1& {\mathrm{\&alpha;}}^{2t-1}& \&CenterDot;\&CenterDot;\&CenterDot;& {\left({\mathrm{\&alpha;}}^{2t-1}\right)}^{n-k-1}\end{array}\right]\&times;\left[\begin{array}{c}{p}_0\\ {\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="H200910056944XE00012.png,H200910056944XE00041.png"\; state="\{\{state\}\}">p</figure-callout>}}_1\\ \&CenterDot;\\ \&CenterDot;\\ \&CenterDot;\\ p_{n-k-1}\end{array}\right]=\left[\begin{array}{c}f\left(1\right)\\ f\left(\mathrm{\&alpha;}\right)\\ \&CenterDot;\\ \&CenterDot;\\ \&CenterDot;\\ f\left({\mathrm{\&alpha;}}^{2t-1}\right)\end{array}\right]$

F (α ⁱ) be the result after information code is passed through the syndrome counting circuit, what can see now that new RS coding circuit will realize is exactly how to calculate p through top formula _i

An execution mode of the present invention is to use the method for Lagrange interpolation (Lagrange's interpolation) to remove to calculate p _iAlso can use the inverse matrix A that asks matrix A in addition ^-1, and the method that multiplies each other with matrix F is calculated p _iWherein matrix A is represented as follows.

$A=\left[\begin{array}{cccc}1& 1& \&CenterDot;\&CenterDot;\&CenterDot;& 1\\ 1& \mathrm{\&alpha;}& \&CenterDot;\&CenterDot;\&CenterDot;& {\mathrm{\&alpha;}}^{n-k-1}\\ \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;\\ \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;\\ \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;\\ 1& {\mathrm{\&alpha;}}^{2t-1}& \&CenterDot;\&CenterDot;\&CenterDot;& {\left({\mathrm{\&alpha;}}^{2t-1}\right)}^{n-k-1}\end{array}\right]$

Matrix F is represented as follows

$F=\left[\begin{array}{c}f\left(1\right)\\ f\left(\mathrm{\&alpha;}\right)\\ \&CenterDot;\\ \&CenterDot;\\ \&CenterDot;\\ f\left({\mathrm{\&alpha;}}^{2t-1}\right)\end{array}\right]$

The performing step of RS encoder one execution mode of the present invention is following:

1. use Lagrange interpolation to calculate Ei, Ei is with 1, α, α ²α ^2t-12t-1 interpolation basic function for node.

$E_i=\frac{\underset{j\&NotEqual;i}{\mathrm{\&Pi;}}(x-{\mathrm{\&alpha;}}^j)}{\underset{j\&NotEqual;i}{\mathrm{\&Pi;}}({\mathrm{\&alpha;}}^i-{\mathrm{\&alpha;}}^j)}$

E _iData format do

E _i＝e _i，n-k-1x ^n-k-1+e _i，n-k-2x ^n-k-2+…+e _i，1x+e _i，0

With the E that calculates _iDeposit among the ROM and preserve;

2. send into information code the syndrome counting circuit of many symbol parallel inputs, calculate syndrome f (1) f (α) ... F (α ^2t-1).

The syndrome computation structure figure of many symbol parallel inputs is as shown in Figure 2, sends into 2t syndrome computing module to a plurality of symbol parallels of an information code, and 2t syndrome computing module calculates output f (1), f (α), f (α respectively ²) ..., f (α ^2t-1).Syndrome computing module internal frame diagram is as shown in Figure 3, in the syndrome computing module the current N that sends into a symbol m _u(x) and α ^IvDo the multiply accumulating computing, and then and α ^INDo multiplying, and the u time result calculated with u-1 result of calculation addition, after the symbol of current information sign indicating number has all passed through the multiply accumulating computing, final result again with α ³²Multiply each other and obtain f (α ⁱ).

If the symbolic number k of an information code is not equal to M * N, just before information code input coding device, adds numerical value and be 0 symbol and make the final symbolic number of information code equal M * N in the information code front.

3. ought calculate f (1), f (α) ... .f (α ^2t-1) after, from ROM, read E _iWith f (α ⁱ) multiply each other, obtain final check code p (x).Computing formula is following:

$p_{n+k-1}{x}^{n+k-1}+p_{n-k-2}{x}^{n-k-2}+\&CenterDot;\&CenterDot;\&CenterDot;+{\mathrm{<figure-callout\; id="0"\; label="p"\; filenames="H200910056944XE00022.png,H200910056944XE00032.png"\; state="\{\{state\}\}">p</figure-callout>}}_0=\underset{i=0}{\overset{n-k-1}{\mathrm{\&Sigma;}}}f\left({\mathrm{\&alpha;}}^i\right)E_i\left(x\right)$

Be given in an embodiment in 10G EPON (Ethernet Passive Optical Network, the ethernet passive optical network) system below.

In 10G EPON system, adopted based on stream RS (255,223) as forward error correction coding, there is following requirement in this system to the coding rate and the time delay of encoder:

1. data rate is fast, at the uniform velocity get into the RS encoder with the speed of 8 symbols of each timeticks, and work clock operates in 156MHz.

2. require the time delay of encoder less, and fixing.

3. encoder area when hardware is realized is little.

This system requirements is 255 as the symbolic number n of a code word of an encoding block; The information code symbolic number k that comprises in code word is 223, and check code symbol numbers 2t is 32, in order to realize conveniently; Numerical value of interpolation is 0 symbol before each encoding block; Constitute 224 information code symbols, divide 28 timeticks then, each timeticks send 8 information code symbols to get into many symbol parallels syndrome computing module.

The Reed-Solomon code coder structure of in 10G EPON, realizing is as shown in Figure 4.

The computing formula of many symbol parallel input syndromes is following

$f\left({\mathrm{\&alpha;}}^i\right)=\underset{u=0}{\overset{27}{\mathrm{\&Sigma;}}}\underset{V=0}{\overset{7}{\mathrm{\&Sigma;}}}{\mathrm{din}}_{8u+v}{\mathrm{\&alpha;}}^{(8u+v)i}=\left(\underset{u=0}{\overset{27}{\mathrm{\&Sigma;}}}\left({\left({\mathrm{\&alpha;}}^i\right)}^{8u}\underset{v=0}{\overset{7}{\mathrm{\&Sigma;}}}{\mathrm{din}}_{8u+v}{\left({\mathrm{\&alpha;}}^i\right)}^v\right)\right){\mathrm{\&alpha;}}^{32}$

This syndrome computing block diagram is as shown in Figure 5, and the syndrome computing module is as shown in Figure 6.Fig. 6 is a syndrome computing module internal frame diagram of at every turn sending into one group of eight parallel symbol, eight symbol din of information code _8u+0, din _8u+1..., din _8u+6, din _8u+7Parallel syndrome computing module, the din of being sent to _8u+0Multiply each other din with α _8u+1Same α ⁱMultiply each other ..., din _8u+6Same α ⁶ⁱMultiply each other din _8u+7Same α ⁷ⁱMultiply each other, add up then, and then and α ^INDo multiplying, and the u time result calculated with u-1 result of calculation addition, after the M of current information sign indicating number group code has all passed through the multiply accumulating computing, final result again with α ³²Multiply each other and obtain f (α ⁱ).

After calculating syndrome, from the ROM table, read E _iValue, and calculation check sign indicating number.Computing formula is following

$p_{31}{x}^{31}+p_{30}{x}^{30}+\&CenterDot;\&CenterDot;\&CenterDot;+{\mathrm{<figure-callout\; id="0"\; label="p"\; filenames="H200910056944XE00022.png,H200910056944XE00032.png"\; state="\{\{state\}\}">p</figure-callout>}}_0=\underset{i=0}{\overset{31}{\mathrm{\&Sigma;}}}f\left({\mathrm{\&alpha;}}^i\right)E_i\left(x\right)$

E in the following formula _iExpression as follows

E _i＝e _i，31x ³¹+e _i，30x ³⁰+…+e _i，1x+e _i，0 0≤i≤31

It is following to obtain p (x) inner element computing formula according to top two formula

$p_l=\underset{i=0}{\overset{n-k-1}{\mathrm{\&Sigma;}}}f\left({\mathrm{\&alpha;}}^i\right)e_{i,l},0\&le;l\&le;31$

It is as shown in Figure 7 that the corresponding check yardage is calculated structure chart.Among this embodiment, n=255, k=223, t=16, N=8, M=28.

Among above-mentioned execution mode and the embodiment, m (x) is an information code, and p (x) is a check code, din _Nu+vBe the information code symbol of input, E _iBe with 1, α, α ²α ^2t-1Be 2t-1 interpolation basic function of node, α is a finite field gf (2 ^m) primitive element, α ⁱ(α ^j) be 2t the root of RS sign indicating number generator polynomial g (x), t is the maximum error correction number of encoder, n is the symbolic number of a Reed-Solomon coding codeword; K is the symbolic number of information code, and m is the figure place of the binary sequence that comprises of a symbol, and i, j are zero or positive integer; And 0≤j≤n-k-1,0≤i≤n-k-1, n-k-1=2t-1; M, N are positive integer, and u, v are integer and 0≤u≤M-1,0≤v≤N-1.

Reed-Solomon encoder implementation method of the present invention does not increase on the basis of system complexity and resource guaranteeing, has realized the RS coding to parallel symbol, has shortened the coding time delay.And can be operated on the higher clock frequency, can satisfy the requirement of high speed data transmission system the RS coding rate.

Claims (3)

1. a Reed-Solomon encoder implementation method through circuit calculation check sign indicating number, will be calculated code word of back composition that the check code that obtains is placed on information code then; It is characterized in that the account form of check code is following,

One, use Lagrange's interpolation to calculate E _i,

E _jData format do

E _i＝e _i，n-k-1x ^n-k-1+e _i，n-k-2x ^n-k-2+...+e _i，1x+e _i，0

With the E that calculates _iDeposit in the memory and preserve;

Two, send into information code the syndrome counting circuit of many symbol parallel inputs, calculate f (1), f (α) ..., f (α ^2t-1), calculate f (1), f (α) ..., f (α ^2t-1) formula following:

If the symbolic number k of an information code is not equal to M * N, just before information code input coding device, adds numerical value and be 0 symbol and make the final symbolic number of information code equal M * N in the information code front;

Three, from memory, read E _iWith f (α ⁱ) multiply each other, obtaining final check code, computing formula is following:

Wherein, p (x) is a check code, din _Nu+vBe the information code symbol of input, E _iBe with 1, α, α ²... α ^2t-1Be 2t-1 interpolation basic function of node, α is a finite field gf (2 ^m) primitive element, α ⁱOr α ^jBe 2t the root of RS sign indicating number generator polynomial g (x), t is the maximum error correction number of encoder, and n is the symbolic number of a Reed-Solomon coding codeword; K is the symbolic number of information code, and m is the figure place of the binary sequence that comprises of a symbol, and i, j are zero or positive integer; And 0≤j≤n-k-1,0≤i≤n-k-1, n-k-1=2t-1; M, N are positive integer, and u, v are integer and 0≤u≤M-1,0≤v≤N-1.

2. Reed-Solomon encoder implementation method according to claim 1 is characterized in that, calculates f (α ⁱ) time, at first being divided into N symbol to information code is one group input signal m _u(*)={ din _Nu+0, din _Nu+1..., din _Nu+N-1, send into 2t syndrome computing module in the syndrome counting circuit, in the syndrome computing module the N of current input symbol m _u(*) and (α ⁱ) ^vDo the multiply accumulating computing, and then with (α ⁱ) ^NDo multiplying, and the u time result calculated with u-1 result of calculation addition, after the symbol of current information sign indicating number has all passed through the multiply accumulating computing, final result again with α ³²Multiply each other and obtain f (α ⁱ).

3. Reed-Solomon encoder implementation method according to claim 1 and 2 is characterized in that, n=255, k=223, t=16, N=8, M=28.

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