CN101834617A - RS (Reed-Solomon) error correction decoder - Google Patents
RS (Reed-Solomon) error correction decoder Download PDFInfo
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Abstract
The invention provides an RS (Reed-Solomon) error correction decoder which comprises an first-in first-out (FIFO) buffer, an adjoint computing circuit, a deleted location polynomial computing circuit, a correction adjoint computing circuit, a key equation solution circuit, a Chien search circuit, an error value computing circuit and a summator, wherein the deleted location polynomial computing circuit and the adjoint computing circuit are arranged in parallel. Through the arrangement, the RS error correction decoder can carry out adjoint computation and deleted location polynomial computation synchronously, thereby increasing the decoding speed.
Description
[technical field]
The invention belongs to the error-correcting code technique field, especially, relate to a kind of RS error-correcting code decoder.
[background technology]
Error correcting code is extensive use in information technology, generally speaking, before transmitting terminal transmission information, error correcting encoder calculates corresponding check code according to the data message that will send, and check code formed error correcting code together as redundant check and data message, after receiving terminal is received error correcting code, mistake can not only be automatically found, and the mistake of code word in transmission course can be automatically corrected by error correcting deocder.
RS error correcting code (Reed-Solomon error correction, Read-Solomon error correcting code) is the very strong cyclic code of a kind of error correcting capability, and common symbol (N, K) implication of RS is as follows: N indication code word length; K represents the message length in the code word; N-K=2t represents the symbolic number of check code, and wherein t represents the code word error number that can correct.
The coding and decoding flow process of RS error-correcting code decoder of the prior art as shown in Figure 1, in step 101, at first determine raw information, in step 102, raw information is carried out the RS coding, to obtain the RS coded data, in step 103, receiving terminal obtains the RS coded data, in step 104, calculate syndrome,, judge whether syndrome equals 0 in step 105, if judged result is a "No", then execution in step 106, confirm wrong multinomial and errors present, and in step 107, correct a mistake according to errors present, and after step 107 is finished, execution in step 109, output information.
In step 105, if judged result is a "Yes", then know that in step 108 the reception data are consistent with initial data, execution in step 109 is exported reception information.
In error correction coding algebraically, regard a multinomial as with the data series that binary digit is represented, for example sequence of binary digits 10101111 can be expressed as:
M(x)＝a
7x
7+a
6x
6+a
5x
5+a
4x
4+a
3x
3+a
2x
2+a
1x
1+a
0x
0＝x
7+x
5+x
3+x
2+1
Wherein, x
iThe position of expression code, or certain binary number bit position, x
iThe coefficient a of front
iIf the value of indication code is a
iBe a binary code, value 0 or 1 then, and M (x) is called the message code multinomial.
For coding step, the sequence length of supposing the input coding device is K, and then the message code multinomial of list entries can be expressed as:
M(x)＝m
K-1x
K-1+m
K-2x
K-2+...+m
1x+m
0 (1)
By above introduction as can be known, m
iBe 1 or 0, x
iExpression m
iPosition in sequence, i=0,1,2 ..., K-1.
Encoder has following equation:
x
RM(x)＝α(x)g(x)+R(x) (2)
Wherein, x
RM (x) represents x
RWith the product of M (x), R is the exponent number of R (x), and g (x) is a generator polynomial, and α (x) is x
RMerchant's multinomial that M (x) obtains divided by g (x), R (x) is the remainder polynomid that defines in (2) formula for receiving first multinomial.
Generator polynomial g (x) expression formula is
M wherein
i(x) be minimal polynomial.Its physical significance is, g (x) is by the generation of multiplying each other of t minimal polynomial, the maximum number of errors that t can correct for the RS error correcting code.
The sequence of encoder output is T (x), and length is N, and T (x) is expressed as
T(x)＝M(x)x
N-K+R(x) (3)
Suppose that the mistake that channel produces is E (x), the expression formula of error location polynomial E (x) is
E(x)＝E
N-1x
N-1+E
N-2x
N-2+...+E
1x+E
0 (4)
Wherein, E
iThe expression improper value is worked as E
iBe to represent wrong generation, E at 1 o'clock
iBe to represent that inerrancy took place at 0 o'clock.
Then receiving symbol multinomial R (x) can be expressed as
R(x)＝T(x)+E(x) (5)
Know by formula (2), (3)
T(x)＝M(x)x
R+R(x)＝α(x)g(x) (6)
Be that T (x) can be divided exactly by α (x).
Definition syndrome S
i, i.e. S
0..., S
2t-1, the maximum wrong number that t can correct for the RS error correcting code.The expression formula of syndrome is
S
i＝E(α
i)＝R(α
i) (7)
Wherein α is corresponding Galois field (Galois Field, element GF).The receiving symbol multinomial can be expressed as
R(x)＝r
N-1x
N-1+r
K-2x
K-2+...+r
1x+r
0 (8)
Wherein, r
jExpression list entries { r
N-1, r
N-2..., r
1, r
0One, be 1 or 0, x
jExpression r
jPosition in sequence, j=0,1,2,3..., N-1.
According to Huo Na algorithm (Horner), and formula (7), (8), the algorithm of following syndrome is proposed in the prior art:
S
i＝R(x
i)＝r
N-1(α
i)
N-1+r
N-2(α
i)
N-2+...+r
1(α
i)+r
0
＝((r
N-1(α
i)+r
N-2)(α
i)+...+r
1)(α
i)+r
0 (9)
Wherein, i=1,2 ..., 2t.
Fig. 2 shows the circuit structure of the calculating syndrome (9) that prior art provides, each clock cycle is imported 1 bit data (input) from adder 204 among the figure, and control bit this moment (control) control selector 203, make the value of register output be delivered in the adder 204, thereby make the 1 bit data addition with it of input, result after the addition carries out the primary constant multiplying by multiplier 201, operation result feeds back to register 202, input data accumulation at next clock cycle and adder 204 places, after constantly adding up, close selector 203 by control bit after the data input that needs verification is finished, this moment, the result of register 202 outputs was exactly the syndrome value of list entries.The serial input is adopted in the calculating of syndrome, adopts the calculating of this mode only to need a constant multiplier and an adder just can calculate S
iBut sort circuit structure arithmetic speed is slow partially, and needs 2t above circuit could calculate S respectively
1-S
2tValue, cause operation inconvenience, circuit structure complicated.
The delete position is the code word that decoder refusal reads, and as in the bar code decoding process, the part code word may read because of former thereby decoded device refusal such as stained in leaching process, thereby this code word is designated idle bit, i.e. the delete position.Existing RS error-correcting code decoder is when calculating syndrome, the back (or one step of back) that the position calculation that delete position decoding can be made mistakes is placed on syndrome carries out, though decoded information is consistent with raw information, but calculate asynchronous carrying out at position calculation and the syndrome that delete position decoding makes mistakes, can prolong decode time.
Therefore, at the above deficiency that prior art exists, needing badly provides a kind of RS error-correcting code decoder, can realize carrying out synchronously syndrome calculates and the delete position polynomial computation, and adopt improved syndrome counting circuit, thereby accelerate decoding speed, and guarantee that decoding can not make mistakes.
[summary of the invention]
In order to overcome the slow partially shortcoming of RS error-correcting code decoder arithmetic speed of prior art, the invention provides a kind of RS error-correcting code decoder, to overcome the problems referred to above.
The invention provides a kind of RS error-correcting code decoder, wherein the code word size of RS error correcting code is N, is used to correct t wrong number of codewords, and corresponding Galois field element is α, it is characterized in that, comprising: first-in first-out buffer is used for buffering and receives code word; The syndrome counting circuit is used for calculating syndrome according to code word; Delete position polynomial computation circuit is used for calculating the delete position multinomial according to the delete position of code word, revises the syndrome counting circuit, according to syndrome and delete position polynomial computation correction syndrome; Key equation solving circuit is according to revising associated polynomial and delete position polynomial computation error location polynomial and wrong multinomial; The money search circuit is according to error location polynomial mistake in computation position root of polynomial, to obtain errors present; The improper value counting circuit according to wrong multinomial and delete position polynomial computation mistake/delete position multinomial, utilizes the Forney formula to calculate improper value and deletion value according to mistake/delete position multinomial and errors present; First adder, through the reception code word of buffering through first adder and improper value and the addition of deletion value, thereby obtain correct code word, wherein, the parallel setting of delete position polynomial computation circuit and syndrome counting circuit.
The preferred embodiment one of according to the present invention, the syndrome counting circuit comprises: data storage, comprise 2t memory address at least, be used to store 2t data unit; Multiplier is used for successively the data cell and the α of i memory address will reading from data storage
iMultiply each other, to obtain multiplied result, wherein i is an integer, 1≤i≤2t; Second adder is used for successively with multiplied result and j+1 the code word r that is input to N code word of syndrome counting circuit
N-1-jAddition obtaining addition result, and is saved to i memory address of data storage with addition result, and wherein j is whole 2t the number of times that memory address reads to the data memory, and j is an integer, 1≤j≤N-1.
The preferred embodiment one of according to the present invention, data storage is the twoport data storage, comprise and read address port, write address port, read port and write inbound port, wherein read the address of reading of address port input and at first point to the 1st memory address in 2t the memory address, each clock cycle adds 1, until 2t clock cycle of experience, thus 2t memory address of traversal; The write address of write address port input at first points to the 1st memory address in 2t the memory address, and each clock cycle adds 1, until 2t clock cycle of experience, thus 2t memory address of traversal; Read port is used to read the data in the memory address that points to the address; Write inbound port and write data to the memory address that write address points to.
The preferred embodiment one of according to the present invention, data storage further comprises: controller is used to control the work of reading address port, write address port, read port and writing inbound port.
The preferred embodiment one of according to the present invention, controller judge write address or read the address and whether point to 2t+1 memory address, if judged result is a "Yes", and controller control write address or read the address and point to the 1st memory address then.
The preferred embodiment one of according to the present invention, controller judges whether j equals N-1, if judged result is a "Yes", then obtains syndrome respectively from 2t memory address.
The preferred embodiment one of according to the present invention, α is different constants corresponding to the various criterion value.
The preferred embodiment one of according to the present invention is arranged to data cell the 1st the code word r that the RS error-correcting code decoder receives when initialization
N-1
By above setting, RS error-correcting code decoder of the present invention can be realized carrying out synchronously syndrome and be calculated and the delete position polynomial computation, thereby accelerates decoding speed.
[description of drawings]
Fig. 1 shows the coding and decoding flow process of RS error correcting code of the prior art.
Fig. 2 shows the circuit structure of the calculating syndrome that prior art provides.
Fig. 3 is that the circuit of RS error-correcting code decoder of the present invention connects block diagram.
Fig. 4 is the workflow diagram of RS error-correcting code decoder of the present invention.
Fig. 5 is that the circuit of the syndrome counting circuit in the RS error-correcting code decoder of the present invention connects block diagram.
Fig. 6 is the serial data input mode schematic diagram of the syndrome counting circuit in the RS error-correcting code decoder of the present invention.
Fig. 7 is the workflow diagram of the syndrome counting circuit in the RS error-correcting code decoder of the present invention.
[embodiment]
Relevant feature of the present invention and technology contents please refer to following detailed description and accompanying drawing, and accompanying drawing only provides reference and explanation, is not to be used for the present invention is limited.
Fig. 3 is that the circuit of RS error-correcting code decoder of the present invention connects block diagram.As shown in Figure 3, RS error-correcting code decoder of the present invention comprises first-in first-out buffer 601, adder 602, syndrome counting circuit 603, revises syndrome counting circuit 604, key equation solving circuit 605, improper value counting circuit 606, delete position polynomial computation circuit 607, money search circuit 608.
The workflow of RS error-correcting code decoder of the present invention as shown in Figure 4, at first, in step 701, utilize syndrome counting circuit 603 to calculate syndrome S (x) according to receiving code word r (x), utilize delete position polynomial computation circuit 607 to calculate delete position multinomial Λ (x) according to the delete position simultaneously.
In step 702, by utilizing correction syndrome counting circuit 604 to calculate the associated polynomial T (x) of correction according to syndrome S (x) and delete position multinomial Λ (x).
In step 703, by T (x) and Λ (x), utilize key equation solving circuit 605 by MEA (Euclidean algorithm) algorithm solving key equation, obtain error location polynomial σ (x) and wrong multinomial ω (x).
In step 704, utilize money search circuit 608 to calculate the root of σ (x), thereby draw errors present.
In step 705, utilize improper value counting circuit 606 to calculate mistake/delete position multinomial ψ (x) according to ω (x) and Λ (x).
In step 706, improper value counting circuit 606 utilizes the Forney formula to calculate improper value and deletion value according to ψ (x) and errors present, and it is seen through adder 602 additions with original code word r (x), obtain correct code word, wherein original code word r (x) input summer 602 again after first-in first-out buffer 601 buffering, purpose is to postpone original code word r (x) 602 times of input summer, and is synchronous with the output result of improper value counting circuit 606.
It should be noted that RS error-correcting code decoder of the present invention with syndrome counting circuit 603 and delete position polynomial computation circuit 607 parallel settings, thereby saved operation time, improved decoding efficiency.
Below will introduce the circuit structure of syndrome counting circuit 603 in detail.
Fig. 5 is the circuit connection block diagram according to the syndrome counting circuit 603 in the RS error-correcting code decoder of the present invention.As shown in Figure 5, the syndrome counting circuit in the disclosed RS error-correcting code decoder comprises multiplier 301, adder 302, data storage 303, controller 306, first data input pin 304 and second data input pin 305.
Wherein, data storage 303 is preferably the twoport data storage, comprise and read address port (being the raddr shown in Fig. 3), read port (being the rdata shown in Fig. 3), write address port (being the waddr shown in Fig. 3) and write inbound port (being the wdata shown in Fig. 3), when reading a certain memory address of reading to point to data storage 303 in the address of address port input, can utilize read port that the data of storing in this memory address are read, similarly, when the write address of write address port input points to a certain memory address of data storage 303, can utilize and write inbound port and write data to this memory address.It should be noted that available controller 306 produces reads address and write address, and control is read address port, write address port and controlled read port and write the work of inbound port.
The syndrome counting circuit 603 of disclosed RS error-correcting code decoder can carry out initialization to data memory 303 when beginning, operation below wherein carrying out when initialization: (wherein memory address 1 at 2t memory address 1-2t of data storage 303 successively, 2,3, ..., 2t only numbers for convenience of explanation, and it is not corresponding with physical memory address) the input data cell, usually the data cell of importing during initialization is first code word r
N-1
Read the address since the 1st memory address 1, each clock cycle adds 1, until 2t clock cycle of experience, thereby travels through whole 2t memory address 1-2t, wherein reads the address and adds 1 action and controlled by controller 306.
Read port reads the data cell in the memory address that points to the address, as pointing to memory address 1 when reading the address, read port can read the data cell of memory address 1 stored, and is entered into multiplier 301, and wherein the action of read port reading of data is controlled by controller 306.
Write address is since the 1st memory address 1, and each clock cycle adds 1, until 2t clock cycle of experience, thereby travels through whole 2t memory address 1-2t, and wherein write address adds 1 action and controlled by controller 306.
Write inbound port and write the data cell of exporting by adder 302 to the memory address of write address sensing, as pointing to memory address 1 when write address, write the memory headroom that inbound port can write to the data cell of adder 302 output memory address 1 and carry out storage, wherein write the action that port writes data and controlled by controller 306.
The first input end 304 and second input 305 can carry out the serial data input, first serial data and second serial data input to first data input pin 304 and second data input pin 305 respectively synchronously by figure place, promptly when importing first serial data and second serial data respectively to the first input end 304 and second input 305, these two groups of serial datas are synchronous according to the clock cycle, can in a clock cycle, import Bits Serial data respectively simultaneously to the first input end 304 and second input 305.
Fig. 6 is the serial data input mode schematic diagram of the syndrome counting circuit 603 in the RS error-correcting code decoder of the present invention.Please refer to Fig. 6, in Fig. 6, first serial data 404 and second serial data 405 are for inputing to the serial data of the first input end 304 and second input 305 respectively, as shown in Figure 6, the input of serial data is a circulation with 2t clock cycle, total N-1 circulation.First serial data 404 and second serial data 405 are according to the syndrome computing formula
S
i＝(...(r
(N-1)α
i+r
(N-2))α
i+r
(N-3))α
i......+r
1)α
i+r
0 (9)
Definition, wherein, i=1,2 ..., 2t.Symbol is to be that (Galois Field, GF) multiplication GF (2 for corresponding Galois field
m) element, can be defined as a constant according to respective standard during Practical Calculation, and r
0To r
N-1The code word that receives for the RS error-correcting code decoder, wherein r
N-1Be first code word that receives, r
0It is last code word that receives.
In clock cycle, the serial data that first serial data 404 inputs to first data input pin 304 is respectively: α, α at first 2t
2, α
3..., α
2t, the serial data that second serial data 405 inputs to second data input pin 305 is respectively: r
N-2, r
N-2, r
N-2..., r
N-2
In clock cycle, the serial data that first serial data 404 inputs to first data input pin 304 is respectively: α, α at second 2t
2, α
3..., α
2t, the serial data that second serial data 405 inputs to second data input pin 305 is respectively: r
N-3, r
N-3, r
N-3..., r
N-3
Similarly, in the clock cycle, the serial data that first serial data 404 inputs to first data input pin 304 is respectively: α, α at N-1 2t
2, α
3..., α
2t, the serial data that second serial data 405 inputs to second data input pin 305 is respectively: r
0, r
0, r
0..., r
0
The data cell s of i the memory address that multiplier 301 will be read from data storage 303 successively
iWith α
iMultiply each other, to obtain multiplied result, wherein i is an integer, 1≤i≤2t;
Fig. 7 is the workflow diagram of the syndrome counting circuit 603 in the RS error-correcting code decoder of the present invention.Below with reference to Fig. 7 the workflow of the syndrome counting circuit in the RS error-correcting code decoder of the present invention is described in detail.
As shown in Figure 7,, carry out initialization operation, promptly to memory address 1-2t input r in step 501
N-1And outer circulation counting variable j is set equals 1, variable i=1 is set in addition, wherein i is used to represent the memory address operated, j is used to add up whole 2t the number of times that memory address reads to the data memory, more than operates under the control of controller 306 to finish.
In step 502, make read address and the write address of data storage 303 point to memory address i.
In step 503, read port reads data cell among the memory address i to multiplier 301 according to reading the address.
In step 504, from one first serial data α of first data input pin, 304 inputs
iTo multiplier 301, from serial data r of second data input pin, 305 inputs
N-1-jTo adder 302.
In step 505, multiplier 301 is with α
iMultiply each other with data cell and to obtain multiplied result.
In step 506, adder 302 is with r
N-1-jObtain addition result with the multiplied result addition.
In step 507, write inbound port and addition result is write to memory address i according to write address.
In step 508, i is carried out handling from adding 1.
In step 509, judge whether i equals 2t+1, if judged result is a "No", then skip to step 502.
If judged result is a "Yes", then execution in step 510, and i is set to 1, and j is carried out handling from adding 1.
In step 511, judge whether j equals N-1, if judged result is a "Yes", then in step 512, obtain syndrome.
If judged result is a "No", then skip to step 502.
Therefore, by above-mentioned N-1 computing, the data cell s that stores in the 2t of data storage 303 memory address
1To s
2tBe respectively:
s
1＝(...(r
(N-1)α+r
(N-2))α+r
(N-3))α......+r
1)α+r
0
s
2＝(...(r
(N-1)α
2+r
(N-2))α
2+r
(N-3))α
2......+r
1)α
2+r
0
s
3＝(...(r
(N-1)α
3+r
(N-2))α
3+r
(N-3))α
3......+r
1)α
3+r
0
......
s
2t＝(...(r
(N-1)α
2t+r
(N-2))α
2t+r
(N-3))α
2t......+r
1)α
2t+r
0
That is:
si＝(...(r
(N-1)α
i+r
(N-2))α
i+r
(N-3))α
i......+r
1)α
i+r
0
Wherein, i=1,2 ..., 2t.Thereby, data cell s
1, s
2, s
3..., s
2tCorresponding to each the syndrome S in the formula (9)
1, S
2, S
3..., S
2t
By above setting, RS error-correcting code decoder of the present invention can be realized carrying out synchronously syndrome and be calculated and the delete position polynomial computation, thereby accelerates decoding speed.
Above with reference to description of drawings various preferred embodiments of the present invention, but only otherwise deviate from the spirit and scope of the invention, those skilled in the art can carry out modifications and changes on the various forms to it, all belongs to protection scope of the present invention.
Claims (8)
1. RS error-correcting code decoder, wherein the code word size of RS error correcting code is N, is used to correct t wrong number of codewords, corresponding Galois field element is α, it is characterized in that, comprising:
First-in first-out buffer is used for buffering and receives code word;
The syndrome counting circuit is used for calculating syndrome according to described code word;
Delete position polynomial computation circuit is used for calculating the delete position multinomial according to the delete position of described code word,
Revise the syndrome counting circuit, according to described syndrome and described delete position polynomial computation correction syndrome;
Key equation solving circuit is according to described correction associated polynomial and described delete position polynomial computation error location polynomial and wrong multinomial;
The money search circuit is according to error location polynomial mistake in computation position root of polynomial, to obtain errors present;
The improper value counting circuit according to wrong multinomial and delete position polynomial computation mistake/delete position multinomial, utilizes the Forney formula to calculate improper value and deletion value according to mistake/delete position multinomial and described errors present;
First adder, the reception code word of buffering be through described first adder and described improper value and the addition of deletion value, thereby obtain correct code word,
Wherein, described delete position polynomial computation circuit and described syndrome counting circuit are parallel is provided with.
2. RS error-correcting code decoder according to claim 1 is characterized in that, described syndrome counting circuit comprises:
Data storage comprises 2t memory address at least, is used to store 2t data unit;
Multiplier is used for successively the data cell and the α of i memory address will reading from described data storage
iMultiply each other, to obtain multiplied result, wherein i is an integer, 1≤i≤2t;
Second adder is used for successively with described multiplied result and j+1 the code word r that is input to N code word of described syndrome counting circuit
N-1-jAddition obtaining addition result, and is saved to i memory address of described data storage with described addition result, and wherein j is whole 2t the number of times that memory address reads to described data storage, and j is an integer, 1≤j≤N-1.
3. RS error-correcting code decoder according to claim 2, it is characterized in that, described data storage is the twoport data storage, comprise and read address port, write address port, read port and write inbound port, the 1st memory address in the described 2t memory address at first pointed in the wherein said address of reading of reading address port input, each clock cycle adds 1, until 2t clock cycle of experience, thereby travels through a described 2t memory address; The write address of described write address port input at first points to the 1st memory address in the described 2t memory address, and each clock cycle adds 1, until 2t clock cycle of experience, thereby travels through a described 2t memory address; Described read port is used to read the data in the described memory address of reading to point to the address; The said write port writes data to the memory address that described write address points to.
4. RS error-correcting code decoder according to claim 3 is characterized in that, described data storage further comprises: controller is used to control described work of reading address port, described write address port, described read port and said write port.
5. RS error-correcting code decoder according to claim 4, it is characterized in that, described controller judges whether described write address or the described address of reading point to 2t+1 memory address, if judged result is a "Yes", described write address controlled by then described controller or described the 1st memory address pointed in the described address of reading.
6. RS error-correcting code decoder according to claim 4 is characterized in that, described controller judges whether described j equals N-1, if judged result is a "Yes", then obtains syndrome respectively from a described 2t memory address.
7. RS error-correcting code decoder according to claim 2 is characterized in that, described α is different constants corresponding to the various criterion value.
8. RS error-correcting code decoder according to claim 2 is characterized in that, described data cell is arranged to the 1st the code word r that described RS error-correcting code decoder receives when initialization
N-1
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102655443A (en) * | 2011-03-04 | 2012-09-05 | 上海华虹集成电路有限责任公司 | Partial parallel realizing method and device of Euclidean algorithm |
| CN102684708A (en) * | 2012-05-10 | 2012-09-19 | 天津大学 | Decoding device |
| CN103870354A (en) * | 2012-12-07 | 2014-06-18 | 北京兆易创新科技股份有限公司 | Error checking and error correction code encoder and coding method |
| CN103986475A (en) * | 2013-02-08 | 2014-08-13 | 阿尔特拉公司 | Parallel decomposition of reed solomon umbrella codes |
| CN104218957A (en) * | 2014-08-26 | 2014-12-17 | 中山大学 | RS decoder low in hardware complexity |
| CN108471315A (en) * | 2017-02-23 | 2018-08-31 | 杭州海康威视数字技术股份有限公司 | A kind of deletion-correcting coding method and device |
| CN109831278A (en) * | 2018-12-26 | 2019-05-31 | 中国电子科技集团公司第二十研究所 | A kind of wrong symbol delet method of CCSK-RS concatenated code |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1653699A (en) * | 2002-05-08 | 2005-08-10 | 汤姆森特许公司 | Method of soft-decision decoding of reed-solomon codes |
| US20090259921A1 (en) * | 2008-04-10 | 2009-10-15 | National Chiao Tung University | Method and apparatus for decoding shortened bch codes or reed-solomon codes |
| CN101674090A (en) * | 2009-09-28 | 2010-03-17 | 杭州电子科技大学 | 16-bit FEC decoding realization method for GPON |
| CN201789495U (en) * | 2010-06-01 | 2011-04-06 | 福建新大陆电脑股份有限公司 | Rs error correcting code decoder |
-
2010
- 2010-06-01 CN CN 201010188923 patent/CN101834617B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1653699A (en) * | 2002-05-08 | 2005-08-10 | 汤姆森特许公司 | Method of soft-decision decoding of reed-solomon codes |
| US20090259921A1 (en) * | 2008-04-10 | 2009-10-15 | National Chiao Tung University | Method and apparatus for decoding shortened bch codes or reed-solomon codes |
| CN101674090A (en) * | 2009-09-28 | 2010-03-17 | 杭州电子科技大学 | 16-bit FEC decoding realization method for GPON |
| CN201789495U (en) * | 2010-06-01 | 2011-04-06 | 福建新大陆电脑股份有限公司 | Rs error correcting code decoder |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102655443B (en) * | 2011-03-04 | 2016-11-02 | 上海华虹集成电路有限责任公司 | The part parallel revising Euclidean algorithm realizes device |
| CN102655443A (en) * | 2011-03-04 | 2012-09-05 | 上海华虹集成电路有限责任公司 | Partial parallel realizing method and device of Euclidean algorithm |
| CN102684708A (en) * | 2012-05-10 | 2012-09-19 | 天津大学 | Decoding device |
| CN102684708B (en) * | 2012-05-10 | 2015-02-04 | 天津大学 | Decoding device |
| CN103870354A (en) * | 2012-12-07 | 2014-06-18 | 北京兆易创新科技股份有限公司 | Error checking and error correction code encoder and coding method |
| CN103870354B (en) * | 2012-12-07 | 2018-04-17 | 北京兆易创新科技股份有限公司 | A kind of error checking and correction code decoder and interpretation method |
| CN103986475A (en) * | 2013-02-08 | 2014-08-13 | 阿尔特拉公司 | Parallel decomposition of reed solomon umbrella codes |
| CN103986475B (en) * | 2013-02-08 | 2018-12-28 | 阿尔特拉公司 | The parallel decomposition of Reed-Solomon umbellate form code |
| CN104218957B (en) * | 2014-08-26 | 2017-07-28 | 中山大学 | A kind of RS decoders of low hardware complexity |
| CN104218957A (en) * | 2014-08-26 | 2014-12-17 | 中山大学 | RS decoder low in hardware complexity |
| CN108471315A (en) * | 2017-02-23 | 2018-08-31 | 杭州海康威视数字技术股份有限公司 | A kind of deletion-correcting coding method and device |
| CN108471315B (en) * | 2017-02-23 | 2021-08-20 | 杭州海康威视数字技术股份有限公司 | Erasure decoding method and device |
| CN109831278A (en) * | 2018-12-26 | 2019-05-31 | 中国电子科技集团公司第二十研究所 | A kind of wrong symbol delet method of CCSK-RS concatenated code |
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