CN103762991B - Decoding method and system of BCH codes - Google Patents
Decoding method and system of BCH codes Download PDFInfo
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- CN103762991B CN103762991B CN201310714354.8A CN201310714354A CN103762991B CN 103762991 B CN103762991 B CN 103762991B CN 201310714354 A CN201310714354 A CN 201310714354A CN 103762991 B CN103762991 B CN 103762991B
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Abstract
The invention belongs to the field of error correction decoding, and provides a decoding method and system of BCH codes. The decoding method of the BCH codes comprises the steps that syndrome operation is carried out on the received BCH codes to obtain a syndrome polynomial, values of the syndrome polynomial are calculated successively through a parallel iterative decoding circuit on the basis of a BM algorithm without inverse operation so that error location polynomial coefficients and an error location polynomial can be obtained, the root of the error location polynomial is calculated through a Chien search method, and the error location is obtained through calculation. According to the step that the error location polynomial coefficients and the error location polynomial can be obtained through successive calculation of the parallel iterative decoding circuit, the iteration time of the parallel iterative decoding circuit and the calculation time of the Chien search method are matched, and multiplexing is carried out on the parallel iterative decoding circuit according to the iteration time. Therefore, according to the decoding method and system of the BCH codes, the number of adders, the number of multipliers and the number of registers for hardware implementation can be effectively reduced, complexity of combinational logic is reduced, and the size of a chip can be effectively reduced.
Description
Technical field
The present invention relates to error-correcting decoding field, more particularly to a kind of BCH code interpretation method and system.
Background technology
BCH（Bose-Chaudhuri-Hocquenghem, Bo Si-Cha Deheli-Huo Kun lattice nurses）Code is used as a kind of important
Error Correction of Coding mode, be widely used in the communications field and consumer electronics field.BCH decoders include three steps
Suddenly, first is that syndrome is calculated, and second step is mistake in computation position multinomial, and the 3rd step is then that money search finds out errors present simultaneously
Correct.Generally IBM is used when error location polynomial is hard-wired（Inversionless Berlecamp-
Massey, the Berlekamp-Mei Xi algorithms without inverse operation）Algorithm, and IBM algorithms are with the growth of its error correcting capability, and its hardware is opened
Pin can be greatly increased, and its combinational logic can be increasingly difficult to meet clock request, therefore how optimize the hardware configuration of IBM
Become extremely important.In fact, the most of the time of decoding spends in syndrome calculating and Chien（Money）In search, IBM algorithms
Time be relatively little, can suitably increase the execution cycle of IBM algorithms, reduce the complexity of circuit.
The content of the invention
For above-mentioned defect, it is an object of the invention to provide a kind of BCH code interpretation method and system, can effectively subtract
The quantity of adder, multiplier and register, reduces the complexity of combinational logic, so as to effectively reduce chip in small hardware realization
Area.
To achieve these goals, the present invention provides a kind of BCH code interpretation method, including：
Syndrome computing is carried out to receiving BCH code and obtains syndrome multinomial, to the value base of the associated polynomial
Error location polynomial coefficient and mistake are gradually calculated by Parallel Iteration Decoding Method circuit in the BM algorithms without inverse operation
Position multinomial, the root of error location polynomial is solved using money search method, solves errors present；
Error location polynomial coefficient and error location polynomial are gradually calculated by Parallel Iteration Decoding Method circuit
The step of include：The iteration time of the Parallel Iteration Decoding Method circuit is matched with the calculating time of the money search method,
And be multiplexed Parallel Iteration Decoding Method circuit according to the iteration time.
Interpretation method of the invention, carries out syndrome computing to receiving numeral and obtains the polynomial step of syndrome
Including：
Numeral R (x) to receiving is calculated, and obtains associated polynomial S (x)={ S0,S1……S2t-1,
Wherein, variable X is the element that finite field expands on domain, and t is the maximum mistake digit that BCH code can be corrected, syndrome S
X () is an one-dimension array, S0,S1……S2t-1It is the element in syndrome S (x), subscript 0,1 ... 2t-1 are syndrome S (x)
Index.
Interpretation method of the invention, error location polynomial system is gradually calculated by Parallel Iteration Decoding Method circuit
The step of number and error location polynomial, includes：
Setting initial values of the multinomial coefficient λ under zero degree iteration in the middle of auxiliary calculating isAuxiliary is set to calculate
Initial values of the middle multinomial coefficient λ under an iteration beFormer and later two bit-error locations are more in setting subsequent iteration
Initial values of the difference γ of item formula under zero degree iteration is γ(-1)=1, it is first under zero degree iteration that middle auxiliary variable δ γ are set
Initial value is δ(-1)=1；
Following iteration is performed up to r=2t-1, the value of r represents the r+1 times iteration,
It is error location polynomial coefficient to be asked that μ is, finally gives and obtains error location polynomial μ (x) eventually, wherein (t
=Nt1), N represents multiplexing number, and t1 represents the maximum error correcting capability after multiplexing.Multiplier adder number
Interpretation method of the invention, error location polynomial system is gradually calculated by Parallel Iteration Decoding Method circuit
In the step of number and error location polynomial, the Parallel Iteration Decoding Method circuit includes：Three groups of multipliers, one group of adder,
Three groups of registers and a group selector.
Interpretation method of the invention, error location polynomial system is gradually calculated by Parallel Iteration Decoding Method circuit
The step of number and error location polynomial, also includes：
When each iteration according to iterations carries out state transition if being determined, and time sum according to each iteration with
The calculating time of the money search method is matched, with the multiplexing to the Parallel Iteration Decoding Method circuit.
The present invention accordingly provides a kind of BCH code decoding system, including syndrome acquisition module, and error location polynomial is produced
Module and money search module,
Syndrome acquisition module is used to carrying out syndrome computing to receiving BCH code obtaining syndrome multinomial；
Error location polynomial generation module is used for logical based on the BM algorithms without inverse operation to the value of the associated polynomial
Cross Parallel Iteration Decoding Method circuit and be gradually calculated error location polynomial coefficient and error location polynomial；
Money search module is used to be solved using money search method the root of error location polynomial, solves errors present wherein,
When error location polynomial generation module is by the calculating of the iteration time of the Parallel Iteration Decoding Method circuit and the money search method
Between match, and Parallel Iteration Decoding Method circuit is multiplexed according to the iteration time.
Decoding system of the invention, the syndrome computing module to numeral R (x) for receiving based on carrying out
Calculate, obtain associated polynomial S (x)={ S0,S1……S2t-1, wherein, variable X is the element that finite field expands on domain, and t is BCH code
The maximum mistake digit that can be corrected, syndrome S (x) is an one-dimension array, S0,S1……S2t-1For in syndrome S (x)
Element, subscript 0,1 ... 2t-1 are the index of syndrome S (x).
Decoding system of the invention, error location polynomial generation module is used to set multinomial in the middle of auxiliary calculating
Initial value of the coefficient lambda under zero degree iteration beIt is first under an iteration that multinomial coefficient λ in the middle of auxiliary calculating is set
Initial value isThe difference γ for setting former and later two error location polynomials in subsequent iteration is initial under zero degree iteration
It is γ to be worth(-1)=1, it is δ to set initial values of the middle auxiliary variable δ γ under zero degree iteration(-1)=1；
Following iteration is performed up to r=2t-1, the value of r represents the r+1 times iteration,
It is error location polynomial coefficient to be asked that μ is, finally gives and obtains error location polynomial μ (x) eventually, wherein (t
=Nt1), N represents multiplexing number, and t1 represents the maximum error correcting capability after multiplexing.Multiplier adder number
Decoding system of the invention, the Parallel Iteration Decoding Method circuit includes：Three groups of multipliers, one group of adder,
Three groups of registers and a group selector.
Decoding system of the invention, error location polynomial generation module is additionally operable to be determined according to iterations often
When secondary iteration carries out state transition, and time sum according to each iteration and the calculating time of the money search method are carried out
Match somebody with somebody, with the multiplexing to the Parallel Iteration Decoding Method circuit.
The present invention by the calculating time match of the iteration time of Parallel Iteration Decoding Method circuit and money search method, and according to iteration
Be multiplexed for Parallel Iteration Decoding Method circuit by the time, so as to determine IBM by the size of error correcting capability and maximum decoding duration
The quantity of adder, multiplier and register that iterative algorithm is used, is compressed repeatedly by reducing the time of the hollow race of IBM algorithms
For the time so as to reduce complexity, with it is conventional realize algorithm and compare it is maximum decode duration it is equal in the case of reduce hardware
Adder in circuit, multiplier and register number are realized, so as to reach the purpose of optimization IBM structures.Whereby, the present invention
The quantity of adder, multiplier and register during hardware is realized can be effectively reduced, the complexity of combinational logic is reduced, so as to have
Effect reduces chip area.
Brief description of the drawings
Fig. 1 is a kind of theory diagram of BCH code decoding system of the invention；
Fig. 2 is the circuit diagram of the parallel decoding iterative circuit of existing IBM algorithms；
Fig. 3 is the circuit diagram of the parallel decoding iterative circuit of IBM algorithms in an embodiment of the present invention；
Fig. 4 is regular time-multiplexed structure chart in an embodiment of the present invention；
Fig. 5 is irregular time-multiplexed structure chart in another embodiment of the present invention；
Fig. 6 is a kind of flow chart of BCH code interpretation method of the invention.
Specific embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
As shown in figure 1, a kind of BCH code decoding system 100 of the invention, including syndrome acquisition module 10, errors present is more
Item formula generation module 20 and money search module 30,
Syndrome acquisition module 10 is used to carrying out syndrome computing to receiving BCH code obtaining syndrome multinomial.Tool
Body, the syndrome computing module is used to calculate numeral R (x) for receiving, and obtains associated polynomial S (x)={ S0,
S1……S2t-1, wherein, variable X is the element that finite field expands on domain, and t is the maximum mistake digit that BCH code can be corrected, adjoint
Formula S (x) is an one-dimension array, S0,S1……S2t-1It is the element in syndrome S (x), subscript 0,1 ... 2t-1 are syndrome S
The index of (x).
Error location polynomial generation module 20 is used to be based on the BM algorithms without inverse operation to the value of associated polynomial（I.e.
IBM algorithms）Error location polynomial coefficient and error location polynomial are gradually calculated by Parallel Iteration Decoding Method circuit.
Error location polynomial generation module 20 by the calculating time match of the iteration time of Parallel Iteration Decoding Method circuit and money search method,
And be multiplexed Parallel Iteration Decoding Method circuit according to iteration time.
Money search module 30 is used to be solved using money search method the root of error location polynomial, solves errors present.
Fig. 2 is the circuit diagram of the parallel decoding iterative circuit of existing IBM algorithms.As shown in Fig. 2 the parallel of IBM algorithms is translated
Code iterative circuit mainly includes three groups of multipliers, one group of adder, three groups of registers and a group selector.
The initial value of the Parallel Iteration Decoding Method circuit：δ(-1)=1, γ(-1)=1,
It is known：Si(i=0,1 ..., 2t-1), if represent that the r+1 times iteration, i.e. r=0 are represented with the value of alphabetical r changing for the first time
Generation, r=1 represents second iteration,..., r=2t-1 represents the 2t times iteration, and (r=0,1 ..., 2t-1) is represented and iterated to r=2t-1
Untill.
(r+1) secondary iterative process is divided into three below step：
Required error location polynomial μ (x) is finally given by t iteration.
In above-mentioned formula, r represents current state, and r+1 represents next state；I-th variable of i correspondences (post by multiplier
Storage and selector are numbered), and i ∈ (0, t)；Wherein Si(i=0,1 ..., 2t-1) represents the value of the syndrome of input；μ waits to ask
Error location polynomial coefficient；λ is multinomial coefficient in the middle of auxiliary is calculated；γ is that former and later two bit-error locations are more in subsequent iteration
The difference of item formula, also referred to as correction value；δ is middle auxiliary variable.
Needed when BCH is decoded searching for two steps by IBM and money, money search is generally using traversal GF
The method of the respective element in (2m) domain is looked for one's roots, generally calculate the time can it is more long than IBM a lot.In the present invention, in order to improve bandwidth
Pile line operation typically is used, IBM and money search is calculated time match（The calculating time that IBM and money are searched for it is equal or
Approximately equal）, and be multiplexed Parallel Iteration Decoding Method circuit according to iteration time.So as to by the size of error correcting capability and most
It is big to decode duration to determine the quantity of adder, multiplier and register that IBM iterative algorithms are used, by reducing IBM algorithms
The time of hollow race carrys out the contractible iteration time so as to reduce complexity, realizes algorithm and compares the appearance in maximum decoding with conventional
Adder in hardware circuit implementation, multiplier and register number are reduced Deng in the case of, so as to reach optimization IBM knots
The purpose of structure.Whereby, the present invention can effectively reduce the quantity of adder, multiplier and register during hardware is realized, reduction group
Logical complexity, so as to effectively reduce chip area.
In one embodiment, the iteration time of IBM algorithms is launched, the script of IBM algorithms is calculated into time t by meter
The calculating time is transformed into nt by the calculating logic unit that correlation is multiplexed during calculation, parallel in being multiplexed Fig. 2 in implementation process
The multiplier and adder of decoding iteration circuit the inside part reach the purpose of optimization circuit.Parallel decoding iteration electricity after optimization
Road is as shown in Figure 3.With reference to Fig. 2, in the parallel decoding iterative circuit of original IBM algorithms, multiplier has three groups, and adder has one
Group, three groups of register, one group of selector, every group has t；With reference to Fig. 3, optimizing latter every group has t1 (t=Nt1)；It is so false
If it is T originally to calculate the time once, corresponding calculating can be just completed after must calculating n times using multiplex mode now, when
Between be NT；Adopting can launch the calculating time of IBM in this way, and the calculating time match then searched for money gets up,
I.e. so that the time NT after optimization is equal to the time of money search, area and the optimal principle of bandwidth are reached.
In iterative decoding circuit in figure 3, error location polynomial generation module is used to set many in the middle of auxiliary calculating
Initial values of the binomial coefficient λ under zero degree iteration beSetting auxiliary calculates middle multinomial coefficient λ under an iteration
Initial value beThe difference γ of former and later two error location polynomials is under zero degree iteration in setting subsequent iteration
Initial value is γ(-1)=1, it is δ to set initial values of the middle auxiliary variable δ γ under zero degree iteration(-1)=1；
And for performing following iteration up to r=2t-1, the value of r represents the r+1 times iteration,
In fig. 2, it is necessary to t multiplier and adder calculate 1 clock obtains δ(r), and in figure 3, now only need
t1Individual multiplier and adder, however it is necessary that N number of clock just can be with δ(r)Value, while can reduce pilot process storage variable
The number of register.After multiplexing in calculating process, present 1 is reduced to per N number of register, adder and multiplier,
The input and output of circuit keep constant.The now multiplexing of circuit from the time rule carry out, originally each time
Iteration time T transformed into NT, referred to as regular time division multiplexing mode.t1=t2=Λ=tN=T, Fig. 4 are that the rule is time-multiplexed
Structure chart.
And consider the calculating process of IBM, in iteration early stage, there are the feelings that formula feeding is also not accompanied by some registers
Condition, now these corresponding circuits be equivalently employed without carrying out any operation, hence it is evident that there is serious time wastes.Assuming that maximum is entangled
Wrong ability is t, and iteration coefficient is k, then for IBM algorithms, associated polynomial SiThe input of (i=0,1 ..., 2t-1) is suitable
Sequence is as shown in table 1；
Table 1
| K（Iteration coefficient） | Input syndrome |
| 0 | S1,0 |
| 2 | S3, S2 |
| 4 | S5, S4 |
| ……… | ………. |
| 2t-4 | S2t-3, S2t-4 |
| 2t-2 | S2t-1, S2t-2 |
For t register of IBM hardware circuits,
As k=0, R0 and R1 have value, and the value of other registers is 0；
As k=2, R0, R1, R2, R3 have value, and the value of other registers is 0；
…
As k=k0, all of register has value；
For k0 to 2t-2, all of register has value.So as in iteration early stage, exist does not have also in some registers
Syndrome feeding situation, now these corresponding circuits be equivalently employed without carrying out any operation, hence it is evident that there is the serious time
Waste
From computing formula,
During for r=0,
During for r=1,
……
For r=k（k<(t+1)/2）When,
For r=k（k>(t+1)/2）When,
Therefore, in another embodiment, Time Division Multiplexing Fabric can select δ according to iterations r(r)The calculating time,
So algorithm further optimizes, and becomes irregular Time Division Multiplexing Fabric figure as shown in Figure 5.So can be shown in chart 4
The empty time utilization for running of circuit early stage gets up, and reduces the time that iterative algorithm is calculated.Namely error location polynomial generation module
It is additionally operable to determine when each iteration carries out state transition, and the time sum according to each iteration and institute according to iterations
The calculating time for stating money search method is matched, with the multiplexing to Parallel Iteration Decoding Method circuit.Now during the calculating of multiplexing algorithm
Between be it is irregular be referred to as irregular time division multiplex；Multiplexing scheme shown in Fig. 5, you can not sent into also with register value
（This duration is 0）Part to being used, save the corresponding calculating time, so under identical iteration time, Fig. 5 is needed
The multiplier and adder wanted are less, so as to reduce chip area.The scheme that Fig. 4 and Fig. 5 are used rises with original project plan comparison
To there is certain effect of optimization, and the effect of Fig. 5 can become apparent from, but complexity can also rise.On the one hand answered using the time-division
Scheme, on the other hand determines when this iteration carries out state transition using iterations, reduces the empty race time, so that
In the case where iteration time is fixed, the quantity of multiplier, adder and register is effectively reduced, and then reduce chip area.
Fig. 6 is a kind of flow chart of BCH code interpretation method of the invention, and it is realized by system as shown in Figure 1, the method
Including：
Step S601, carries out syndrome computing to receiving BCH code and obtains syndrome multinomial.Preferably, this step
Suddenly include：Numeral R (x) to receiving is calculated, and obtains associated polynomial S (x)={ S0,S1……S2t-1, wherein, variable
X is the element that finite field expands on domain, and t is the maximum mistake digit that BCH code can be corrected, and syndrome S (x) is a dimension
Group, S0,S1……S2t-1It is the element in syndrome S (x), subscript 0,1 ... 2t-1 are the index of syndrome S (x).
Step S602, the value to associated polynomial passes through Parallel Iteration Decoding Method circuit gradually based on the BM algorithms without inverse operation
Error location polynomial coefficient and error location polynomial are calculated, by the iteration time of Parallel Iteration Decoding Method circuit and institute
The calculating time for stating money search method is matched, and is multiplexed Parallel Iteration Decoding Method circuit according to the iteration time.It is excellent
Choosing, Parallel Iteration Decoding Method circuit includes：Three groups of multipliers, one group of adder, three groups of registers and a group selector.
Step S603, the root of error location polynomial is solved using money search method, solves errors present.
Error location polynomial coefficient and error location polynomial are gradually calculated by Parallel Iteration Decoding Method circuit
The step of include：.
In step S602, error location polynomial coefficient and mistake are gradually calculated by Parallel Iteration Decoding Method circuit
The polynomial step in position includes by mistake：Setting initial values of the multinomial coefficient λ under zero degree iteration in the middle of auxiliary calculating isSetting initial values of the multinomial coefficient λ under an iteration in the middle of auxiliary calculating isSubsequent iteration is set
In the initial values of the difference γ under zero degree iteration of former and later two error location polynomials be γ(-1)=1, middle auxiliary is set and is become
Initial values of the amount δ γ under zero degree iteration is δ(-1)=1；
Following iteration is performed up to r=2t-1, the value of r represents the r+1 times iteration,
It is error location polynomial coefficient to be asked that μ is, finally gives and obtains error location polynomial μ (x) eventually, wherein (t
=Nt1), N represents multiplexing number, and t1 represents the maximum error correcting capability after multiplexing.Multiplier adder number
Preferably, in step S602, error location polynomial is gradually calculated by Parallel Iteration Decoding Method circuit
The step of coefficient and error location polynomial, also includes：
When each iteration according to iterations carries out state transition if being determined, and time sum according to each iteration with
The calculating time of the money search method is matched, with the multiplexing to the Parallel Iteration Decoding Method circuit.
In sum, the present invention is by the calculating time match of the iteration time of Parallel Iteration Decoding Method circuit and money search method,
And be multiplexed Parallel Iteration Decoding Method circuit according to iteration time, so that the size and maximum decoding duration that pass through error correcting capability
Come determine IBM iterative algorithms use adder, multiplier and register quantity, by reduce the hollow race of IBM algorithms when
Between carry out the contractible iteration time so as to reduce complexity, with it is conventional realize algorithm and compare it is maximum decode duration it is equal in the case of
Adder in hardware circuit implementation, multiplier and register number are reduced, so as to reach the purpose of optimization IBM structures.
Whereby, the present invention can effectively reduce the quantity of adder, multiplier and register during hardware is realized, reduce answering for combinational logic
Miscellaneous degree, so as to effectively reduce chip area.
Certainly, the present invention can also have other various embodiments, ripe in the case of without departing substantially from spirit of the invention and its essence
Know those skilled in the art and work as and various corresponding changes and deformation, but these corresponding changes and change can be made according to the present invention
Shape should all belong to the protection domain of appended claims of the invention.
Claims (10)
1. a kind of BCH code interpretation method, it is characterised in that including：
Syndrome computing is carried out to receiving BCH code and obtains syndrome multinomial, the polynomial value of the syndrome is based on
BM algorithms without inverse operation are gradually calculated error location polynomial coefficient and error bit by Parallel Iteration Decoding Method circuit
Multinomial is put, the root of error location polynomial is solved using money search method, solve errors present；
The step of error location polynomial coefficient and error location polynomial is gradually calculated by Parallel Iteration Decoding Method circuit
Suddenly include：The iteration time of the Parallel Iteration Decoding Method circuit is matched with the calculating time of the money search method, and root
Parallel Iteration Decoding Method circuit is multiplexed according to the iteration time.
2. interpretation method according to claim 1, it is characterised in that carry out syndrome computing to receiving numeral and obtain companion
Include with the polynomial step of formula：
Numeral R (x) to receiving is calculated, and obtains syndrome multinomial S (x)={ S0,S1……S2t-1,
Wherein, variable X is the element that finite field expands on domain, and t is the maximum mistake digit that BCH code can be corrected, syndrome S (x)
It is an one-dimension array, S0,S1……S2t-1It is the element in syndrome S (x), subscript 0,1 ... 2t-1 are the rope of syndrome S (x)
Draw.
3. interpretation method according to claim 2, it is characterised in that be gradually calculated by Parallel Iteration Decoding Method circuit
The step of error location polynomial coefficient and error location polynomial, includes：
Setting initial values of the multinomial coefficient λ under zero degree iteration in the middle of auxiliary calculating isAuxiliary is set and calculates middle
Initial values of the multinomial coefficient λ under an iteration beFormer and later two error location polynomials in subsequent iteration are set
Initial values of the difference γ under zero degree iteration be γ(-1)=1, it is initial under zero degree iteration that middle auxiliary variable δ γ are set
It is δ to be worth(-1)=1；
Following iteration is performed up to r=2t-1, the value of r represents the r+1 times iteration,
(3)γ(r)=δ(r)γ(r-1):δ(r),
It is error location polynomial coefficient to be asked that μ is, finally gives and obtains error location polynomial μ (x) eventually, wherein (t=
Nt1), N represents multiplexing number, and t1 represents the maximum error correcting capability after multiplexing.Multiplier adder number.
4. interpretation method according to claim 3, it is characterised in that be gradually calculated by Parallel Iteration Decoding Method circuit
In the step of error location polynomial coefficient and error location polynomial, the Parallel Iteration Decoding Method circuit includes：Three groups multiply
Musical instruments used in a Buddhist or Taoist mass, one group of adder, three groups of registers and a group selector.
5. interpretation method according to claim 2, it is characterised in that be gradually calculated by Parallel Iteration Decoding Method circuit
The step of error location polynomial coefficient and error location polynomial, also includes：
When each iteration according to iterations carries out state transition if being determined, and time sum according to each iteration with it is described
The calculating time of money search method is matched, with the multiplexing to the Parallel Iteration Decoding Method circuit.
6. a kind of BCH code decoding system, it is characterised in that including syndrome acquisition module, error location polynomial generation module
And money search module,
Syndrome acquisition module is used to carrying out syndrome computing to receiving BCH code obtaining syndrome multinomial；
Error location polynomial generation module is used to pass through the polynomial value of the syndrome based on the BM algorithms without inverse operation
Parallel Iteration Decoding Method circuit is gradually calculated error location polynomial coefficient and error location polynomial；
Money search module is used to be solved using money search method the root of error location polynomial, solves errors present wherein, mistake
Position multinomial generation module is by the calculating time of the iteration time of the Parallel Iteration Decoding Method circuit and the money search method
Match somebody with somebody, and be multiplexed Parallel Iteration Decoding Method circuit according to the iteration time.
7. decoding system according to claim 6, it is characterised in that the syndrome computing module is used for receiving
Numeral R (x) is calculated, and obtains syndrome multinomial S (x)={ S0,S1……S2t-1,
Wherein, variable X is the element that finite field expands on domain, and t is the maximum mistake digit that BCH code can be corrected, syndrome S (x)
It is an one-dimension array, S0,S1……S2t-1It is the element in syndrome S (x), subscript 0,1 ... 2t-1 are the rope of syndrome S (x)
Draw.
8. decoding system according to claim 6, it is characterised in that error location polynomial generation module is used to set auxiliary
Initial values of the multinomial coefficient λ under zero degree iteration in the middle of calculating is helped to beAuxiliary is set and calculates middle multinomial coefficient λ
Initial value under an iteration isThe difference γ for setting former and later two error location polynomials in subsequent iteration exists
Initial value under zero degree iteration is γ(-1)=1, it is δ to set initial values of the middle auxiliary variable δ γ under zero degree iteration(-1)=1；
Following iteration is performed up to r=2t-1, the value of r represents the r+1 times iteration,
(3)γ(r)=δ(r)γ(r-1):δ(r),
It is error location polynomial coefficient to be asked that μ is, finally gives and obtains error location polynomial μ (x) eventually, wherein (t=
Nt1), N represents multiplexing number, and t1 represents the maximum error correcting capability after multiplexing.Multiplier adder number
9. decoding system according to claim 8, it is characterised in that the Parallel Iteration Decoding Method circuit includes：Three groups multiply
Musical instruments used in a Buddhist or Taoist mass, one group of adder, three groups of registers and a group selector.
10. decoding system according to claim 7, it is characterised in that error location polynomial generation module is additionally operable to root
When each iteration according to iterations carries out state transition if being determined, and time sum according to each iteration is searched for the money
The calculating time of method is matched, with the multiplexing to the Parallel Iteration Decoding Method circuit.
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| CN106961282A (en) * | 2017-03-31 | 2017-07-18 | 山东超越数控电子有限公司 | A kind of Hardware Implementation of the High Speed I BM algorithm structures based on binary BCH code |
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| CN108845890A (en) * | 2018-05-07 | 2018-11-20 | 西安电子科技大学 | Data verification method based on Nand flash storage array |
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