CN103580700A - Syndrome solving and ECC decoding circuit and method of code word polynomials - Google Patents
Syndrome solving and ECC decoding circuit and method of code word polynomials Download PDFInfo
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- CN103580700A CN103580700A CN201210276155.9A CN201210276155A CN103580700A CN 103580700 A CN103580700 A CN 103580700A CN 201210276155 A CN201210276155 A CN 201210276155A CN 103580700 A CN103580700 A CN 103580700A
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Abstract
The invention discloses a syndrome solving and ECC decoding circuit and method of code word polynomials. The syndrome solving circuit of the code word polynomial comprises a first trigger, a first multiplication unit, a second multiplication unit, an adder and a second trigger. The input end of the first multiplication unit is connected with the output end of the first trigger, and the output end of the first multiplication unit is connected with the input end of the first trigger. The first input end of the second multiplication unit is connected between the first multiplication unit and the first trigger, and the second input end of the second multiplication unit is used for receiving coefficients of the first code word polynomial and the second code word polynomial respectively. The first input end of the adder is connected with the output end of the second multiplication unit. The input end of the second trigger is connected with the output end of the adder, and the output end of the second trigger is connected with the second input end of the adder. By means of the syndrome solving and EEC decoding circuit and method of the code word polynomials, the problem that a syndrome solving circuit of the code word polynomials in the prior art is large in area is solved, and therefore the effects of simplifying the syndrome solving circuit of the code word polynomials and reducing the area of the solving circuit are achieved.
Description
Technical field
The present invention relates to circuit field, in particular to a kind of syndrome solves and ECC decodes circuit and method of codeword polynome.
Background technology
In the decoding algorithm of error checking and error correction (Error Correcting Code is called for short ECC), need to carry out syndrome calculating to codeword polynome, the method for calculating syndrome has two kinds: the one, by the element α in Galois Field
idirectly be updated in the code word of reception; The 2nd, the code word receiving is done to α
icorresponding minimal polynomial is processed and is obtained remainder polynomid, and then by the element α in Galois Field
isubstitution remainder polynomid.These two kinds of methods all need the coefficient of each code word component in codeword polynome or remainder polynomid and the α of corresponding power
imultiply each other, not only need first by a large amount of NOR gate circuits, to solve the α of each power
i, also need the α of each power solving
ithe multiplication of the code word component by a large amount of NOR gate circuits and corresponding power, therefore, need huge XOR gate network to support, the computational methods of the syndrome that this kind of huge XOR gate network of needs done to support, can make the fan-out in ECC decoding path larger, not only increase the area of ECC decoding circuit, also increased the complexity of optimizing XOR gate network, made ECC decoding circuit more complicated.
The larger problem of syndrome solving circuit area for codeword polynome in correlation technique, not yet proposes effective solution at present.
Summary of the invention
Main purpose of the present invention is to provide a kind of syndrome solves and ECC decodes circuit and method of codeword polynome, to solve the larger problem of syndrome solving circuit area of codeword polynome in prior art.
To achieve these goals, according to an aspect of the present invention, provide a kind of syndrome solving circuit of codeword polynome, having comprised: the first trigger; The first multiplication unit, the input of the first multiplication unit is connected with the output of the first trigger, the output of the first multiplication unit is connected with the input of the first trigger, for the multiplier factor in the multiplier factor from the first trigger and the first multiplication unit is multiplied each other, and acquired results is sent to the first trigger; The second multiplication unit, the first input end of the second multiplication unit is connected between the first multiplication unit and the first trigger, the second input of the second multiplication unit is for receiving respectively the first codeword polynome and the polynomial coefficient of the second code word, for the coefficient of the first codeword polynome is multiplied by the first multiplier factor receiving, obtain the first Output rusults, and the polynomial coefficient of the second code word is multiplied by the second multiplier factor receiving, obtain the second Output rusults; Adder, the first input end of adder is connected with the output of the second multiplication unit, for receiving the first Output rusults and the second Output rusults, and the first Output rusults and the second Output rusults is added; And second trigger, the input of the second trigger is connected with the output of adder, the output of the second trigger is connected with the second input of adder, for adder is cumulative finish after the accumulation result of output adder, obtain syndrome.
Further, the first multiplication unit comprises the first multiplier and the second multiplier, the second multiplication unit comprises the 3rd multiplier and the 4th multiplier, wherein, the input of the first multiplier is connected with the output of the first trigger, the output of the first multiplier is connected with the input of the second multiplier, the output of the second multiplier is connected with the input of the first trigger, the first input end of the 3rd multiplier is connected between the first trigger and the first multiplier, the second input of the 3rd multiplier is for receiving respectively the coefficient of the first component and the coefficient of polynomial the first component of the second code word of the first codeword polynome, the 3rd output of multiplier and the first input end of adder are connected, for the coefficient of the first component of the first codeword polynome being multiplied by the first multiplier factor of the first trigger output, obtain the sub-result of the first output, and the second multiplier factor that the coefficient of polynomial the first component of the second code word is multiplied by the first trigger output, obtain the sub-result of the second output, the first input end of the 4th multiplier is connected between the first multiplier and the second multiplier, the second input of the 4th multiplier is for receiving respectively the coefficient of second component and the coefficient of the polynomial second component of the second code word of the first codeword polynome, the output of the 4th multiplier is connected with the second input of adder, for the coefficient of the second component of the first codeword polynome being multiplied by the first multiplier factor of the first multiplier output, obtain the sub-result of the 3rd output, and the second multiplier factor that the coefficient of the polynomial second component of the second code word is multiplied by the first multiplier output, obtain the sub-result of the 4th output, wherein, adder is also for calculating the sub-result of the first output and the sub-result sum of the 3rd output, obtain the first Output rusults, and calculate the sub-result of the second output and the 4th and export sub-result sum, obtain the second Output rusults.
Further, the multiplier factor in the first multiplier and the second multiplier is the element α in Galois Field
i.
Further, syndrome counting circuit also comprises: selector, the first input end of selector is for receiving the element α of Galois Field
0, the second input of selector is connected with the output of the first multiplication unit, and the output of selector is connected with the first trigger.
To achieve these goals, according to a further aspect in the invention, provide a kind of ECC decoding circuit of codeword polynome, the ECC decoding circuit of this codeword polynome comprises any syndrome solving circuit that foregoing of the present invention provides.
To achieve these goals, according to a further aspect in the invention, provide a kind of syndrome of codeword polynome to solve processing method, this syndrome solves any syndrome solving circuit that processing method provides for foregoing of the present invention, wherein, syndrome solving circuit comprises the first trigger, the second trigger, the first multiplication unit, the second multiplication unit and adder, syndrome solves processing method and comprises: by the first multiplication unit, the multiplier factor in the multiplier factor from the first trigger and the first multiplication unit is multiplied each other, and acquired results is sent to the first trigger, by the second multiplication unit, the coefficient of the first codeword polynome receiving is multiplied by the first multiplier factor receiving, obtain the first Output rusults, and the polynomial coefficient of the second code word receiving is multiplied by the second multiplier factor receiving, obtain the second Output rusults, by adder, receive the first Output rusults and the second Output rusults, and the first Output rusults and the second Output rusults are added, and by the accumulation result of the second trigger output adder after the cumulative end of adder, obtain syndrome.
Further, the first multiplication unit comprises the first multiplier and the second multiplier, the second multiplication unit comprises the 3rd multiplier and the 4th multiplier, wherein, by the first multiplication unit, the multiplier factor in the multiplier factor from the first trigger and the first multiplication unit is multiplied each other, and acquired results is sent to the first trigger comprises: the first multiplier multiplies each other the multiplier factor in the multiplier factor from the first trigger and the first multiplier, and acquired results is sent to the second multiplier, and second multiplier the multiplier factor in the acquired results from the first multiplier and the second multiplier is multiplied each other, and acquired results is sent to the first trigger, by the second multiplication unit, the coefficient of the first codeword polynome receiving is multiplied by the first multiplier factor receiving, obtain the first Output rusults, and the polynomial coefficient of the second code word receiving is multiplied by the second multiplier factor receiving, obtaining the second Output rusults comprises: the 3rd multiplier is multiplied by the coefficient of the first component of the first codeword polynome the first multiplier factor of the first trigger output, obtain the sub-result of the first output, and the second multiplier factor that the coefficient of polynomial the first component of the second code word is multiplied by the first trigger output, obtain the sub-result of the second output, the 4th multiplier is multiplied by the coefficient of the second component of the first codeword polynome the first multiplier factor of the first multiplier output, obtain the sub-result of the 3rd output, and the second multiplier factor that the coefficient of the polynomial second component of the second code word is multiplied by the first multiplier output, obtain the sub-result of the 4th output, and adder calculating the first sub-result of output and the sub-result sum of the 3rd output, obtain the first Output rusults, and calculate the sub-result of the second output and the sub-result sum of the 4th output, obtain the second Output rusults.
To achieve these goals, according to a further aspect in the invention, a kind of ECC coding/decoding method of codeword polynome is provided, and the syndrome of any codeword polynome that this ECC coding/decoding method provides by foregoing of the present invention solves the syndrome that processing method obtains codeword polynome; And according to the syndrome of codeword polynome, codeword polynome is carried out to ECC error correction.
By the present invention, adopt and comprise following structure syndrome solving circuit: the first trigger; The first multiplication unit, the input of the first multiplication unit is connected with the output of the first trigger, the output of the first multiplication unit is connected with the input of the first trigger, for the multiplier factor in the multiplier factor from the first trigger and the first multiplication unit is multiplied each other, and acquired results is sent to the first trigger; The second multiplication unit, the first input end of the second multiplication unit is connected between the first multiplication unit and the first trigger, the second input of the second multiplication unit is for receiving respectively the first codeword polynome and the polynomial coefficient of the second code word, for the coefficient of the first codeword polynome is multiplied by the first multiplier factor receiving, obtain the first Output rusults, and the polynomial coefficient of the second code word is multiplied by the second multiplier factor receiving, obtain the second Output rusults; Adder, is connected with the output of the second multiplication unit, for receiving the first Output rusults and the second Output rusults, and the first Output rusults and the second Output rusults is added; And second trigger, be connected with the output of adder, for adder is cumulative finish after the accumulation result of output adder, obtain syndrome.By the second input via the second multiplication unit, receive respectively the first codeword polynome and the polynomial coefficient of the second code word, and the output of the second multiplication unit is connected with adder, realized codeword polynome has been inputted to syndrome solving circuit according to the mode of grouping parallel, and the intermediate variable of the syndrome corresponding with each group codeword polynome solving is added up, and export final accumulation result when cumulative end, and then obtain the polynomial syndrome of original code word; by by output feedback link to the first trigger of the first multiplication unit, only realized and can solve by a set of the first multiplication unit and the first trigger the multiplier factor that obtains each power, by the first input end of the second multiplication unit being connected between the first multiplication unit and the first trigger, realized the second multiplication unit when receiving codeword polynome and calling from its first input end the multiplier factor receiving each time, all can access the multiplier factor of the corresponding power of coefficient of the codeword polynome receiving with its second input, and then realized in to syndrome solution procedure at every turn by the corresponding codeword polynome of multiplier factor substitution of corresponding power time all without increasing the multiplication unit being formed by NOR gate circuit, also be, by by output feedback link to the first trigger of the first multiplication unit, and the first input end of the second multiplication unit is connected between the first multiplication unit and the first trigger, realized and only relied on a set of solving circuit can solve the syndrome of the codeword polynome of different component numbers, solved the larger problem of syndrome solving circuit area of codeword polynome in prior art, and then reached the polynomial syndrome solving circuit of simplification code word, reduce the effect of solving circuit area.
Accompanying drawing explanation
The accompanying drawing that forms the application's a part is used to provide a further understanding of the present invention, and schematic description and description of the present invention is used for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 is according to the schematic diagram of the syndrome solving circuit of the embodiment of the present invention;
Fig. 2 is the schematic diagram of syndrome solving circuit according to the preferred embodiment of the invention;
Fig. 3 is according to the structured flowchart of the syndrome solving circuit of the embodiment of the present invention;
Fig. 4 is according to the operation principle flow chart of the syndrome solving circuit of the embodiment of the present invention; And
Fig. 5 is according to the flow chart of the ECC coding/decoding method of the embodiment of the present invention.
Embodiment
It should be noted that, in the situation that not conflicting, embodiment and the feature in embodiment in the application can combine mutually.Describe below with reference to the accompanying drawings and in conjunction with the embodiments the present invention in detail.
The embodiment of the present invention provides a kind of syndrome solving circuit of codeword polynome, below the syndrome solving circuit of codeword polynome that the embodiment of the present invention is provided be specifically introduced.
Fig. 1 is according to the schematic diagram of the syndrome solving circuit of the embodiment of the present invention, and as shown in Figure 1, the syndrome solving circuit of the codeword polynome of this embodiment comprises the first trigger, the first multiplication unit, the second multiplication unit, adder and the second trigger.
Particularly, the input of the first multiplication unit is connected with the output of the first trigger, and the output of the first multiplication unit is connected with the input of the first trigger; The first input end of the second multiplication unit is connected between the first multiplication unit and the first trigger, the second input of the second multiplication unit is for receiving respectively the first codeword polynome and the polynomial coefficient of the second code word, wherein, the first codeword polynome and the second codeword polynome are the flanking sequence in original code word multinomial, and the first codeword polynome is identical with the code word component in the second codeword polynome; The first input end of adder is connected with the output of the second multiplication unit; The input of the second trigger is connected with the output of adder, and the output of the second trigger is connected with the second input of adder.
The operation principle of the syndrome solving circuit of the embodiment of the present invention is: after solving circuit powers on and starts working, the first trigger reception control signal carries out initialization, owing to all storing multiplication factor in the first trigger and the first multiplication unit, when the second input of the second multiplication unit receives the coefficient (being assumed to be the coefficient of the first codeword polynome) of codeword polynome for the first time, the second multiplication unit can (be assumed to be the first multiplier factor by the coefficient of the first codeword polynome receiving from the second input and the multiplier factor receiving for the first time from its first input end, , the multiplier factor being sent out for the first time by the output of the first trigger) multiply each other, complete the substitution of Galois Field element, obtain the intermediate variable of the syndrome corresponding with the first codeword polynome, i.e. the first Output rusults, and this first Output rusults is sent to adder, adder is saved to this first Output rusults in the second trigger, when the first trigger is exported its inner multiplier factor, the first multiplication unit also can receive this multiplier factor, and the multiplier factor receiving and the multiplier factor of self are once multiplied each other, the result of the gained that multiplies each other is fed back to the first trigger from the output of the first multiplication unit, the new multiplier factor of the first trigger using the multiplier factor receiving as storage inside simultaneously, when the second input of the second multiplication unit receives the coefficient (being assumed to be the polynomial coefficient of the second code word) of codeword polynome for the second time, the second multiplication unit can (be assumed to be the second multiplier factor by the polynomial coefficient of the second code word receiving from the second input and the multiplier factor receiving for the second time from its first input end, , the multiplier factor being sent out for the second time by the output of the first trigger, also be the multiplier factor after the first trigger upgrades) multiply each other, complete the substitution of Galois Field element, obtain the intermediate variable of the syndrome corresponding with the second codeword polynome, i.e. the second Output rusults, and this second Output rusults is sent to adder, simultaneously, the second trigger also can be by last result of calculation (, the first Output rusults) feed back to adder, adder is done the first Output rusults and the second Output rusults after Galois Field addition, addition result is stored in the second trigger again, when the first trigger is exported its inner multiplier factor for the second time, the first multiplication unit equally also can receive this multiplier factor, and the multiplier factor receiving and the multiplier factor of self are once multiplied each other again, the result of the gained that multiplies each other is fed back to the first trigger from the output of the first multiplication unit, the new multiplier factor of the first trigger using the multiplier factor again receiving as storage inside simultaneously, circulation successively, until the second multiplication unit no longer receives codeword polynome, also, until the input of the coefficient of codeword polynome is complete, when adder completes after last Galois Field addition, the final accumulation result in the second trigger is the syndrome of codeword polynome.
By the second input via the second multiplication unit, receive respectively the first codeword polynome and the polynomial coefficient of the second code word, and the output of the second multiplication unit is connected with adder, realized codeword polynome has been inputted to syndrome solving circuit according to the mode of grouping parallel, and the intermediate variable of the syndrome corresponding with each group codeword polynome solving is added up, and export final accumulation result when cumulative end, and then obtain the polynomial syndrome of original code word; by by output feedback link to the first trigger of the first multiplication unit, only realized and can solve by a set of the first multiplication unit and the first trigger the multiplier factor that obtains each power, by the first input end of the second multiplication unit being connected between the first multiplication unit and the first trigger, realized the second multiplication unit when receiving codeword polynome and calling from its first input end the multiplier factor receiving each time, all can access the multiplier factor of the corresponding power of coefficient of the codeword polynome receiving with its second input, and then realized in to syndrome solution procedure at every turn by the corresponding codeword polynome of multiplier factor substitution of corresponding power time all without increasing the multiplication unit being formed by NOR gate circuit, also be, by by output feedback link to the first trigger of the first multiplication unit, and the first input end of the second multiplication unit is connected between the first multiplication unit and the first trigger, realized and only relied on a set of solving circuit can solve the syndrome of the codeword polynome of different component numbers, solved the larger problem of syndrome solving circuit area of codeword polynome in prior art, and then reached the polynomial syndrome solving circuit of simplification code word, reduce the effect of solving circuit area.
Fig. 2 is the schematic diagram of syndrome solving circuit according to the preferred embodiment of the invention, as shown in Figure 2, the solving circuit of the syndrome of the preferred embodiment of the present invention and the difference of the solving circuit shown in Fig. 1 are, in the solving circuit of the preferred embodiment of the present invention, the first multiplication unit and the second multiplication unit include a plurality of multipliers, particularly, in the first multiplication unit, the number of multiplier is identical with the number of multiplier in the second multiplication unit, physical circuit annexation is: each multiplier in the first multiplication unit is connected successively, input is connected with the output of the first trigger, the input of output feedback link to the first trigger, first multiplier one end in the second multiplication unit is connected between the first multiplier in the first trigger and the first multiplication unit, and the other end is connected to adder, second multiplier one end in the second multiplication unit is connected between the first multiplier and the second multiplier in the first multiplication unit, and the other end is connected to adder, the like.
With the multiplier in the first multiplication unit, be respectively the first multiplier and the second multiplier, multiplier in the second multiplication unit is respectively the 3rd multiplier and the 4th multiplier is the operation principle of the syndrome solving circuit of the example explanation preferred embodiment of the present invention, specific as follows:
After solving circuit powers on and starts working, the first trigger reception control signal carries out initialization, and owing to all storing multiplication factor in the first trigger, the first multiplier and the second multiplier, (the first multiplier and the second multiplier inner multiplication factor are the element α in Galois Field
i, concrete i value can be determined according to the error correcting capability of the ECC decoding circuit of this syndrome solving circuit of application), when the second input of the 3rd multiplier receives the coefficient of the first component of codeword polynome (being assumed to be the first codeword polynome) for the first time, the 3rd multiplier can be by the first component coefficient of the first codeword polynome and the multiplier factor receiving for the first time from its first input end (, the multiplier factor being sent out for the first time by the output of the first trigger) multiply each other, complete the substitution of Galois Field element, obtain the intermediate variable of the syndrome corresponding with the first component of the first codeword polynome, and the intermediate variable of the syndrome corresponding with the first component of the first codeword polynome is sent to adder, meanwhile, the second input of the 4th multiplier receives the coefficient of the second component of the first codeword polynome, and by the second component coefficient of the first codeword polynome and the multiplier factor that receives for the first time from its first input end (, the multiplier factor being sent out for the first time by the output of the first multiplier) multiply each other, complete the substitution of Galois Field element, obtain the intermediate variable of the syndrome corresponding with the second component of the first codeword polynome, and the intermediate variable of the corresponding syndrome of the second component with the first codeword polynome is sent to adder, the intermediate variable of adder to the syndrome corresponding with the first component of the first codeword polynome receiving, the intermediate variable of the syndrome corresponding with the second component of the first codeword polynome carries out Galois Field addition, obtain the intermediate variable of the syndrome corresponding with the first codeword polynome, i.e. the first Output rusults, and this first Output rusults is stored to the second trigger, when the first trigger is exported its inner multiplier factor, the first multiplier also can receive this multiplier factor, and the multiplier factor receiving and the multiplier factor of self are once multiplied each other, and the result of the gained that multiplies each other is sent to the second multiplier simultaneously, the second multiplier once multiplies each other the multiplier factor receiving and the multiplier factor of self, the result of the gained that multiplies each other is fed back to the first trigger from the output of the second multiplier, the new multiplier factor of the first trigger using the multiplier factor receiving as storage inside simultaneously,
When the second input of the 3rd multiplier receives the coefficient of the first component of codeword polynome (being assumed to be the second codeword polynome) for the second time, the 3rd multiplier can be by polynomial the first component coefficient of the second code word and the multiplier factor receiving for the second time from its first input end (, the multiplier factor being sent out for the second time by the output of the first trigger) multiply each other, complete the substitution of Galois Field element, obtain the intermediate variable of the syndrome corresponding with polynomial the first component of the second code word, and the intermediate variable of the syndrome corresponding with polynomial the first component of the second code word is sent to adder, meanwhile, the second input of the 4th multiplier receives the coefficient of the polynomial second component of the second code word, and by the polynomial second component coefficient of the second code word and the multiplier factor that receives for the second time from its first input end (, the multiplier factor being sent out for the second time by the output of the first multiplier) multiply each other, complete the substitution of Galois Field element, obtain the intermediate variable of the syndrome corresponding with the polynomial second component of the second code word, and the intermediate variable of the syndrome corresponding with the polynomial second component of the second code word is sent to adder, the intermediate variable of adder to the syndrome corresponding with polynomial the first component of the second code word receiving, the intermediate variable of the syndrome corresponding with the polynomial second component of the second code word carries out Galois Field addition, obtain the intermediate variable of the syndrome corresponding with the second codeword polynome, when adder is calculated the polynomial syndrome of the second code word, the second trigger also can be by last result of calculation (, the syndrome of the first codeword polynome) feed back to adder, adder is done after Galois Field addition by the intermediate variable of the syndrome corresponding with the first codeword polynome with the intermediate variable of the corresponding syndrome of the second codeword polynome, and addition result is stored in the second trigger again, when the first trigger is exported its inner multiplier factor for the second time, the first multiplier also can receive this multiplier factor, and the multiplier factor receiving and the multiplier factor of self are multiplied each other for the second time, the result of the gained that multiplies each other is sent to the second multiplier simultaneously, the second multiplier multiplies each other the multiplier factor receiving and the multiplier factor of self for the second time, the result of the gained that multiplies each other is fed back to the first trigger from the output of the second multiplier, the new multiplier factor of the first trigger using the multiplier factor again receiving as storage inside simultaneously, circulation successively, until the 3rd multiplier and the 4th multiplier no longer receive codeword polynome, also, until the input of the coefficient of codeword polynome is complete, when adder completes after last Galois Field addition, the final accumulation result in the second trigger is the syndrome of codeword polynome.
By the multiplier in the first multiplication unit and the second multiplication unit is set to respectively to a plurality of multipliers, has realized according to the mode of parallel receive and received the polynomial coefficient of code word, and then reached the computational speed that improves codeword polynome syndrome.
Wherein, if the input degree of parallelism of codeword polynome coefficient is set to p, in Fig. 2, the multiplier in the first multiplication unit and the second multiplication unit is p, 2,3 and 4 explanations carry out according to degree of parallelism p the principle that the syndrome of codeword polynome solves by reference to the accompanying drawings, Fig. 3 is according to the structured flowchart of the syndrome solving circuit of the embodiment of the present invention, Fig. 4 is according to the operation principle flow chart of the syndrome solving circuit of the embodiment of the present invention, as shown in Figure 2, Figure 3 and Figure 4, suppose that the codeword polynome receiving is R (x)=[R
0* x
0+ R
1* x
1+ R
2* x
2+ ... + R
n* x
n], available matrix representation is R (x)=[R0R1R2 ... Rn], in Galois Field, element representation is α
i, wherein, concrete i value can be determined according to the error correcting capability of the ECC decoding circuit of this syndrome solving circuit of application.The input of code word in the present invention is according to the mode access to plant of grouping parallel, and establishing degree of parallelism is p, and the codeword polynome coefficient number of each input is p, and syndrome represents with Si, and syndrome and the pass that receives between code word are: Si=R (α
i).By by α
iin substitution R (x), just can try to achieve syndrome, in Fig. 2, the multiplier factor in the first multiplication unit in each multiplier is Galois Field element α
i, realize all with one coefficient correspondence of each node in multiplier, finish with the multiplication of coefficient and be added and obtain the value after p substitution of this group afterwards, if enter code word coefficient is Rm, Rm+1 ... Rp-1, multiplies each other this p coefficient, and will take advantage of α with the upper element in corresponding position
ithe result of calculation of below deposit in d type flip flop 1, enter next time and calculate, the value of for example having calculated for the first time in rear d type flip flop is at first α
pi, that calculated is R
0* α
0+ R
1* α
li+ R
2* α
2i+ ... + R
p-1* α
(p-1) i, will enter second below and take turns computing, next group will be from R
p* α
pistart to calculate, by the results added of calculating at every turn.By that analogy.Obtain the value of the final syndrome having added up.Operation principle specifically as shown in Figure 4, is first that chien search machine (that is, syndrome solving circuit) receives after control signal, and trigger initialization, inputs one group of p codeword polynome coefficient afterwards; Secondly respectively (this p coefficient is multiplied each other with the upper element in corresponding position, respectively by the corresponding input of this p coefficient multiplier 1, multiplier 2 ... multiplier p, and respectively by 1 pair of coefficient receiving of multiplier with multiplier factor multiplies each other, 2 pairs of coefficients that receive of multiplier and multiplier factor multiply each other ... multiplier p multiplies each other to the coefficient receiving and multiplier factor), complete the substitution of element; By multiplier 1, multiplier 2 ... multiplied result in multiplier p is added, and by result and upper one group of addition results cumulative addition in adder 2 after being added, adder 2 is stored to the second trigger by accumulation result; After coefficient input, the result of resulting cumulative addition is exactly the value of the final syndrome that obtains.
Further, the syndrome solving circuit of the embodiment of the present invention also comprises selector, and the first input end of selector is for receiving the element α of Galois Field
0, take advantage of α for the second input of selector and the p in the first multiplication unit
ithe output of multiplier is connected, and the output of selector is connected with the first trigger.Owing to entering the data of the first trigger, there are two kinds, a kind of is the initial value of inputting for the first time, another kind is that syndrome solving circuit completes the value after the intermediate variable of the corresponding syndrome of multinomial that one is p with degree of parallelism, so need to increase selector at the first trigger front end, enter the first trigger to realize the correct data of control.
The embodiment of the present invention also provides a kind of syndrome of codeword polynome to solve processing method, and the syndrome solving circuit that this syndrome solves processing method can be provided by embodiment of the present invention foregoing is carried out, and particularly, comprises the following steps:
By the first multiplication unit, the multiplier factor in the multiplier factor from the first trigger and the first multiplication unit is multiplied each other, and acquired results is sent to the first trigger;
By the second multiplication unit, the coefficient of the first codeword polynome receiving is multiplied by the first multiplier factor receiving, obtain the first Output rusults, and the polynomial coefficient of the second code word receiving is multiplied by the second multiplier factor receiving, obtain the second Output rusults;
By adder, receive the first Output rusults and the second Output rusults, and the first Output rusults and the second Output rusults are added; And
By the second trigger, at the cumulative accumulation result that finishes rear output adder of adder, obtain syndrome.
The syndrome of the codeword polynome of the embodiment of the present invention solves processing method and receives respectively the first codeword polynome and the polynomial coefficient of the second code word by the second input via the second multiplication unit, and the output of the second multiplication unit is connected with adder, realized codeword polynome has been inputted to syndrome solving circuit according to the mode of grouping parallel, and the intermediate variable of the syndrome corresponding with each group codeword polynome solving is added up, and export final accumulation result when cumulative end, and then obtain the polynomial syndrome of original code word; by by output feedback link to the first trigger of the first multiplication unit, only realized and can solve by a set of the first multiplication unit and the first trigger the multiplier factor that obtains each power, by the first input end of the second multiplication unit being connected between the first multiplication unit and the first trigger, realized the second multiplication unit when receiving codeword polynome and calling from its first input end the multiplier factor receiving each time, all can access the multiplier factor of the corresponding power of coefficient of the codeword polynome receiving with its second input, and then realized in to syndrome solution procedure at every turn by the corresponding codeword polynome of multiplier factor substitution of corresponding power time all without increasing the multiplication unit being formed by NOR gate circuit, also be, by by output feedback link to the first trigger of the first multiplication unit, and the first input end of the second multiplication unit is connected between the first multiplication unit and the first trigger, realized and only relied on a set of solving circuit can solve the syndrome of the codeword polynome of different component numbers, solved the larger problem of syndrome solving circuit area of codeword polynome in prior art, and then reached the polynomial syndrome solving circuit of simplification code word, reduce the effect of solving circuit area.
Further, can be according to certain polynomial syndrome of degree of parallelism compute codeword, if degree of parallelism is p, the multiplier in the first multiplication unit is set to p multiplier, the multiplier factor in each multiplier is all the element α in Galois Field
i; Multiplier in the second multiplication unit is also set to p multiplier, with the first multiplication unit, comprise the first multiplier and the second multiplier, the second multiplication unit comprises that the 3rd multiplier and the 4th multiplier are that example illustrates according to the principle of certain polynomial syndrome of degree of parallelism compute codeword, specific as follows:
The first multiplier multiplies each other the multiplier factor in the multiplier factor from the first trigger and the first multiplier, and acquired results is sent to the second multiplier; And
The second multiplier multiplies each other the multiplier factor in the acquired results from the first multiplier and the second multiplier, and acquired results is sent to the first trigger,
The 3rd multiplier is multiplied by the coefficient of the first component of the first codeword polynome the first multiplier factor of the first trigger output, obtain the sub-result of the first output, and the second multiplier factor that the coefficient of polynomial the first component of the second code word is multiplied by the first trigger output, obtain the sub-result of the second output;
The 4th multiplier is multiplied by the coefficient of the second component of the first codeword polynome the first multiplier factor of the first multiplier output, obtain the sub-result of the 3rd output, and the second multiplier factor that the coefficient of the polynomial second component of the second code word is multiplied by the first multiplier output, obtain the sub-result of the 4th output; And
Adder is calculated the first sub-result of output and the sub-result sum of the 3rd output, obtains the first Output rusults, and calculates the sub-result of the second output and the sub-result sum of the 4th output, obtains the second Output rusults.
Adder is carried out Galois Field addition by the first Output rusults and the second Output rusults, and will add up and be stored to the second trigger, adder is cumulative finish after, the accumulation result in the second trigger is the syndrome of codeword polynome.
By receive the polynomial coefficient of code word according to the mode of parallel receive, reached the effect that improves the computational speed of codeword polynome syndrome.
The embodiment of the present invention also provides a kind of ECC coding/decoding method of codeword polynome, below the ECC coding/decoding method of the codeword polynome of the embodiment of the present invention is specifically introduced.
Fig. 5 is according to the flow chart of the ECC coding/decoding method of the embodiment of the present invention, and as shown in Figure 5, the method comprises that following step S502 is to step S504:
S502: the syndrome that solves codeword polynome.Particularly, the syndrome solving circuit of the codeword polynome providing by embodiment of the present invention foregoing or syndrome solve processing method to carry out syndrome and solves, and obtains the syndrome of codeword polynome.
S504: codeword polynome is carried out to ECC error correction according to the syndrome of codeword polynome.
Syndrome solving circuit by the codeword polynome that provides according to embodiment of the present invention foregoing or syndrome solve processing method to carry out syndrome and solves, the area, the raising syndrome that have reached reduction syndrome solving circuit solve the effect of speed, and then have reached the effect that improves the ECC decoding speed of codeword polynome.
In addition, the embodiment of the present invention also provides a kind of ECC decoding circuit of codeword polynome, and this ECC decoding circuit comprises the syndrome solving circuit of any codeword polynome that embodiment of the present invention foregoing provides.
It should be noted that, in the step shown in the flow chart of accompanying drawing, can in the computer system such as one group of computer executable instructions, carry out, and, although there is shown logical order in flow process, but in some cases, can carry out shown or described step with the order being different from herein.
Obviously, those skilled in the art should be understood that, above-mentioned each module of the present invention or each step can realize with general calculation element, they can concentrate on single calculation element, or be distributed on the network that a plurality of calculation elements form, alternatively, they can be realized with the executable program code of calculation element, thereby, they can be stored in storage device and be carried out by calculation element, or they are made into respectively to each integrated circuit modules, or a plurality of modules in them or step are made into single integrated circuit module to be realized.Like this, the present invention is not restricted to any specific hardware and software combination.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (8)
1. a syndrome solving circuit for codeword polynome, is characterized in that, comprising:
The first trigger;
The first multiplication unit, the input of described the first multiplication unit is connected with the output of described the first trigger, the output of described the first multiplication unit is connected with the input of described the first trigger, for the multiplier factor in the multiplier factor from described the first trigger and described the first multiplication unit is multiplied each other, and acquired results is sent to described the first trigger;
The second multiplication unit, the first input end of described the second multiplication unit is connected between described the first multiplication unit and described the first trigger, the second input of described the second multiplication unit is for receiving respectively the first codeword polynome and the polynomial coefficient of the second code word, for the coefficient of described the first codeword polynome is multiplied by the first multiplier factor receiving, obtain the first Output rusults, and the polynomial coefficient of described the second code word is multiplied by the second multiplier factor receiving, obtain the second Output rusults;
Adder, the first input end of described adder is connected with the output of described the second multiplication unit, for receiving described the first Output rusults and described the second Output rusults, and described the first Output rusults and described the second Output rusults is added; And
The second trigger, the input of described the second trigger is connected with the output of described adder, the output of described the second trigger is connected with the second input of described adder, at the cumulative accumulation result that finishes the described adder of rear output of described adder, obtains syndrome.
2. syndrome solving circuit according to claim 1, is characterized in that, described the first multiplication unit comprises the first multiplier and the second multiplier, and described the second multiplication unit comprises the 3rd multiplier and the 4th multiplier, wherein,
The input of described the first multiplier is connected with the output of described the first trigger, and the output of described the first multiplier is connected with the input of described the second multiplier, and the output of described the second multiplier is connected with the input of described the first trigger,
The first input end of described the 3rd multiplier is connected between described the first trigger and described the first multiplier, the second input of described the 3rd multiplier is for receiving respectively the coefficient of the first component and the coefficient of polynomial the first component of described the second code word of described the first codeword polynome, described the 3rd output of multiplier and the first input end of described adder are connected, for the coefficient of the first component of described the first codeword polynome being multiplied by the first multiplier factor of described the first trigger output, obtain the sub-result of the first output, and the second multiplier factor that the coefficient of polynomial the first component of described the second code word is multiplied by described the first trigger output, obtain the sub-result of the second output,
The first input end of described the 4th multiplier is connected between described the first multiplier and described the second multiplier, the second input of described the 4th multiplier is for receiving respectively the coefficient of second component and the coefficient of the polynomial second component of described the second code word of described the first codeword polynome, the output of described the 4th multiplier is connected with the second input of described adder, for the coefficient of the second component of described the first codeword polynome being multiplied by the first multiplier factor of described the first multiplier output, obtain the sub-result of the 3rd output, and the second multiplier factor that the coefficient of the polynomial second component of described the second code word is multiplied by described the first multiplier output, obtain the sub-result of the 4th output,
Wherein, described adder is also for calculating described the first sub-result of output and the sub-result sum of described the 3rd output, obtain described the first Output rusults, and calculate described the second sub-result of output and the sub-result sum of described the 4th output, obtain described the second Output rusults.
3. syndrome solving circuit according to claim 2, is characterized in that, the multiplier factor in described the first multiplier and described the second multiplier is the element α in Galois Field
i.
4. syndrome solving circuit according to claim 1, is characterized in that, described syndrome counting circuit also comprises:
Selector, the first input end of described selector is for receiving the element α of Galois Field
0, the second input of described selector is connected with the output of described the first multiplication unit, and the output of described selector is connected with described the first trigger.
5. an ECC decoding circuit for codeword polynome, is characterized in that, comprises the syndrome solving circuit described in any one in claim 1 to 4.
6. the syndrome of a codeword polynome solves processing method, it is characterized in that, for the syndrome solving circuit described in claim 1 to 4 any one, wherein, described syndrome solving circuit comprises the first trigger, the second trigger, the first multiplication unit, the second multiplication unit and adder, and described syndrome solves processing method and comprises:
By described the first multiplication unit, the multiplier factor in the multiplier factor from described the first trigger and described the first multiplication unit is multiplied each other, and acquired results is sent to described the first trigger;
By described the second multiplication unit, the coefficient of the first codeword polynome receiving is multiplied by the first multiplier factor receiving, obtain the first Output rusults, and the polynomial coefficient of the second code word receiving is multiplied by the second multiplier factor receiving, obtain the second Output rusults;
By described adder, receive described the first Output rusults and described the second Output rusults, and described the first Output rusults and described the second Output rusults are added; And
By described the second trigger, at the cumulative accumulation result that finishes the described adder of rear output of described adder, obtain syndrome.
7. syndrome according to claim 6 solves processing method, it is characterized in that, described the first multiplication unit comprises the first multiplier and the second multiplier, and described the second multiplication unit comprises the 3rd multiplier and the 4th multiplier, wherein,
By described the first multiplication unit, the multiplier factor in the multiplier factor from described the first trigger and described the first multiplication unit is multiplied each other, and acquired results is sent to described the first trigger comprises:
Described the first multiplier multiplies each other the multiplier factor in the multiplier factor from described the first trigger and described the first multiplier, and acquired results is sent to described the second multiplier; And
Described the second multiplier multiplies each other the multiplier factor in the acquired results from described the first multiplier and described the second multiplier, and acquired results is sent to described the first trigger,
By described the second multiplication unit, the coefficient of the first codeword polynome receiving is multiplied by the first multiplier factor receiving, obtain the first Output rusults, and the polynomial coefficient of the second code word receiving is multiplied by the second multiplier factor receiving, obtain the second Output rusults and comprise:
Described the 3rd multiplier is multiplied by the coefficient of the first component of described the first codeword polynome the first multiplier factor of described the first trigger output, obtain the sub-result of the first output, and the second multiplier factor that the coefficient of polynomial the first component of described the second code word is multiplied by described the first trigger output, obtain the sub-result of the second output;
Described the 4th multiplier is multiplied by the coefficient of the second component of described the first codeword polynome the first multiplier factor of described the first multiplier output, obtain the sub-result of the 3rd output, and the second multiplier factor that the coefficient of the polynomial second component of described the second code word is multiplied by described the first multiplier output, obtain the sub-result of the 4th output; And
Described adder is calculated described the first sub-result of output and the sub-result sum of described the 3rd output, obtains described the first Output rusults, and calculates described the second sub-result of output and the sub-result sum of described the 4th output, obtains described the second Output rusults.
8. an ECC coding/decoding method for codeword polynome, is characterized in that, comprising:
Syndrome by the codeword polynome described in claim 6 or 7 solves the syndrome that processing method obtains described codeword polynome; And
According to the syndrome of described codeword polynome, described codeword polynome is carried out to ECC error correction.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1208192A (en) * | 1997-08-13 | 1999-02-17 | 三星电子株式会社 | Circuit for calculating error position polynomial at high speed |
| CN101325706A (en) * | 2007-06-13 | 2008-12-17 | 卓胜微电子（上海）有限公司 | Reed-Solomon decoder with low hardware spending |
| CN102354535A (en) * | 2011-08-04 | 2012-02-15 | 记忆科技(深圳)有限公司 | Logical unit multiplexing system |
| US8332731B1 (en) * | 2009-11-05 | 2012-12-11 | Micron Technology, Inc. | Error-correcting code and process for fast read-error correction |
-
2012
- 2012-08-03 CN CN201210276155.9A patent/CN103580700B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6286123B1 (en) * | 1997-07-13 | 2001-09-04 | Samsung Electronics Co., Ltd. | Circuit for calculating error position polynomial at high speed |
| CN1208192A (en) * | 1997-08-13 | 1999-02-17 | 三星电子株式会社 | Circuit for calculating error position polynomial at high speed |
| CN101325706A (en) * | 2007-06-13 | 2008-12-17 | 卓胜微电子（上海）有限公司 | Reed-Solomon decoder with low hardware spending |
| US8332731B1 (en) * | 2009-11-05 | 2012-12-11 | Micron Technology, Inc. | Error-correcting code and process for fast read-error correction |
| CN102354535A (en) * | 2011-08-04 | 2012-02-15 | 记忆科技(深圳)有限公司 | Logical unit multiplexing system |
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