JPH01121941A - Data buffering device - Google Patents

Abstract

PURPOSE:To check and detect trouble like data drop-out or false data occurrence by taking out a pattern signal to be checked corresponding to the check pattern added to an input signal and comparing this taken-out signal with the check pattern signal. CONSTITUTION:When input data 12 is given, a signal 35 in the low level or the high level is repeatedly generated to form the check pattern signal, and data is stored in memory groups 22-16 in order. An unload signal 40 is inputted to a terminal 41 to take out stored data 12 and the check pattern signal, and they are sent to an output terminal 51. Meanwhile, the check pattern signal is sent as a pattern signal 52 to be checked to a check circuit 54. The circuit 54 checks the signal in the order of the low level, the high level, the low level... of the original check pattern signal. When the signal 52 whose order is different from that of the check pattern signal is inputted from the memory 22, an error signal 55 is outputted from a terminal 56. This operation is repeated, and error is detected when the drop-out or false occurrence of one word occurs in taken- out data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to data transfer control, and more particularly to a data buffer device having a function of detecting errors occurring during data buffering.

[Conventional technology]

Generally, data transfer between a peripheral device and a central processing unit is controlled by a peripheral ill device. In that case, there is a large difference in data transfer speed between the peripheral device and the central processing unit.

Therefore, it is essential to use a data buffer to match the transfer speed.

This data buffer device has FI to simplify the circuit.
The FO (first in, first out) system is often used. A data buffer device employing this FIFO method is configured to load data from an input terminal using a data load signal and sequentially write the data into the memory within the device, while taking out data from an output terminal using a data unload signal. There is.

In such a FIFO system, the data inputted first from the input terminal is sequentially taken out to the outside through the output terminal. In this way, data writing and reading can be controlled very easily, and the circuit size can be reduced.

[Problem that the invention seeks to solve]

However, such conventional data buffer devices have the following drawbacks. That is, if the load signal or unload signal becomes invalid due to a failure of the control circuit, there is a drawback that accidents such as the same data being retrieved twice or data being omitted are likely to occur.

Data errors caused by such accidents could not be detected even by parity check pits added to the data. For this reason, there is a problem in that errors are detected late or not detected at all, resulting in loss of important data.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an error detection device for a data buffer device that can effectively detect failures such as data dropouts and data overflows that could not be detected using conventional checking methods.

[Means for solving problems]

In the present invention, the device is arranged between the peripheral device and the central processing unit,
Peripheral control device that controls data transfer between these devices
A memory group that temporarily stores data from the peripheral devices, a control circuit that controls writing or reading data to these memory groups, and a load signal generated by the peripheral control device to sequentially identify the a check pattern generation circuit which generates a signal and forms a specific check pattern when these signals are written to the memory group together with the data; and an unload signal generated within the peripheral control device. A data buffer device includes a check circuit that reads a checked pattern signal corresponding to the specific check pattern signal written in the memory group together with the data, and compares it with the specific check pattern signal to check for errors. be equipped.

[Effect]

The data buffer error detection device according to the present invention adds a check pattern signal indicating the order of data input to the input data input to the data buffer, and temporarily stores the check pattern signal. A checked pattern signal corresponding to the check pattern signal included in the stored signals is extracted and compared with the check pattern signal. From the results of this comparison, it is possible to effectively check and detect failures such as missing data or overflowing data.

C Example] The present invention will be described in detail below with reference to Examples.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, human input data 12 is input to an input terminal 11 . Here, when the load signal 15 from the data buffer device is input to the load terminal 14, the input data 12 is latched into the first memory 16 of the memory groups 16-22. This load signal 15 is further input to the control circuit 24. When control circuit 24 receives load signal 15, it generates shift strobe signals 25-31 that sequentially shift input data 12 within memory groups 16-22.

For example, the input data 12 stored in the memory 16 is changed by the shift strobe signals 25 to 31 to the memory groups 16 to 31.
22 one after another and stored in the final stage memory 22. Next, the human data 12 that has been manually input is similarly shifted and stored in the memory 21, and is stored in the same manner thereafter.

On the other hand, the pattern generation circuit 34 receives the load signal 15 described above.
Each time ``LOW'' or ``HIGH'' is input manually,
High) j signal 35 is alternately generated. For example, the first human data 12 is input terminal 1
1, it generates a "low" signal 35 and is stored in memory 16 along with human data 12. Similarly, when the next human power data 12 is applied, a "high" signal 35 is generated and stored in the memory 16 along with the human power data 12.

In the same manner, a "low" or "high" signal 35 is generated every time there is input data 12, and a "low" or "high" signal 35 is generated.
The data are sequentially stored in the memory groups 22 to 16 so as to form a pattern 38 consisting of repetitions of the following.

In this way, the input data 12 sequentially stored in the memory groups 16 to 22 and the check pattern signal 38 are formed.
The "low" or "high" signal 35 is taken out by manually applying an unload signal 40 generated within the data buffer device to an unload terminal 41. That is, when this unload signal 40 is input to the control circuit 24 via the unload terminal 41, the control circuit 24 outputs the input data 12 stored in the memory groups 16 to 22 and the "low" or "high" signal 35. Shift strobe signals 43-49 are applied to memory groups 16-22.

As a result, the first human power data 12, that is, the human power data 12 stored in the memory 22, is sent to the output terminal 51. As a result, the human power data 12 is sequentially shifted, and the next input human power data 12 is stored in the memory 22.

On the other hand, the check pattern signal 38 composed of the "low" or "high" signal 35 is the checked pattern signal 5.
2 to the check circuit 54.

In the check circuit 54, the original check pattern signal 38
The pattern signal 52 to be checked is checked in the order of "low", "high", "low", and so on. When a check pattern signal 54 different from the order of the check pattern signals 38 is manually inputted from the memory 22, an error signal 55 is outputted from the error terminal 56. By repeating the above operations, it is possible to detect an error if one word is missing or overflowing in the data taken out from the data buffer device.

In the embodiment described above, the check pattern signal 38 is composed of 1 bit repetition, but if this is changed to 2 bits and the check pattern signal 38 is composed of 4 patterns, up to 4 words can be omitted. Alternatively, if there is a gush, it can be detected as an error in the same way.

It is clear that it is possible to detect errors with a larger number of words than the 35-bit check pattern signal.

〔Effect of the invention〕

As explained above, the data buffer device according to the present invention sequentially adds check signals to the input data input to the data buffer device to form a checked pattern, and when manually retrieving data, the data buffer device forms a checked pattern. By configuring the system to perform sequential comparisons and checks, it is possible to detect data omissions and leaks that could not be checked using conventional parity checks and other checking methods.

This has the effect of allowing you to check. Furthermore, by increasing the number of bits of the check pattern signal, it is possible to detect missing or overflowing data over several words, as well as data out of order.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a data buffer device according to the present invention. 16-22...Memory, 24...Control circuit, 34...Pattern generation circuit, 54...Check circuit. Applicant: NEC Corporation Representative

Claims (1)

[Claims] A peripheral control device that is placed between a peripheral device and a central processing unit and controls data transfer between these devices includes a memory group for temporarily storing data from the peripheral device, and a memory group for temporarily storing data from the peripheral device, and a memory group for temporarily storing data from the peripheral device. A control circuit that controls writing or reading and a load signal generated by the peripheral control device sequentially generate specific signals, and when these signals are written to the memory group together with the data, a specific check pattern is formed. A check pattern generation circuit comprising a check pattern generating circuit and an unload signal generated within the peripheral control device read out a check pattern signal corresponding to the specific check pattern signal written in the memory group together with the data, and 1. A data buffer device comprising: a check circuit that compares the check pattern signal with a check pattern signal to check whether there is an error.