JPH0378055A - Memory trouble detection system for double buffer - Google Patents

Abstract

PURPOSE:To detect memory trouble without using any parity bit by writing test data in the memories of double buffers at the same times, reading the data out at the same time, and matching the data with each other and detecting the trouble. CONSTITUTION:A test data generating means 1 generate all-'1' and all-'0' data in order and a test signal means 2 outputs the input test data to one of the memories 3 and 4 of the double buffers as write data, and its inverted data to the other memory as write data. Then the memories 3 and 4 are read under the control of a memory control part 5 and the data which are read out of both the memories at the same time are inputted to a trouble detecting means 6 and converted into serial data, which are matched, bit by bit to judge that the signals are normal when '0' corresponds to '1' and generate a trouble detection output when not, thereby indicating the current read position as trouble information.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a memory fault detection method for a double buffer memory in which a read operation to one of two buffers is performed alternately during a write operation to the other, and a parity bit is not added to the stored data. The purpose of this paper is to provide a double-buffer memory fault detection method that can detect double-buffer memory faults without using parity bits. A test data generation means that sequentially generates data; a test signal means that outputs input test data as write data to one side of the double buffer; and outputs inverted data as write data to the other; It is configured to include a control unit that simultaneously writes and drives the buffers for writing and then reads them simultaneously, and a failure detection means that generates notification information including the location of the failure when a failure is detected by collating two pieces of data in the double buffer read at the same time. do.

[Industrial Application Field] The present invention provides a memory fault detection method for double buffer memory, in which a read operation to one of two buffers is performed alternately during a write operation to the other, and a parity bit is not added to the stored data. Regarding.

It has been conventional practice to use memory to interchange the time positions of input data or to convert the speed. In that case, in order to continuously store and read data, a double buffer is configured using two memories (dual configuration), and while writing is being done to one memory in a certain period, the other memory is being written to. A technique is known in which reading is performed and the operation is switched to the opposite operation in the next cycle.

Such technology is used in information processing devices, data transmission devices, switching equipment, and the like. Specifically, it is used, for example, in a time switch of a digital exchange, and performs an operation of reading data alternately stored in frame units in a speech memory configured with a double buffer at a designated time position.

Error detection is performed by providing redundancy in data and hardware to prevent data errors from occurring due to failures in the double buffer memory, but this method has disadvantages such as increased cost, so it is necessary to increase performance. A simple method is desired.

[Prior Art] FIG. 6 is a configuration diagram of a conventional example, and FIG. 7 is an explanatory diagram of operation timing and data structure of the conventional example.

In FIG. 6, 60 and 61 are memories MMO and MMI that constitute a double buffer, 62 is a serial/parallel conversion section, 63 is a memory control section, and 64 is a parallel/parallel conversion section.
Represents the serial converter.

To explain the operation, data is serially input to the serial/parallel converter 62, converted into parallel data (predetermined unit 9, for example, byte unit), and is controlled by a write timing signal from the memory controller 63 to be sent to a double buffer memory. Writing is performed to either MMO or MMI. The write address and write control signal are output from the memory control section 63 to the corresponding memory.

Figure 7A shows the memory control timing during normal operation.As shown in Figure 0, one memory (for example, MMO)
While input data is being written in row 9 under the control of the memory control unit 63, the other memory (MM 1
), the memory control unit 63 performs a read control (m<outputs a read signal and a read address), and a read timing signal is supplied to the parallel/serial converter 64, thereby converting the read parallel data into serial data. It is converted into data and output.

The memory control unit 63 controls writing and reading of the double buffer based on control data from a central control unit (not shown), and controls the writing and reading of the two memories MMO and MMI.
Switching is performed every time a predetermined amount of data is input, and when used as a time switch (path memory) of an exchange, it is performed in units of frames. Memory MM like this
O.

Alternate writing and reading to MMI is shown in FIG. 7A.

It is executed continuously at the timing shown in .

In this conventional method, a parity bit is added to each data to detect data errors due to memory failure, and a parity check is performed when the data is read. The data structure is shown in Figure 7B. In the example shown in Figure 0, one piece of data consists of 8 information bits and 1 parity bit (even parity in this case).
It is made up of.

[Problems to be Solved by the Invention] In the conventional method described above, a parity bit is added to the original data and checked to detect data errors due to memory failure in the double buffer.
There is a problem that adding a parity bit increases the memory capacity and also increases the amount of memory occupied by the parity bit. In addition, a circuit for adding parity before writing and a circuit for checking parity when reading are required (multiple circuits are required for write and read data), resulting in a problem of increased path length.

Furthermore, even if parity bits are used, failure detection is performed in units of words (multiple bytes), so it is not possible to detect which one bit in one word is at fault. Further, in the case of parity bits, there is a problem in that if two bits have a fault, it cannot be detected by checking as shown in the lower part of FIG. 7B.

SUMMARY OF THE INVENTION An object of the present invention is to provide a double-buffer memory fault detection method that can detect double-buffer memory faults without using parity bits.

[Means to solve the problem] FIG. 1 is a diagram showing the principle configuration of the present invention.

In FIG. 1, 1 is a test data generation means, 2 is a test signal means, and 3.4 is a memory 0.4 constituting a double buffer. Memory 1.5 represents a memory control unit, and 6 represents a failure detection means.

The present invention writes test data to two double-buffered memories at the same time, then reads data from the two memories, and the written data is all "1" in one.
” and writing all “0” to the other side is performed alternately, and when reading, the data on both sides is collated and one side is written as “
If the other one is "0" in the second bit, it is considered normal, and when the two match, it is determined that a fault has occurred and the location information is notified.

[Operation] The test data generating means 1 generates data signals to be written to the double buffer memories O and I.

The data signal is a signal in which all "1" and all "0" data of a predetermined length are alternately output, and the length is determined depending on the area or capacity of the memory to be tested.

The memory control unit 5 stores memory 0 when performing a test.
Control is performed such that an operation of writing and reading the memory 1 and memory 1 at the same time is performed alternately.

The test signal means 2 receives the test data output from the test data generation means 1, and under the control of the memory section 5 outputs the data input to one memory 0 as it is as write data, and The input data is inverted (logically) and the output data is supplied to the memory 1 as write data.

Under the control of the memory control unit 5, the memory 0. A read operation is performed on the memory 1, and the data read out from both memories at the same time is input to the fault detection means 6, converted into serial data, and 7) correspondence verification is performed. This verification is normal if one is 0 and the other is l” (exclusive OR),
If the signal is any other than that (the two signals are the same), a failure detection output is generated, and the read position (address or bit position) at that time is notified as failure information.

[Example] Fig. 2 is a block diagram of the embodiment, Fig. 3 is a circuit block diagram of the fault data detection section, Fig. 4 is a block diagram of the fault data control section, and Fig. 5 is a block diagram of the fault data control section.
The figure is an explanatory diagram of the operation timing and data structure of the embodiment. In FIG. 2, 20 is a serial/parallel converter, 21 is a test data control unit, and 22 and 23 are memory 0.
(displayed in MMO) and memory 1 (displayed in MMI), 24
25 is a memory control section, 25 is a fault data detection section, 26 is a parallel/serial conversion section, and 27 is a fault data control section.

When performing a test, one frame of serial data containing consecutive 1's (as much as the memory capacity) is input to the serial/parallel converter 20, and the following frame is filled with 0's. These data are converted into parallel signals word by word in the serial/parallel converter 20 and input to the test data controller 21.The test data controller 2 converts the input data into parallel signals on one side. The other input is input to the memory MMO as it is, and the other is inverted and input to the memory MMI.As a result, the memory MMO and MMI
Data with mutually logically opposite bit configurations are written to.

The timing of memory control during testing is shown in Figure 5A.
It is controlled by the memory control unit 24 as shown in FIG. That is, when a test is started, the memory control unit 24 first sequentially supplies a write control signal and an address signal to the memories MMO and MMl, and when writing for one frame is completed, then A read control m signal and an address signal are supplied to the MMO and MMI, and the data stored in both are read out simultaneously. This operation is repeated several times during a test.

The data read from the two memories MMO and MMI are input to the failure data detection section 25. In this fault data detection section 25, the structure of one bit of the read data consisting of a plurality of parallel bits as shown in FIG. 30. Entered at 31.

When a test signal (“H” signal) is input, the selection circuits 30 and 31 output the respective input signals to the T terminal in the figure, and when there is no test signal (“L” signal), the selection circuits 30 and 31 output the respective input signals to the D terminal in the figure. Output to.

During the test, the two signals output from the T terminals of the selection circuits 30 and 31 are input to the exclusive OR circuit 32, and if one of both signals is 1'' and the other is O'', it outputs "l". If both signals are the same (“0”
(both "1" and "1")) A "0" output occurs, indicating that a memory failure has occurred.

When a test is not performed, two data are input to the selection circuit 33, and the read data is selected by the switching signal (switching signal when the memories MMO and MMI are alternately read and driven), and the read data for normal operation is selected. The output signal is output to the next parallel-to-serial converter (FIG. 2, 26) along with other bit information.

When the failure data detection unit 25 detects the occurrence of a failure,
The detection output (output from Fig. 3) is the failure data control unit 2.
Enter 7. i [The configuration of the harmful data control section 27 is shown in FIG.

The fault data control section 27 in FIG. 4 receives and receives a reset signal from the memory control section 24 to reset the counter circuit 271 when starting a read operation in the test mode. After this, from the memory control unit 24, the memory MMO, M
The read address supplied to MI is the counter circuit 27
1 is input and set, and thereafter a clock signal (indicated by CLK) is input for reading each address, so this is counted.

B of FIG. 5 shows a time chart when a failure occurs.

2 shows changes in the state of each bit position (corresponding to each digit) of the counter circuit 271 that counts read addresses in binary format. When a fault detection signal is generated from the fault data detection section 25 (generated corresponding to the bit position where the fault has been detected), the fault monitoring circuit 272 of the fault data control section 27 shown in FIG. When a fault detection signal is input, the address information of the counter circuit 271 at that time is taken in, and is input to the fault address latch circuit 273 together with the fault detection bit position signal and latched. This situation is shown in FIG. 5B.

The address and bit position signals when this fault occurs are output from the fault address latch circuit 273, and the parallel
It is converted into a serial signal by the serial conversion circuit 274 and sent as alarm information to the control side (for example, the controller of an exchange).C0 in FIG. 5 shows the address and bits that are the contents of the alarm information when a fault occurs. Indicates the data format of location information.

As described above, when a fault bit is detected, alarm information is output from the fault data control unit to the control device.

The address and bit position information included in this alarm information are stored in the control device, and are stored in the memory MM in subsequent operations.
It is used as data to control not to use the failed address (and bit position) of O, MMI.

(If the storage operation is performed while avoiding the faulty bit, normal operation can be performed without replacing the entire memory IJMMO and MMI.

[Effects of the Invention] According to the present invention, it is possible to improve the reliability of a memory integrated circuit as the design margin improves. Furthermore, since fault detection is performed without using parity, it is possible to improve the degree of aggregation and the actual utilization rate of internal circuits.

4 is a configuration diagram of the fault data control unit, FIG. 5 is an explanatory diagram of the operation timing and data structure of the embodiment, FIG. 6 is a configuration diagram of the conventional example, and FIG. 7 is the operation timing and data of the conventional example. It is a configuration explanatory diagram.

In Figure 1, l: Test data generation means 2: Test signal means 3.4: Memory 0. memory 1 5: Memory control section 6: Fault detection means

Claims (1)

[Claims] In a memory fault detection method for a double buffer memory in which a read operation to one of two buffers is performed alternately during a write operation to the other, and a parity bit is not added to stored data, the double buffer memory (3, 4
) test data generation means (1) that sequentially generates all "1" and all "0" data during test operation; outputs the input test data as write data to one memory of the double buffer; a test signal means (2) that outputs inverted data as write data to the memory of A double-buffer memory failure detection method, comprising a failure detection means (6) that generates notification information including the location of the failure when a failure is detected by comparing two pieces of data in the buffer.