JPS61172439A - Error detecting device - Google Patents

Abstract

PURPOSE:To detect an error in an odd number bit and two bits by providing an error detection circuit comparing respectively at least check bits 8 bits generated from write data and read data. CONSTITUTION:In using 8 bits for a write data 1, check bit generating circuits 110, 111 generate three parity bits P1-P3 for high-order 4 bits, low-order 4 bits and entire 8 bits. The error detection circuit 3 uses exclusive OR circuits 8a-8c so as to OR exclusively a check bit 15 generated at write with parity check bits P1-P3 and P'1-P'3 corresponding to a check bit 12 generated at read, outputs are ORed by a circuit 30 to obtain an error detection signal 14. In case of a 2-bit error, since at least one of the three exclusive OR circuits 8a-8c goes to logical 1, the 2-bit error is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The invention of No. 9 relates to an error detection device for detecting an error in data when data illegally written to a storage device it is read.

[Conventional technology]

FIG. 1 is a diagram showing a conventional error detection device, (1)
is the data written by the processing device, (2) is the parity bit generator that generates a parity bit from the write data (1), (4th day) the parity bit generator (parity bit 13 generated by 21) is written. Data (1
), (5) is the storage device that stores data (41, (6) is the data that is output from the storage device + 5 when reading), (7) is the data that is read [1G from the parity bit (9) (9) is the parity bit generated by the parity bit generator (7), (81 is the parity bit 131 during writing and the parity bit <91 generated during reading).
This is an error detection circuit that calculates the exclusive OR of .

Next, the operation of this device will be explained. When writing data, the parity bit generator (2) outputs the write data (1)
The parity bit 13) is then generated. Data 141 is the sum of this parity bit +31 and write data (1)
is stored in the storage device (5). On the other hand, at the time of reading, data t out of the data (6) output from the storage device +51
1G is input to a parity bit generator (7) to generate a new parity bit (9). Then, the parity bit 13) generated during writing and the newly generated parity bit,
The parity bit (9) is input to an error detection circuit (8).

If there is an error in an odd number of bits in the write data (1) and read data (1G), the error detection circuit (8) will output '1', so if there is an error in an odd number of bits, it is possible to detect the error. .

In this way, conventional circuits can produce errors in odd-numbered bits, but cannot detect errors in even-numbered bits, so even if such an error occurs, processing continues. Therefore, the disadvantage is that the calculation results of the processing device lack accuracy.
】Ta. □ [Summary of the Invention] The present invention was made to improve the above-mentioned drawbacks, and since the probability of occurrence of errors of 4 bits or more is negligible in a normal system, errors of odd bits and 2 bits can be ignored. This paper proposes an error detection device for storage devices that can detect errors.

[Embodiments of the invention]

This invention will be explained below. In Figure 2 (1
10), (111) is a check bit generation device that generates 3 check bits from input data, and data (lO) successively output from the memory bag @15.
More check bit generator! The 3 check bits newly generated in (111), I[3, are the check bit ■ generated by the check bit generating device I (111) and the check bit generating device I! An error detection circuit detects an error by comparing the check bit (151) generated by (110), and I is an error detection signal output from the error detection circuit 113.

FIG. 8 is a detailed diagram of the check bit generator (110), and the check bit generator ill is also similar.

Further, FIG. 4 shows a detailed circuit of the error detection circuit-[3].

Figure 8 shows the case where data (1) is 3 bits,
The upper 4 of data (1) in parity bit generator (2a)
The parity bit generator (2C) generates check bit P1 for the lower 4 bits of data (1), and the parity bit generator (2b) generates check bit P8 for the lower 4 bits of data (1). A check bit P2 for all bits is generated.

Furthermore, the error detection circuit +13 in FIG.
g and the corresponding parity bit generation value! (110
Exclusive OR circuits (8a) to (8c) that compare the bits P'r'3 generated by Consisting of

The following describes the operation of the device in Figures 2, 8, and 4.
This will be explained using figures. When write data (1) is 3 bits, the check bit generation circuit (110) generates eight parity bits 11 to P3 for the upper 4 bits, lower 4 bits, and all 8 bits of this data (1). The error detection circuit performs exclusive OR of the corresponding parity bits P1-%pH and F'+ from among the check bits generated during writing and the check bits generated during reading. (8c), and the output is logically summed by the circuit - to provide an error detection signal +14). 2
In the case of a bit error, the eight exclusive OR circuits (
Since at least one of 8a) to (8c) becomes 11', a 2-bit error can be detected.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to detect a 2-bit error that could not be detected by a conventional detection circuit using parity bits, and this has the effect of making it possible to manufacture a more reliable memory at a lower cost.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a conventional error detection circuit, FIG. 2 is a diagram showing an error detection circuit according to an embodiment of the present invention, and FIG. 8 is a diagram showing an example of a conventional error detection circuit.
This figure is a diagram showing details of the check bit generation circuit used in FIG. 2, and FIG. 4 is a diagram showing details of the error detection circuit used in FIG. 2. In the figure, (110) and (111) are check bit generation devices, +51 is a storage device, and 113 is an error detection circuit. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] a first check bit generation device that generates at least 3 check bits from data written to the storage device; a second check bit generation device that generates at least 3 check bits from data read from the storage device; an error detection circuit that compares the at least 8 check bits generated by the second check bit generation device with the corresponding 3 check bits generated by the first check bit generation device; An error detection device characterized by: