JPH0534703B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an error detection method used in a storage device of an information processing device, and more specifically to a transfer error detection method during continuous transfer of a plurality of data.

[Background of the invention]

Conventionally, errors caused by failures in the address and timing systems of storage devices using error correction codes such as 1-bit error correction and 2-bit error detection codes have been tested by incorporating address information into the error correction code along with data bits. I was walking along. However, using addresses that are originally unrelated to data as inputs to data-based logic has led to an increase in the number of input/output signals for data-based LSIs, modules, packages, etc. In addition, when multiple data are transferred continuously with one instruction to achieve high-speed transfer, for example, when transferring a specific number of consecutive data starting from a given address, there is a problem that address information is not generated for each data. It was hot.

[Purpose of the invention]

An object of the present invention is to provide a highly reliable error detection method for a storage system that continuously transfers multiple pieces of data, which can detect errors caused by failures in the address and timing systems, and can also detect errors in the transfer order. It's about doing.

[Summary of the invention]

The present invention enables an efficient error detection method by incorporating count information that controls the transfer of multiple data into an error correction code.

Further, the present invention is characterized in that an inverted binary system is used to obtain the counting information. When counting using the inverted binary system, for example, in the case of 3 bits, two consecutive numbers will always differ by one bit, such as 000→001→011→010→110→111→101→100. Therefore, when counting is performed using the inverted binary system, the counting information for consecutive data always differs by one bit. Here, consider a case where the transfer order is shifted by one timing. The (i+1) or (i-1)th count information is input to the error correction code decoding circuit where the i-th count information should be input. However, the i-th and (i
Since the +1)th or (i-1)th count information differs by only 1 bit, the decoding circuit points out a 1-bit error in the count information, or in other words, detects an error in the transfer order.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. The CNT10 changes from “00” → “01” → “11” → based on the timing signal 81 that controls data transfer.
This is a counter that counts "10", and the count value 11 controls the order of reading from the write data stack 60 and the order of writing to the read data stack 70. The CG 20 generates a write check bit 21 from the write data 61 and the count value 11. SG30
is the data 8 read from the memory module 80
1. Generate syndrome 31 from check bit 82 and count value 11. The DET 40 decodes the syndrome 31 and supplies a correction signal 41 to the correction circuit 50 if a correctable error has occurred, and activates a transfer error signal 42 if an error related to transfer control has occurred.

The operation of this embodiment will be explained in more detail assuming that a 1-bit error correction 2-bit error detection code having a parity check matrix shown in FIG. 2 is used. The write data stack 60 sequentially outputs 8-bit data D ₀ , D ₁ , D ₂ , and D ₃ under the control of the counter 10 . For example, D ₀ =
“10000000”, D ₁ = “01000000” D ₂ = “00100000”,
D ₃ = “00010000”. The count value from the counter 10 changes sequentially as T ₀ = “00”, T ₁ = “01”, T ₂ = “11”, T ₃ = “10”, and D ₀ , D ₁ , D ₂ , It is input to the check bit generation circuit 20 together with _D3 . Check bit 21 has C ₀ = “00111”, C ₁ = “10111”, C ₂ = “01011”, C ₃
="10100" is generated sequentially, and the data D ₀ , D ₁ , D ₂ ,
D ₃ is written to memory module 80.
If the reading is performed correctly, the syndrome generation circuit 30 will have (D ₀ , T ₀ , C ₀ ) or (D ₃ , T ₃ ,
C ₃ ) are input sequentially, and the syndromes S ₀ to S ₃
are all “00000”.

Now, due to an error in transfer control or an error in the address/timing system of the memory module,
(D ₀ , C ₀ ) to (D ₀ , C ₀ ), (D ₁ , C ₁ ), (D ₂ , C ₂ )
Suppose that data is read out of synchronization. The syndrome is S ₀ = “00000”, S ₁ = “11100”, S ₂ = “11010”, S ₃
="11100", and the decoding circuit 40 indicates a transfer error.

According to this embodiment, since the information originally used to control data is incorporated into the error correction code, the amount of circuitry for detecting transfer errors and the number of circuit input/output signals are only slightly increased. Furthermore, it is possible to detect a shift in the transfer order.

〔Effect of the invention〕

According to the present invention, since information originally used to control data is incorporated into the error correction code, errors caused by address/timing system failures can be eliminated with a slight increase in the amount of circuitry and the number of circuit input/output signals. can be detected. Further, according to the present invention, any one timing shift in the transfer order can be detected as a transfer error.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a system used in an embodiment of the error detection method of the present invention, and FIG. 2 shows a parity check matrix of an error correction code used in an embodiment of the error detection method of the present invention. It is a diagram. 10...Counter, 20...Check bit generation circuit, 30...Syndrome generation circuit, 40...
... syndrome decoding circuit, 50 ... data correction circuit, 60 ... write data stack, 70 ... read data stack, 80 ... memory module.

Claims (1)

[Scope of Claims] 1. A storage system that continuously transfers a plurality of data, comprising means for counting the transfer order of the plurality of data, and generating a check bit based on the count value from the counting means and written data at the time of writing, and An error detection method comprising means for constructing code words from check bits and write data, and detecting synchronization deviation between code words. 2. The error detection method according to claim 1, characterized in that the counting means counts using an inverted binary system. 3. An error detection method according to claim 1, comprising means for generating a syndrome from the code word and the count value at the time of reading, and means for decoding the syndrome. 4. The error detection method according to claim 3, wherein the counting means is divided into one for writing and one for reading.