JP2008269671A - Semiconductor memory device and its operating method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve efficiency of code configuration by matching the code configuration of a burst error correction code with the number of input/output of PRAM, ReRAM and a solid electrolyte memory. <P>SOLUTION: The semiconductor memory device uses an error correction code which comprises a plurality of symbols, in which each symbol comprises a plurality of bits, and which can correct an error in a symbol unit for error detection and error correction. The semiconductor memory device is provided with a plurality of memory cells including any of a phase transition resistance element, metal oxide resistance element, or solid electrolyte resistance element, and peripheral circuits (3 to 7). The memory cell includes a first data cell (11) storing a part of bits of the data symbols. The peripheral circuits (3 to 7) reads out the part of bits from the first data cell (11), reproduces the data symbol by adding the prescribed dummy bit to the part of bits, and performs error detection and error correction using the reproduced data symbol. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device such as a phase change random access memory (PRAM), a resistance change random access memory (ReRAM), and a solid electrolyte memory, and in particular, when reading data using a reference cell. The present invention relates to a data error correction technique.

  In recent years, research and development of new nonvolatile semiconductor memory devices that store 1-bit information by changing the resistance of a memory element have been actively conducted. For example, a PRAM (Phase change RAM) using a phase change resistance element formed of a chalcogenite alloy or the like as a memory element is an example of such a nonvolatile semiconductor memory device. PRAM utilizes the property that the resistance value of the phase change resistance element changes depending on the heating method (or the cooling method after heating). The heating of the phase change resistance element is most typically performed by generating Joule heat by passing a current through the phase change resistance element. Another example is a ReRAM (Resistive RAM) using a metal oxide resistance element formed of perovskite oxide or the like as a memory element. The ReRAM utilizes the property that the resistance value of a metal oxide resistance element formed of perovskite oxide or the like changes depending on the voltage applied to the metal oxide resistance element or the applied current. Furthermore, research and development is also underway for solid electrolyte memories that use a solid electrolyte resistance element formed of a solid electrolyte such as copper sulfide as a memory element. The solid electrolyte resistance element is an element that utilizes movement of atoms in the solid electrolyte, and the resistance value of the solid electrolyte resistance element changes depending on the polarity of the applied voltage. The solid electrolyte memory uses such a property of the solid electrolyte resistance element.

  The read operation of the storage data stored in these storage elements is common in that it is performed by detecting the resistance value. One of the most typical methods for detecting the resistance value is that a reference cell programmed with predetermined data is provided in the memory cell, and a signal (typically a current signal) obtained from the selected memory cell, This is a method of comparing a signal obtained from a reference cell. For example, a reference cell in which data “0” is programmed and a reference cell in which data “1” is programmed are prepared. The average current value of the current flowing through these reference cells and the current flowing through the memory cell are The read operation is performed by comparing the current value.

  Like many other memory devices, the PRAM, ReRAM, and solid electrolyte memory described above are considered inevitable to encounter memory cell data errors. In the case of PRAM, data writing is performed depending on the heating method, so that it is easily affected by the operating environment, particularly the environmental temperature. For example, when a PRAM optimized at room temperature is operated in an environment of about 100 ° C., it is considered that a memory cell that normally operates at room temperature performs a defective operation. Furthermore, since the same current path is used for the write operation and the read operation, the possibility that the stored data is rewritten by the read operation cannot be denied. On the other hand, in the case of the ReRAM and the solid electrolyte memory, the write operation is complicated because the write operation needs to be changed according to the write data, and the write operation may not be executed normally due to fluctuations in the power supply voltage. . Similarly to the PRAM, since the same current path is used for the write operation and the read operation, the stored data may be rewritten by the read operation. As described above, in the PRAM, ReRAM, and solid electrolyte memory, it is difficult to avoid a soft error caused by using the same current path in the write operation and the read operation. It is unavoidable that reversal occurs with a low probability.

  In order to cope with such a data error, it is desirable to relieve a soft error by an ECC (Error Check and Correction) technique using an error correction code, as in many other memory devices. In a memory device employing ECC, error correction encoding is performed on write data when data is written, and the error correction encoded data is written to the memory array. At the time of data reading, a syndrome is calculated from the data read from the memory array, and when a data error is found, the corrected data is output to the outside. At this time, the data stored in the memory array is also corrected.

  One useful error correction code is a burst error correction code in which one block is composed of a plurality of symbols, each symbol is composed of a plurality of bits, and error correction in symbol units is possible. The Reed-Solomon code and the Fire code are a kind of such a burst error correction code. The usefulness of burst error correction codes in PRAM, ReRAM, and solid electrolyte memory is that it enables error correction when a data error occurs in a reference cell. When a data error occurs in the reference cell, a burst error often occurs in the read data. If a burst error correction code is employed, there is a high possibility that read data can be corrected correctly even if a data error occurs in the reference cell.

One problem in using burst error correction codes for memory array error correction is that the code configuration may not fit the number of inputs and outputs of the PRAM, ReRAM, and solid electrolyte memory. In general, the PRAM, ReRAM, and solid electrolyte memory preferably have ²ⁿ external input / output pins. For example, a typical PRAM external interface includes 16 (= 2 ⁴ ) input / output pins DQ0 to DQ15. However, in the known burst error correction coding method, there may occur a situation in which the code configuration is not suitable for PRAM, ReRAM, and solid electrolyte memory having ²ⁿ external input / output pins. Hereinafter, a Reed-Solomon code will be described as an example.

In the known Reed-Solomon coding, one block is composed of data symbols and parity symbols. A data symbol is a symbol that includes data that is actually used, and a parity symbol is a symbol that is used for error detection and error correction. When one symbol is composed of M bits, the maximum allowable number of data symbols included in one block is 2 ^M −1. For example, when one symbol is composed of 4 bits, one block can be configured to include a maximum of 15 data symbols. A Reed-Solomon code in which the total number of symbols included in one block is J and the number of data symbols is K is referred to as a (J, K) Reed-Solomon code.

  The number of parity symbols included in one block affects the error correction capability. In the Reed-Solomon code, one block needs to include 2t parity symbols in order to enable error correction of t symbols of symbols included in one block.

The fact that the maximum number of data symbols contained in one block is reduced from 2 ^M to 1 is critical in the design of PRAM, ReRAM and solid electrolyte memory. In order to simplify the architecture of the PRAM, ReRAM and solid electrolyte memory, it is preferable to assign each data symbol of one block to each input / output pin. However, in order to reduce the number of external input / output pins to ^{2n, the} number of bits included in one symbol must be increased unnecessarily. That is, in the Reed-Solomon code, for the maximum number of data symbols in the case where one symbol is composed of n bits is less by only one from 2 ^n, a 2 ⁿ pieces of input and output pins of one block 2 ^In order to assign to each of ⁿ data symbols, one symbol needs to be composed of (n + 1) bits. This is undesirable because it reduces the efficiency of the code structure.

  This is especially important for realizing PRAM, ReRAM and solid electrolyte memory with 16 input / output pins. It is clear that the number of bits included in one symbol is a number represented by a power of 2, facilitating address allocation of PRAM, ReRAM and solid electrolyte memory. For example, it is preferable that the number of bits included in one symbol is 4 in order to facilitate address allocation. However, the problem is that when one symbol is composed of 4 bits, the maximum number of data symbols included in one block is 15. When one symbol is composed of 4 bits, the number of data symbols is insufficient by one to realize PRAM, ReRAM and solid electrolyte memory having 16 input / output pins. Therefore, in a general Reed-Solomon encoding method, in order to realize a PRAM, a ReRAM, and a solid electrolyte memory having 16 input / output pins, it is necessary to configure one symbol with 5 bits. This is not preferable because it reduces the efficiency of the code structure and complicates the address assignment.

  From such a background, it is desired to provide a technique for adapting the code configuration of the error correction code to the number of inputs and outputs of the PRAM, ReRAM, and solid electrolyte memory. In particular, it is desired to provide a technique for realizing a PRAM, a ReRAM, and a solid electrolyte memory having 16 input / output pins while one symbol is substantially composed of 4 bits.

  An object of the present invention is to provide a technique for adapting the code configuration of a burst error correction code to the number of inputs and outputs of PRAM, ReRAM and solid electrolyte memory, thereby improving the efficiency of the code configuration.

  In order to achieve the above object, the present invention employs the means described below. In the description of technical matters constituting the means, in order to clarify the correspondence between the description of [Claims] and the description of [Best Mode for Carrying Out the Invention] Number / symbol used in the best mode for doing this is added. However, the added number / symbol should not be used to limit the technical scope of the invention described in [Claims].

  In one aspect, a semiconductor memory device according to the present invention includes a plurality of symbols, each symbol includes a plurality of bits, and an error correction code capable of error correction in symbol units is detected and corrected. This is a semiconductor memory device used for the above. The semiconductor memory device includes a plurality of memory cells each including one of a phase change resistance element, a metal oxide resistance element, and a solid electrolyte resistance element, and a peripheral circuit (3 to 7). The plurality of memory cells include a first data cell (11) that stores some bits of a data symbol of the symbols. Peripheral circuits (3-7) read out the part of the bits from the first data cell (11), regenerate the data symbol by adding a predetermined dummy bit to the part of the bit, and the reproduced Error detection and error correction are performed using data symbols.

  In one embodiment, the memory cell of the semiconductor memory device further includes a second data cell (11) that stores a bit of a parity symbol of the symbols, and the first data cell ( 11) includes a first reference cell (12A) and a second reference cell (12B) that are simultaneously selected. In this case, the second reference cell (12B) stores the remaining bits of the parity symbol and generates a reference signal used for reading data from a data cell different from the first data cell (11). The first reference cell (12A) is used to generate a reference signal used for reading data from the first data cell (11) and the second reference cell (12B). It is preferable.

  In one embodiment, the second reference cell includes a first cell and a second cell that store complementary data. In this case, it is preferable that the predetermined dummy bit is determined so that the remaining bits stored in the first memory cell and the second memory cell are complementary to each other.

  Preferably, the peripheral circuit (3-7) detects a data error in both the data symbol read from the first data cell and the residual bit read from the second reference cell (12B). Then, the data stored in the first reference cell (12A) is corrected. In this case, the peripheral circuits (3 to 7) detect a data error in the data symbol read from the first data cell, and detect a data error in the remaining bit read from the second reference cell. If not, it is preferable to correct the data stored in the first data cell (11). The peripheral circuits (3 to 7) detect a data error in the remaining bits read from the second reference cell, and detect a data error in the data symbol read from the first memory cell. If not, it is preferable to correct the remaining bits stored in the second reference cell.

  In another aspect, the semiconductor memory device according to the present invention includes a plurality of memory cells each including one of a phase change resistance element, a metal oxide resistance element, and a solid electrolyte resistance element, and a peripheral circuit (3-7). It comprises. The plurality of memory cells include a plurality of data cells (11). The peripheral circuit (3-7) generates a data symbol by adding a plurality of data cells (11) and a predetermined dummy bit to the write data, and calculates a parity symbol using the generated data symbol Only the bit corresponding to the write data in the data symbol is written into the first data cell (11) of the plurality of data cells (11).

  In one embodiment, the memory cell of the semiconductor memory device further includes a first reference cell (12A) and a second reference cell (12B) that are selected simultaneously with the first data cell (11) during a read operation. Contains. In this case, the peripheral circuits (3 to 7) write some bits of the parity symbol to the second data cell of the plurality of data cells (11), and write the remaining bits of the parity symbol to the second data cell. In order to write to two reference cells (12B), the first reference cell (12A) generates a reference signal used for reading data from the first data cell (11) and the second reference cell (12B). Used for.

  When the second reference cell (12B) includes a first cell and a second cell that store complementary data, the predetermined dummy bit is stored in the first cell and the second cell. Preferably, the remaining bits are determined to be complementary to each other.

  In still another aspect, the semiconductor memory device according to the present invention includes a plurality of memory cells each including any of a phase change resistance element, a metal oxide resistance element, and a solid electrolyte resistance element. The plurality of memory cells include a first data cell (11) used for storing a bit of a data symbol of the plurality of symbols, and a bit of a parity symbol of the plurality of symbols. A second data cell (11) used for storing; a first reference cell (12A) used for generating a reference signal used for reading data of the first data cell (11); The first data cell (11) includes a second reference cell (12A) used to generate a reference signal used for reading data from another data cell. The second reference cell (12A) is used to store the remaining bits of the parity symbol.

  Preferably, the first reference cell (12A) is used to generate a reference signal used for reading data from the second reference cell as well as the first data cell (11).

  The first data cell (11) preferably stores only some of the bits of the data symbol. In this case, the peripheral circuit (3-7) of the semiconductor memory device reproduces the data symbol by adding a predetermined dummy bit to the part of bits, and the second data cell (11) and the second data cell. It is preferable to read the parity symbol from the two reference cells (12B) and perform error detection and error correction using the reproduced data symbol and the read parity symbol.

  According to the present invention, the code configuration of the burst error correction code can be adapted to the number of inputs and outputs of the semiconductor memory device, thereby improving the efficiency of the code configuration.

  The semiconductor memory device of this embodiment is a nonvolatile memory device that includes a plurality of memory cells each including any of a phase change resistance element, a metal oxide resistance element, and a solid electrolyte resistance element. When a phase change resistance element is used as a memory cell, the semiconductor memory device of this embodiment functions as a PRAM. When a metal oxide resistance element is used as a memory cell, the semiconductor memory device of this embodiment Functions as ReRAM. When a solid electrolyte resistance element is used as the memory cell, the semiconductor memory device of this embodiment functions as a solid electrolyte memory.

  In the semiconductor memory device of this embodiment, data stored in the memory array is encoded using (18, 16) Reed-Solomon code. That is, in the present embodiment, the number of data symbols included in one block is 16, and the number of parity symbols is 2. This means that error correction of one symbol out of 18 symbols included in one block is possible.

As described above, in order to reduce the number of data symbols to 16, the number of bits included in one symbol must be 5 in the known Reed-Solomon encoding method. However, in the present embodiment, by adopting the following code configuration, the incompatibility between the code configuration of the error correction code and the number of inputs and outputs of the semiconductor memory device is eliminated:
(1) 4 bits out of 5 bits constituting each data symbol and parity symbol are stored in a data cell of the memory array.
(2) A predetermined value is used as the remaining 1 bit of each data symbol and is not stored in the data cell.
(3) The remaining 1 bit of each parity symbol is stored in the reference cell.

  As a result, a PRAM, ReRAM, and solid electrolyte memory having 16 inputs / outputs can be realized while the number of bits included in one data symbol is substantially four. Further, since the data symbols are 64 bits in total and the parity symbols are 10 bits in total, it is also possible to realize a PRAM, ReRAM, and solid electrolyte memory having 64 inputs / outputs. Hereinafter, the semiconductor memory device of this embodiment will be described in detail. In the following embodiments, for convenience, a PRAM using a phase change resistance element as a memory cell will be described as an example. However, the ReRAM using the metal oxide resistance element as the memory cell and the solid electrolyte memory using the solid electrolyte resistance element as the memory cell can also have the same operation method and circuit configuration as the following embodiments. is there.

  FIG. 1 is a block diagram showing a configuration of a PRAM 10 according to an embodiment of the present invention. The PRAM 10 includes a plurality of memory arrays in which memory cells configured with magnetoresistive elements are arranged in a matrix.

  There are two types of memory arrays of the PRAM 10, data arrays 1_0 to 1_15 and parity arrays 2_0 and 2_1. In the following description, the data arrays 1_0 to 1_15 are collectively referred to as the data array 1 and the parity arrays 2_0 and 2_1 are described as the parity array 2 when they are not distinguished from each other. Data array 1 is used to store data symbols and parity array 2 is used to store parity symbols. The data arrays 1_0 to 1_15 are associated with data inputs / outputs DQ0 to DQ15 of the PRAM 10, respectively. At the time of data writing, a data symbol is constructed from the write data input to the data input / output DQ0 to DQ15 and stored in the data array 1_0 to 1_15, while a parity symbol is generated from the data symbol and stored in the parity arrays 2_0 and 2_1. Saved.

  Access to the data array 1 and the parity array 2 is performed using peripheral circuits, specifically, a row decoder 3, a column decoder 4, a write circuit 5, a sense amplifier circuit 6, and a controller 7. The row decoder 3 and the column decoder 4 are used for selecting a memory cell to be accessed. The write circuit 5 generates a write current used for writing data to the selected memory cell. The sense amplifier circuit 6 is used for identifying data stored in the memory cell. The controller 7 has a function of controlling the row decoder 3, the column decoder 4, the write circuit 5, and the sense amplifier circuit 6. The controller 7 further has a function of performing various operations for error correction, such as Reed-Solomon coding and error detection.

  FIG. 2 is a block diagram showing details of the configuration of the data array 1_0 and the sense amplifier circuit 6 provided corresponding to the data array 1_0 of the present embodiment. There are two types of memory cells arranged in the data array 1_0: a data cell 11 and a reference cell 12. As shown in FIG. 3, the data cell 11 and the reference cell 12 are arranged at a position where the word line 13 and the bit line 14 intersect. The word line 13 is selected according to the X address, and the bit line 14 is selected according to the Y address.

  Returning to FIG. 2, the data array 1_0 is divided into two areas 15A and 15B. The area 15A is an area used for storing even-numbered Y address data, and the area 15B is an area used for storing odd-numbered Y address data. A row of one memory cell is designated by one X address, whereas a column of four data cells 11 is designated by one Y address. That is, when a set of X address and Y address is designated, four data cells 11 located in the same row are selected. As will be described later, these four data cells 11 are used for storing one data symbol.

In the description of the present embodiment, in the case of 16 data input / output configurations, a lower y address than the Y address may be used to distinguish the columns of the data cells 11. In FIG. 2, a pair of X address and Y address, for example, data Q0 to Q3 of Y address “0” of each data array 1 and each parity array 2 correspond to y addresses “0” to “3”, respectively. The data Q4 to Q7 of the Y address “1” correspond to the y addresses “0” to “3”, respectively. Further, the data Q8 to Q11 of the Y address “2” correspond to the y addresses “0” to “3”, and the data Q12 to Q15 of the Y address “3” are the y addresses “0” to “3”. It corresponds to.

  On the other hand, in the case of 64 data input / output configurations, there is no lower y address, and data Q0 to Q3 of data array 1_0 to 1_15 are input / output as 64-bit data in one cycle. Similarly, data array 1_0 ˜1_15 data Q4 to Q7 are also input / output as 64-bit data in one cycle.

  Two columns of reference cells 12 are provided in each of the areas 15A and 15B. The reference cell provided in the area 15A is hereinafter referred to as a reference cell 12A, and the reference cell 12 provided in the area 15B is referred to as a reference cell 12B. Complementary data is written in the two reference cells 12A located in the same memory cell row (that is, connected to the same word line 13). When data is read from the data cell 11 located in the area 15A, a current is passed through the two reference cells 12A located in the same row as the data cell 11, and a reference signal is generated from these currents. This reference signal is generated so as to have a signal level corresponding to the middle of the signal level corresponding to the data “1” and the signal level corresponding to the data “0”. By comparing the reference signal and a data signal generated when a current flows through the data cell 11, the data of the data cell 11 is determined.

  The two reference cells 12A located in the same memory cell row need only store data complementary to each other, and data “1” and “0” are recorded in any of the two reference cells 12A. Note that it is also good. If the difference between the characteristics of the two reference cells 12A is sufficiently small, data reading is not affected even if data “1” and “0” are recorded in any of the two reference cells 12A. That is, the two reference cells 12A are allowed to take either a state of storing data “1” and “0” and a state of storing data “0” and “1”, respectively.

  Similarly, complementary data is written in two reference cells 12B located in the same memory cell row (that is, connected to the same word line 13). When reading data from the data cell 11 located in the area 15B, two reference cells 12B located in the same row as the data cell 11 are used.

  The sense amplifier circuit 6 includes two 4-bit sense amplifiers 16A and 16B and two 2-bit sense amplifiers 17A and 17B. The 4-bit sense amplifier 16A is used for identifying data stored in the data cell 11 located in the area 15A. Specifically, the 4-bit sense amplifier 16A generates a reference signal from the signal received from the reference cell 12A located in the area 15A, and is stored in the data cell 11 located in the area 15A using the reference signal. Identify the data. Similarly, the 4-bit sense amplifier 16B is used for identifying data stored in the data cell 11 located in the area 15B.

  On the other hand, the 2-bit sense amplifiers 17A and 17B are used for identifying data stored in the reference cells 12A and 12B. As will be described later, unlike the general PRAM, the reference cells 12A and 12B are not simply used for the generation of the reference signal; the reference cells 12A and 12B can generate parity symbols along with the generation of the reference signal. Used for storing some bits. The 2-bit sense amplifier 17A generates a reference signal from the signal received from the reference cell 12B located in the area 15B, and identifies data of the reference cell 12A located in the area 15A using the reference signal. Similarly, the 2-bit sense amplifier 17B generates a reference signal from the signal received from the reference cell 12A located in the area 15A, and identifies the data of the reference cell 12B located in the area 15B using the reference signal.

  In the embodiment, the other data arrays 1_1 to 1_15 and the parity arrays 2_0 and 2_1, and the sense amplifier circuit 6 provided corresponding to them also have the configuration shown in FIG. However, the other data arrays 1_1 to 1_15 and the parity arrays 2_0 and 2_1 are composed of data cells 11 arranged in a matrix and reference cells 12 arranged in two columns, as shown in FIG. It is also possible. In this case, the sense amplifier circuit 6 is composed of a 4-bit sense amplifier. Similar to the data array 1_0, a row of memory cells is selected by one X address, and four columns of memory cells are selected by one Y address. That is, when a set of X address and Y address is designated, four data cells 11 and two reference cells 12 located in the same row are selected. The 4-bit sense amplifier generates a reference signal using signals supplied from the two reference cells 12 located in the row of the selected memory cell, and identifies data in the data cell 11 using the reference signal. .

  Subsequently, data allocation in the present embodiment will be described. In this embodiment, one set of X address and Y address corresponds to one block. That is, when an X address and a Y address are specified at the time of access, access to one block corresponding to the X address and the Y address is performed.

  5A and 5B are conceptual diagrams showing a code configuration of a burst error correction code in the present embodiment. FIG. 5A illustrates the code configuration of a block corresponding to an even-numbered Y address by taking a Y address “0” as an example, and FIG. 5B illustrates the code configuration of a block corresponding to an odd-numbered Y address to a Y-address “1”. Is shown as an example.

  As shown in FIGS. 5A and 5B, each block includes 16 data symbols and two parity symbols. The 16 data symbols are respectively associated with the inputs / outputs DQ0 to DQ15 of the PRAM 10, that is, the data arrays 1_0 to 1_15, respectively. Hereinafter, the data symbols associated with the inputs / outputs DQ0 to DQ15 may be referred to as data symbols DQ0 to DQ15, respectively. Further, the two parity symbols are associated with the parity arrays 2_0 and 2_1, respectively. Hereinafter, the parity symbols associated with the parity arrays 2_0 and 2_1 may be referred to as parity symbols P0 and P1, respectively.

  Data arrays 1_0 to 1_15 are used to store data symbols DQ0 to DQ15, respectively. However, all bits of data symbols DQ0 to DQ15 are not stored in data arrays 1_0 to 1_15. The upper 4 bits of the 5 bits constituting each of data symbols DQ0 to DQ15 are stored in data arrays 1_0 to 1_15, respectively. The remaining lower 1 bits are fixed to a predetermined value and are not actually stored in the data arrays 1_0 to 1_15. The bits of the data symbols DQ0 to DQ15 that are not actually stored in the data arrays 1_0 to 1_15 are hereinafter referred to as dummy bits.

  Similarly, the parity arrays 2_0 and 2_1 are used to store parity symbols P0 and P1, respectively. However, all bits of the parity symbols P0 and P1 are not stored in the parity arrays 2_0 and 2_1. Of the 5 bits constituting the parity symbols P0 and P1, 4 bits are stored in the parity arrays 2_0 and 2_1, respectively. The remaining 1 bit is stored in the reference cells 12A and 12B of the data array 1_0; the remaining 1 bit that is not stored in the parity arrays 2_0 and 2_1 is hereinafter referred to as a remaining bit. More specifically, the remaining bits of the parity symbols P0 and P1 of the block corresponding to an even Y address of an X address are stored in the reference cell 12B located in the row of the memory cell corresponding to the X address of the data array 1_0. Is done. 2 and 5A, the remaining bits stored in the reference cell 12B are referred to as Qref0. On the other hand, the remaining bits of the parity symbols P0 and P1 of the odd-numbered Y address block of a certain X address are stored in the reference cell 12A located in the row of memory cells corresponding to the X address of the data array 1_0. 2 and 5B, the remaining bits stored in the reference cell 12A are referred to as Qref1.

  As described above, two reference cells 12A corresponding to the same X address must have one data “1” and the other data “0”, and 2 corresponding to the same X address. The same applies to the two reference cells 12B. Therefore, substantially one bit of data can be stored in two reference cells 12A (or two reference cells 12B). In this case, it may be considered that the remaining bits of the two parity symbols P0 and P1 cannot be stored.

However, such a problem can be avoided by appropriately determining dummy bits of the data symbols DQ0 to DQ15. Specifically, by setting the odd number of dummy bits of the data symbols DQ0 to DQ15 to “1”, the remaining bits of the two parity symbols P0 and P1 are set to “1” and “0”, respectively. It can be limited to a combination or a combination of “0” and “1”. This is because when the values of the data symbols DQ0 to DQ15 are D _{0 to} D ₁₅ and the values of the parity symbols P0 and P1 are P ₀ and P ₁ respectively, the following equation is established in the Reed-Solomon code: is there:
D ₀ + D ₁ + D ₂ +... + D ₁₅ + P ₀ + P ₁ = 0.
Note that D _{0 to} D ₁₅ and P ₀ , P ₁ are elements of the Galois field GF (2 ⁵ ), and the addition is defined as an operation on the Galois field GF (2 ⁵ ). I want. The above equation means that if the odd number of the least significant bits of the data symbols DQ0 to DQ15 is 1, one of the parity symbols P0 and P1 must be “0” and the other must be “1”. ing. This means that the remaining bits of the two parity symbols P0 and P1 can be stored in two reference cells 12A (or two reference cells 12B) in which one stores data “1” and the other stores data “0”. Yes.

  Hereinafter, a read operation and a write operation corresponding to the code configuration illustrated in FIGS. 9A and 9B will be described.

(Read operation)
Referring to FIG. 10, in the read operation, first, data symbols and parity symbol data of a block corresponding to the selected X address and Y address are read from parity arrays 2_0 and 2_1 (step S01).

  More specifically, when the read operation is started, four data cells 11 to 4 selected by the set of the selected X address and Y address in each of the data arrays 1_0 to 1_15 and the parity arrays 2_0 and 2_1. Bit data is read. Specifically, when the Y address is an even Y address, data is read from the data cell 11 located in the area 15A using the reference signal generated using the reference cell 12A located in the area 15A. In the case of an odd Y address, data is read from the data cell 11 located in the area 15B using a reference signal generated using the reference cell 12B located in the area 15B. Hereinafter, a reference cell used for generating a reference signal used for reading data is referred to as a reference signal generating reference cell.

  Further, the remaining bits of the parity symbols P0 and P1 are read from the reference cell 12 of the data array 1_0. If the designated Y address is an even Y address, 2-bit data is read from the two reference cells 12B corresponding to the designated X address using the reference signal generated using the reference cell 12A. It is. On the other hand, in the case of an odd Y address, 2-bit data is read from the two reference cells 12A corresponding to the designated X address using the reference signal generated using the reference cell 12B. Hereinafter, the reference cell from which the remaining bits of the parity symbols P0 and P1 are read is referred to as a read target reference cell.

  The controller 7 adds 16 predetermined dummy bits to the 4-bit data read from the data arrays 1_0 to 1_15, and reproduces 16 data symbols. Furthermore, the controller 7 adds the remaining bits read from the reference cell to be read to the 4-bit data read from the parity arrays 2_0 and 2_1 to reproduce two parity symbols.

  Subsequently, the controller 7 performs error detection using the reproduced 16 data symbols and 2 parity symbols (step S02).

  If no error is detected (step S03), the controller 7 outputs the read data read from the data arrays 1_0 to 1_15 as it is (step S04), and the read operation is completed.

  On the other hand, if an error is detected, the controller 7 determines whether error correction is possible (step S05). In this embodiment, when an error is detected in one symbol, error correction is possible regardless of the number of bits of the error. If error correction is impossible, the controller 7 outputs an error signal and completes the read operation (step S12).

  If error correction is possible, the controller 7 corrects the read data read from the data arrays 1_0 to 1_15, and outputs the corrected read data (step S06).

  Further, the controller 7 performs an error correction operation on the data arrays 1_0 to 1_15 and the parity arrays 2_0 and 2_1 (steps S07 to S11). One subject of this error correction operation is a data cell 11, a reference signal generation reference cell (a reference cell used to generate a reference signal), and a read target reference cell (a reference from which the remaining bits of the parity symbol are read) Cell) which should be corrected. Even if a data error is detected in the data cell 11 and the read target reference cell, the data actually stored in the data cell 11 and the read target cell are not necessarily in error; the data is stored in the reference signal generation reference cell used for generating the reference signal. Even when there is an error, a data error can be detected in the data cell 11 and the read target reference cell. In the present embodiment, appropriate memory cell data is corrected according to the content of the error pattern detected in error detection.

  Specifically, in this embodiment, when a data error is detected in both the data cell 11 and the read target reference cell, the data in the corresponding reference signal generation reference cell is inverted and corrected. This is because when a data error is detected in both the data cell 11 and the read target reference cell in a situation where the data error rate of the memory cell is sufficiently reduced, a data error of the reference signal generation reference cell occurs. This is because the probability of being the highest is. On the other hand, if a data error is detected only in the data cell 11, the data in the data cell 11 is corrected. If a data error is detected only in the read target reference cell, the data in the read target reference cell is corrected. The

  More specifically, when an error is detected and no error is detected in the read target reference cell (that is, when a data error is detected only in the data cell 11), as shown in FIG. The data in the data cell 11 in which an error is found is inverted, thereby correcting the data in the data cell 11 (step S11).

  On the other hand, when an error is detected in the read target reference cell (step S07) and an error is also detected in the data cell 11 (step S08), as shown in FIG. 11B, the controller 7 It is determined that there is an error in the generated reference cell, and the corresponding reference signal generation reference cell is corrected. The correction of the reference signal generation reference cell is performed by inverting the data of only one of the two reference cells used for generating the reference signal. The state in which the reference signal generation reference cell has an error is a state in which the same data is written in two reference cells (although it is unknown whether the data is “1” or “0”). Thus, it is possible to correct the reference signal generation reference cell by inverting only one data. Ref

  Furthermore, when an error is detected in the reference cell to be read (step S07) and no error is detected in the data cell 11 (step S08), the controller 7 reads the data as shown in FIG. 11C. It is determined that there is an error in the target reference cell, and the read target reference cell in which the data error is detected is corrected.

  According to such a read operation, data written in the data cell 11 and the reference cell 12 can be corrected with high probability.

(Light operation)
Next, the write operation will be described. When a write command is input, the controller 7 creates a parity symbol data pattern corresponding to the write data. It should be noted that all bit information of a data symbol is required to create a parity symbol. In the code examples of FIGS. 5A and 5B, when 64 data input / output configurations are adopted, 64-bit write data is all bit information of one data symbol, so 64-bit write data is used. Parity symbols can be created from Therefore, in this case, the write data is directly written in the data array 1 as the data symbols DQ0 to DQ15 (the upper 4 bits), and the parity array 2 that stores the parity symbols is created by the controller 7 from the write data. The upper 4 bits of the two parity symbols P0 and P1 thus written are written. Further, the remaining bits (least significant bits) of the parity symbols P0 and P1 are written in the reference cell 12 (reference cell 12A or reference cell 12B) of the data array 1_0. As described above, one of the remaining bits of the parity symbols P0 and P1 is “1” and the other is “0”, so that there is only one bit of information, and the pair of reference cells 12 stores one bit. Note that, in the end, the remaining bits of the two parity symbols P0, P1 can be stored in the pair of reference cells 12. In the write operation, even if an error bit exists in the write destination data cell 11 and reference cell 12, it is overwritten, so that a pre-read operation and an error detection operation as described later are not necessary.

  On the other hand, when 16 data input / output configurations are employed, only some of the bits of each data symbol are input from outside as write data. In order to create a parity symbol, as shown in the flowchart of FIG. 8A, all bits of the corresponding data symbol are prefetched (step S21). Next, the controller 7 creates two parity symbols P0 and P1 using the input 16-bit write data and the remaining 48-bit data acquired by prefetching (step S22). Next, 16-bit write data and two parity symbols P0 and P1 are written (step S23). Specifically, 16-bit write data is written to the corresponding data cell 11 of the data array 1, and the upper 4 bits of the two parity symbols P0 and P1 are written to the corresponding data cell 11 of the parity array 2, Further, the remaining bits of the two parity symbols P0 and P1 are written into the corresponding reference cells 12 of the data array 1_0. For example, FIG. 9A is a diagram illustrating a code configuration when data Q0 (corresponding to y = 0 when Y = 0) is input as write data and bits in which a write operation is actually performed. In step S21, all bit information corresponding to the data Q0 to Q3 (y = 0 to 3) is prefetched from the data array 1. In step S22, a parity symbol is created from data Q0 (y = 0) as write data and data Q1 to Q3 (y = 1 to 3) as data originally written in the data array 1. In step S23, the write data D0 is written to the data array 1, the upper 4 bits of the parity symbols P0 and P1 are written to the parity array 2, and the data Qref0 of the remaining bits of the parity symbols P0 and P1 is referred to the data array 1_0. It is written in the cell 12B.

  8A and 9A, the method of writing data limited to data bits corresponding to write data and parity symbols has the merit of reducing current consumption during write operation, but write There is also a problem that even if a soft error exists in the data cell 11 corresponding to a data bit other than data, the soft error cannot be corrected.

  FIG. 8B is a diagram for explaining another write operation for solving such a problem. FIG. 9B shows data Q0 (corresponding to y = 0 of Y = 0) as write data in the other write operation. ) Is a diagram illustrating a code configuration and a bit in which data is actually written. In step S31, all the bit information of the data symbols DQ0 to DQ15 to which the write data Q0 belongs and the corresponding parity symbols P0 and P1 are pre-read from the data array 1 and the parity array 2. It should be noted that the prefetched data includes the data of the reference cell 12 to which the remaining bits of the new parity symbol are written. For example, when the Y address of the write destination is an even address (for example, “0”), the reference cell 12B of the area 15B of the data array 1_0 is the write destination of the remaining bits of the new parity symbol, and this reference cell The 12B data Qref0 is prefetched. On the other hand, when the Y address of the write destination is an odd address (for example, “1”), the reference cell 12A of the area 15A of the data array 1_0 is the write destination of the remaining bits of the new parity symbol, and this reference cell The data Qref1 of 12A is prefetched. Hereinafter, the reference cell 12 to which the remaining bits of the parity symbol are written is referred to as a write target reference cell.

  In the prefetching of the data cell 11 and the write target reference cell of the data array 1_0, the reference cell 12 located in the same row as the write reference cell is used for generating a reference signal. For example, when the Y address of the write destination is an even address (for example, “0”), the reference cell 12A in the area 15A of the data array 1_0 is used for generating a reference signal, and the Y address of the write destination is an odd address ( For example, in the case of “1”), the reference cell 12B in the area 15B of the data array 1_0 is used to generate a reference signal. Hereinafter, the reference cell 12 used for generating the reference signal in the prefetching is referred to as a reference signal generation reference cell.

  Subsequently, the controller 7 performs error detection on the pre-read data symbol and parity symbol (step S32). When there is no error (soft error) in the pre-read data symbol, that is, when it is determined in step S33 that there is no error, the controller 7 acquires the input 16-bit write data and the pre-read. Two parity symbols P0 and P1 are created using the remaining 48-bit data (step S34). Next, 16-bit write data and two parity symbols P0 and P1 are written (step S35). Specifically, 16-bit write data is written to the corresponding data cell 11 of the data array 1, and the upper 4 bits of the two parity symbols P0 and P1 are written to the corresponding data cell 11 of the parity array 2, Further, the remaining bits of the two parity symbols P0 and P1 are written into the write target reference cell 12.

  On the other hand, when a data error is detected in steps S32 and S33, the controller 7 determines whether error correction is possible (step S36). In this embodiment, when an error is detected in one symbol, error correction is possible regardless of the number of bits of the error. If error correction is impossible, the controller 7 outputs an error signal and completes the write operation (step S37).

  When error correction is possible, data writing is performed in an operation sequence that differs depending on the error pattern. More specifically, data writing is performed as follows.

  When there is an error in the data bit corresponding to the write data of the pre-read data symbol or the bit stored in the reference cell to be written (step S38: YES), the case where no error is found and Similarly, creation of parity symbols P0 and P1 (step S34), writing of 16-bit write data, and data of two parity symbols P0 and P1 are performed (step S35). Even if an error is found in the data bit corresponding to the write data of the data symbol or the bit stored in the reference cell to be written, these are overwritten, so no action is required.

  If there is an error in a data bit that does not correspond to the pre-read data symbol write data (step S39: YES), an error-corrected data symbol and a parity symbol are generated (step S40). Specifically, correct data bits are calculated by error correction, and further, error-corrected data symbols DQ0 to DQ15 are generated by combining the data bits corresponding to the write data and the data bits with corrected errors. The Further, parity symbols P0 and P1 are generated from the error-corrected data symbols.

  Subsequently, the error-corrected data symbols DQ0 to DQ15 and the parity symbols P0 and P1 are written into the data array 1 and the parity array 2 (step S41). It should be noted that in the data writing in step S41, not only the data bits corresponding to the write data but also the entire data symbols DQ0 to DQ15 are written as shown in FIG. 9B.

  If none of the above applies, that is, if there is an error in the reference current generation reference cell, after the error-corrected data symbol and parity symbol are generated (step S42), the reference current Correction of the generated reference cell and data writing are performed simultaneously (step S44). The procedure for generating error-corrected data symbols and parity symbols in step S42 is the same as in step S40. Specifically, correct data bits are calculated by error correction, and further, error-corrected data symbols DQ0 to DQ15 are generated by combining the data bits corresponding to the write data and the data bits with corrected errors. The Further, parity symbols P0 and P1 are generated from the error-corrected data symbols.

  It should be noted that, for generating the parity symbols P0 and P1, error-corrected data symbols DQ0 to DQ15 are used instead of the data symbols DQ0 to DQ15 obtained by prefetching. When there is an error in the reference current generation reference cell, the values of the data symbols DQ0 to DQ15 obtained by prefetching may be different from the values written in the data array 1. On the other hand, the error-corrected data symbols DQ0 to DQ15 coincide with the values written in the data array 1. Therefore, it is necessary to generate parity symbols P0 and P1 from the error-corrected data symbols.

  The correction of the reference current generation reference cell in step S44 is performed by inverting one data of the two reference current generation reference cells. In the data write in step S44, 16-bit write data and two parity symbols P0 and P1 are written. In the data writing in step S44, it is not necessary to correct data bits that do not correspond to the written data.

  By performing the write operation according to the above procedure, data can be written while correcting the soft error in the data cell 11 corresponding to the data bits other than the write data.

FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a block diagram showing a configuration of a data array and a sense amplifier circuit of the semiconductor memory device according to the embodiment of the present invention. FIG. 3 is a conceptual diagram showing the configuration of the data array of the semiconductor memory device according to one embodiment of the present invention. FIG. 4 is a block diagram showing another configuration of the data array and the parity array of the semiconductor memory device according to the embodiment of the present invention. FIG. 5A is a diagram showing a code configuration of the semiconductor memory device according to one embodiment of the present invention. FIG. 5B is a diagram showing a code configuration of the semiconductor memory device according to the embodiment of the present invention. FIG. 6 is a timing chart for explaining the read operation of the semiconductor memory device according to the embodiment of the present invention. FIG. 7A is a conceptual diagram illustrating the error correction operation of the semiconductor memory device according to the embodiment of the present invention. FIG. 7B is a conceptual diagram illustrating the error correction operation of the semiconductor memory device according to the embodiment of the present invention. FIG. 7C is a conceptual diagram illustrating the error correction operation of the semiconductor memory device according to the embodiment of the present invention. FIG. 8A is a timing chart illustrating the write operation of the semiconductor memory device according to one embodiment of the present invention. FIG. 8B is a timing chart illustrating a write operation of a semiconductor memory device according to another embodiment of the present invention. FIG. 9A is a diagram illustrating bits for which prefetching is performed and bits for which data writing operation is performed in the write operation of FIG. 8A. FIG. 9B is a diagram illustrating bits for which prefetching is performed and bits for which data writing is performed in the write operation of FIG. 8B.

Explanation of symbols

1, 1_0 to 1_15: Data array 2, 2_0, 2_1: Parity array 3: Row decoder 4: Column decoder 5: Write circuit 6: Sense amplifier circuit 7: Controller 11: Data cell 12, 12A, 12B: Reference cell 13: Word line 14: Bit line 15A, 15B: Area 16A, 16B: 4-bit sense amplifier 17A, 17B: 2-bit sense amplifier

Claims (12)

A semiconductor memory device that uses an error correction code that is composed of a plurality of symbols, each symbol is composed of a plurality of bits, and is capable of error correction in symbol units for error detection and error correction,
A plurality of memory cells each including any of a phase change resistance element, a metal oxide resistance element, or a solid electrolyte resistance element;
Peripheral circuit,
The plurality of memory cells include a first data cell that stores some bits of a data symbol of the symbol;
The peripheral circuit reads the part of the bits from the first data cell, reproduces the data symbol by adding a predetermined dummy bit to the part of the bit, and uses the reproduced data symbol for an error. A semiconductor memory device that performs detection and error correction. The semiconductor memory device according to claim 1,
The plurality of memory cells further includes:
A second data cell storing a bit of a part of a parity symbol of the symbols;
A first reference cell and a second reference cell selected simultaneously with the first data cell during a read operation;
The second reference cell is used to store a remaining bit of the parity symbol and generate a reference signal used for reading data from a data cell different from the first data cell;
The first reference cell is used to generate a reference signal used for reading data from the first data cell and the second reference cell. Semiconductor memory device. The semiconductor memory device according to claim 1,
The second reference cell includes a first cell and a second cell that store complementary data,
The predetermined dummy bit is determined so that the remaining bits stored in the first cell and the second cell are complementary to each other. The semiconductor memory device according to claim 2,
When the peripheral circuit detects a data error in both the data symbol read from the first data cell and the remaining bit read from the second reference cell, the peripheral circuit is stored in the first reference cell. Semiconductor memory device that corrects data that is stored. The semiconductor memory device according to claim 4,
When the peripheral circuit detects a data error in the data symbol read from the first data cell and does not detect a data error in the remaining bits read from the second reference cell, A semiconductor memory device for correcting data stored in one data cell. The semiconductor memory device according to claim 4,
The peripheral circuit detects a data error in the remaining bits read from the second reference cell, and detects no data error in the data symbol read from the first memory cell. A semiconductor memory device that corrects the remaining bits stored in two reference cells. A semiconductor memory device that uses an error correction code that is composed of a plurality of symbols, each symbol is composed of a plurality of bits, and is capable of error correction in symbol units for error detection and error correction,
A plurality of memory cells each including any of a phase change resistance element, a metal oxide resistance element, or a solid electrolyte resistance element;
Peripheral circuit,
The memory cell includes a plurality of data cells;
The peripheral circuit generates a data symbol by adding a predetermined dummy bit to the write data, calculates a parity symbol using the generated data symbol, and a bit corresponding to the write data in the data symbol A semiconductor memory device that writes only the data into the first data cell of the plurality of data cells. The semiconductor memory device according to claim 7,
Furthermore,
A first reference cell and a second reference cell selected simultaneously with the first data cell during a read operation;
The peripheral circuit writes some bits of the parity symbol to a second data cell of the plurality of data cells, and writes the remaining bits of the parity symbol to the second reference cell;
The first reference cell is used to generate a reference signal used for reading data from the first data cell and the second reference cell. Semiconductor memory device. The semiconductor memory device according to claim 8,
The second reference cell includes a first cell and a second cell that store complementary data,
The predetermined dummy bit is determined so that the remaining bits stored in the first cell and the second cell are complementary to each other. A semiconductor memory device that uses an error correction code that is composed of a plurality of symbols, each symbol is composed of a plurality of bits, and is capable of error correction in symbol units for error detection and error correction,
Each comprises a plurality of memory cells including either a phase change resistance element, a metal oxide resistance element, or a solid electrolyte resistance element,
The plurality of memory cells include
A first data cell used to store a bit of a data symbol of the plurality of symbols;
A second data cell used to store bits of a part of a parity symbol of the plurality of symbols;
A first reference cell used to generate a reference signal used for reading data of the first data cell;
A second reference cell used to generate a reference signal used to read data of a data cell different from the first data cell;
The second reference cell is used for storing a remaining bit of the parity symbol. The semiconductor memory device according to claim 10,
The first reference cell is used to generate a reference signal used for reading data from the second reference cell. The semiconductor memory device according to claim 10,
Furthermore,
With peripheral circuits,
In the first data cell, only some bits of the data symbol are stored,
The peripheral circuit reads the part of the bits from the first data cell, reproduces the data symbol by adding a predetermined dummy bit to the part of the bit, and the second data cell and the second data cell. A semiconductor memory device that reads out the parity symbol from two reference cells and performs error detection and error correction using the reproduced data symbol and the read parity symbol.

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