JPS63146520A - Transmission system for reed solomon code - Google Patents

Abstract

PURPOSE:To improve the data transmission efficiency by selecting only an element of parity to have a bit number in compliance with a proper condition in matching with a word length of a code word. CONSTITUTION:A fixed bit value is added to a specific (m-l)-bit in m-bit by a reed Solomon code generating means, and the remaining (l) bits and (l) bits of data are made correspondent to be an element in m-bit of a finite field GF(2<m>) and the generation operation of m-bit parity is applied to generate a reed Solomon code where the length of code word is (LXl+MXm) bit, the result is sent to a transmission line and fed to an error correction arithmetic means therethrough. The error correction arithmetic means treats each element of the inputted reed Solomon code as elements of (L+M)-set of the finite field GF(2<m>) to apply error correction. Thus, the data transmission efficiency is improved by selecting only a bit number of parity to a proper value in matching with the word length of code word in this way.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a Reed-Solomon code transmission system, and more particularly to a Reed-Solomon code transmission system in which a parry is added to data.

Conventional technologyIn data transmission using data communications, PCM recording/playback equipment, digital audio discs, etc., with the recent trend toward higher density and larger capacity, data to be transmitted must be transmitted using a predetermined method to ensure reliability. The generated parity (check vector) is added to create an encoded block, and this block is transmitted (including recording) and received (including playback). From the signal, the code of the data to be transmitted is determined. Error correction methods that correct errors and restore the original correct data have become essential.

Various types of error correction codes have been known that consist of the above-mentioned parity and the data to be transmitted, which is its generating element. ), Reed-Solomon codes are widely used.

The word length of the code word (block) of the Reed-Solomon code is L
+M, of which L pieces of data (data vectors) and M pieces of parity (check vectors) are to be transmitted.
The Solomon code is (L+M.

L) is called a Reed-Solomon code (note that L.

M is a natural number). The coder for this Reed-Solomon code is W = (C, C, ..., C) (1) 0 1
It is represented by a row matrix W of L+H-1. However, C8 to C are data or parity, and there is at least one data and L+H-1 parity.

In addition, in a Reed-Solomon code defined on a finite field (Galois field) GF (2”), the number of elements of the code word (L + M
) is known to require the following condition: 2m-1≧L+M (2).

Problem to be Solved by the Invention If the above vector (element>C-C is each OL+H-1 8 bits), the number of elements of the code word (data parity) L+M is at most 255 (
=28-1). However, with the recent trend toward high-density data storage, the actual data is, for example, 512 bytes, and in order to perform conventional Reed-Solomon encoding on this data,
If the number of bytes in one code word is 255 bytes, the actual data is 512
The byte had to be divided into three or more parts and transmitted using three or more code words, which was inefficient.

For this reason, it is conceivable to make the elements C-C long, for example, 0 and H-1 10 bits, and in this case, the number of elements in one code word, L 0 MG, can be up to 1023 (=
2 ”-1), and with one sign g N, the actual data is 512
Can transmit bytes. However, since data elements are normally handled as 8 bits, in this case, a total of 40 bits (5 data elements) would be transmitted using 4 code word elements (40 bits), making the data handling unreasonable.

The present invention was created in view of the above points, and was developed by Reed-Solomon, who solved the above problems by selecting an appropriate value for the number of parity bits according to the word length of the code word. The purpose is to provide a code transmission method.

Means for Solving the Problems The Reed-Solomon code transmission system of the present invention transmits a total of L pieces of data each having l bits and a total of M pieces of data each having m bits 1-(where m>fl). (L 4M) on a finite field GF(2) whose elements are parity and parity.

A means for generating a Reed-Solomon code of L) and transmitting it to a transmission path, and a means for generating a Reed-Solomon code of L) and transmitting it to a transmission path, and a means for generating a Reed-Solomon code of L) and sending it to a transmission path at a specific (m-el bit position) for l-bit data in the Reed-Solomon code that has come through the transmission path. It consists of a means for performing an error correction operation by handling m bits obtained by adding a fixed bit value as an element of a finite field GF(2).

The operational Reed-Solomon code generation means adds a fixed bit value to a specific (m-e1 bit) among m bits, and associates the remaining l bits with l bits of data to generate a finite field GF.
Perform an m-bit parity generation operation as the m-bit source of (2'), and the length of the code word is (L)l+MXm)
A Reed-Solomon code, which is a bit, is generated and sent to a transmission path, and supplied to an error correction calculation means via this.

The error correction calculation means performs error correction calculation by handling each element of the input Reed-Solomon code as a base of (L+M) finite fields GF(2). Here, each piece of data in the Reed-Solomon code is a bit, but the fixed bit value is added to the specific (m-2) bit position to convert it into m-bit data. Error correction calculation is performed from.

However, when the error location points to data, the error correction calculation means invalidates the error correction calculation only when the pattern of the additional bit part of the specific (m-2) bits is different from the fixed bit pattern; The error correction operation is also invalidated when even one error location points outside the (L+M) elements of the code word.

In this way, data elements of any number of bits can be transmitted using one code word without making data handling unreasonable.

Embodiment FIG. 1 shows a signal format of an embodiment of a Reed-Solomon code transmitted according to the present invention.

In the figure, D-D31 each has 4 bits (=4) of data, making a total of 32 pieces (m=32>), and Po-P3 each has 6 bits (m=6> of parity, making a total of 4 pieces of data). (
M=4), and the code word consists of 36 elements. In reality, as mentioned above, the data is often 8 bits, but for the sake of simplicity, it is assumed to be 4 bits here.

As is clear from equation (1) above, the code n of this Reed-Solomon code is W=(D'', Dl'', D2'', . . . , D31').

PO・Pl・P2・P3)
) defined above. In addition, in the formula 0, * is as described later,
It is generated by adding a fixed l bit, and then indicates that it is 4-bit data excluding the fixed l bit.

Parity Po-P3 of type 0 is check matrix 1-1o
(However, in the above formula, α is the primitive element of the finite field GF (26).) If we assume a matrix of 4 rows and 36 columns as
is■ S=H-W'=(S , S , S , 53)=
(0, O, 0, 0)' (2) It is generated as represented by a column matrix consisting of four zero vectors. In addition, in the formula 0, the king indicates the inverted 1 matrix.

Here, the original definition of the finite field GF (26>) in equation (4) can be defined as (0:0OOOOOO ), (1:000
001), (α:0OO010), (α2:00010
0), (α3:0O1000).

(α, 010000), (α5:100000)4
.

, (α, 000011), (α7:0OO116.

0), ..., (α62:100001).

That is, there are a total of 64 elements in the finite field GF (26).

In this embodiment, in order to generate a Reed-Solomon code defined on the finite field GF (26), each data element (data element) Do-D31 of 4 bits is as shown in FIG. ``0'' is added to the most significant bit of , and ``1'' is added to the least significant bit to make a total of 6 bits (the bit arrangement may also be rearranged). And the above 64 finite fields G
Among the elements of F(26), 16 elements whose most significant bit is rOJ and whose least significant bit is "1" are data D. ~D
31 and the following correspondence.

Data GF (26) original 0000 4+ 000001 0001 H000011 0010++ 000101 0011 → 0001 1 1 0100 → 001001 1111 → 01 1 1 11 Generate with the following correspondence (36.32>Read/
The parity generator polynomial G(x) of the Solomon code is G(x) = (X-1) ・(x-a> ・(x-a2
)・(×−α3) =x 10(1+α+α2+α3)・×3+(α+(x
2+(x4+.5), x2+(α3+α4+α5+α6
)・X+α6=X' +A-X3+B-x2+C-x+
Next to D. Therefore, based on the known parity generation principle,
In this embodiment, parity is generated by the division circuit shown in FIG. Note that in FIG. 3, illustrations of the clock input and clear input are omitted. In Figure 3, 1
is a data input terminal, 21 to 24 are adders each having a 6-bit parallel input terminal and a parallel output terminal, and 3 is a 6-AN
D gate 4 is a division control signal input terminal. The output terminal of AND gate 3 is connected to each input terminal of multipliers 51-54. Further, 6 to 64 are each 6-bit registers, and each output terminal thereof is connected to the input terminal of adders 21 to 24.

Here, each of the adders 22 to 24 has six adders as shown in FIG.
The output signals of the registers 62 to 64 are supplied in parallel to one input terminal of each of the two-man exclusive OR circuits 91 to 96, and the output signals of the multipliers 5 to 53 are supplied in parallel to the other input terminal. The configuration is such that it is supplied to

Multipliers 51, 52, 53 and 54 are circuits for multiplying coefficients A, B, C, and D shown in the equation below, and have a 6-bit parallel input terminal and a 6-bit parallel output terminal, and have exclusive It is constructed by combining OR circuits. - As an example, for the sake of simplicity, to explain a multiplier that multiplies by a coefficient α, 6-bit input data X is expressed as (X6, X5,
X4, X3, X2.

■×1], then the multiplication of this by α is expressed by the following equation.

Therefore, the multiplier that multiplies the coefficient α is as shown in FIG.
It can be configured by one two-manpower exclusive OR circuit 11.

The division circuit shown in Fig. 3, the adder shown in Fig. 4, the
The configuration of each of the riding tightening components shown in the figure is basically the same as the conventional one, but this embodiment differs from the conventional one in that the configuration of the adder 21 shown in FIG. 3 is the configuration shown in FIG. 5. . That is, in FIG. 5, each bit terminal of the 6-bit parallel output terminal from the register 61 is connected to one input terminal of each of the two-man exclusive OR circuits 10 to 106. Further, the 4-bit data from input terminal 1 is supplied to each other input terminal of exclusive OR circuits 10 to 105, but the 4-bit data from input terminal 1 is supplied to each other input terminal of remaining exclusive OR circuits 101 and 1o6. Fixed bit values of "0" and "1" are always applied.

Next, the operation of the division circuit shown in FIG. 3 will be explained with reference to the timing chart shown in FIG.
After data 1 to 64 are cleared, data D-D31 sequentially enters the input terminal 1 as shown in FIG. 7 in synchronization with the clock pulse shown in FIG. This input data is added to adder 2
1 and AND gate 3 to multipliers 51 to 54, respectively, and are each multiplied by the coefficients A-D shown in the equation here.

The output signals of multipliers 51 to 53 are supplied to adders 22 to 24, where they are combined with the output signals of registers 62 to 64, while the output signals of multiplier 54 are supplied to register 64. Each output signal of the adders 24, 23.degree. 22 is supplied to the registers 63, 62.degree. 61 at the previous stage. register 61
The output signal of is supplied to the adder 21, where the input data,
It is added to the evening.

Thereafter, the same operation as above is repeated, and the final data D31 is input to the input terminal 1, and is supplied to the multipliers 51 to 54 through the adder 21 and the AND gate 3, and then the output signals of the multipliers 51 to 53 are stored in the registers 61 to 63 through the adders 22 to 24, and when the output signal of the multiplier 54 has been stored in the register 64, the division control signal from the input terminal 4 becomes low level as shown in FIG. After the AND gate 3 is closed, the values stored in the registers 61 to 64 are sequentially read out to the output terminal 7 in synchronization with the clock as shown in FIG. The values stored in the registers 61 to 64 immediately after the AND gate 3 is closed are the parity P. ~ Corresponds to P3.

The code word length is 15l bits (=4 bits x 32 + 6 bits x 4) consisting of the parity Po-P3 and data Do-D31 generated in this way, and has the format (36,32 ) The Reed-Solomon code is supplied to a predetermined receiving system via a transmission path (for example, after being recorded on a recording medium and then being reproduced).

This receiving system calculates the syndrome from the input Reed-Solomon code, determines the number of errors from this syndrome, calculates the error location if there is an error, and identifies the element with the error at the position indicated by the error location. Correct the elements with errors from the above syndrome to correct values.

FIG. 8 shows a block system diagram of an embodiment of the jindrome output circuit which is the main part of the present invention. In the figure, the Reed-Solomon code inputted to the input terminal 15 is inputted to the data conversion circuit 16 in order for each element in 6-bit parallel fashion.

The data conversion circuit 161 includes two data selectors 21 and 22, as shown in FIG. 9, for example.

In FIG. 9, each element constituting a code word is 6 bits, and the input elements are a5, a4 in order from the most significant bit.
, a3 , a2 , al , and ao , a5 and a. 1 bits are supplied to data selectors 21 and 22, respectively, and the remaining 4 bits a1 to a4 are directly output to the output terminal as output elements b1 to b4.

To the data selector 21, a value of "0" is always applied, and to the data selector 22, a value of "1" is always applied. As a result, the input element is 4
When the input element is 6-bit parity, the fixedly applied "O" and 1 are selected and output as the output bits b5 and 1. When the input element is 6-bit parity, the input bits a5 and a are output bits. b5 and s.

Select and output as is. That is, when the input element is parity, the data conversion circuit 16 passes through and outputs the input 6 bits as is, and when the input element is data, it can be treated as an element of the finite field GF (26). As described above, fixed bit values of "0" and "1" are added to the specific most significant bit and least significant bit positions and output.

The 6-bit signal extracted from the data conversion circuit 16 in this manner is sent to the adder 17o.

171, 172 and 173 in parallel to registers 18o, 181, 182 and 183, respectively.

The output signal of the register 18o is supplied directly (or through a multiplier that multiplies by 1) to the adder 17°, where it is added to the output signal of the data conversion circuit 16, and the output signal of the register 181, 18
2.183 output signals are multiplied by the coefficients α, α, α, and the multiplier 19. 19. 19 through adder 171
゜17,. 173, where the data conversion circuit 1
It is added to the output signal of 6.

Thereafter, the same operation as above is repeated for all elements of the input code word, thereby register 8 . 18
From 1.182 and 183, the syndromes So, S1. S2 and S3 are retrieved.

Next, the error correction operation will be explained. (36°32)
Reed-Solomon codes are capable of error correction up to double errors, but for the sake of simplicity, a case where there is only one error will be described. It is known that when there is no error, the syndromes So to S3 described above are all 0, but when there is one error, the following formula holds true.

Therefore, if equation (9) holds true, the syndrome S at this time. , Sl is known to be given by the well-known syndrome n usage, so from equation (10), i =
=-1 weight g(x(31/S□) + 35(
11) Calculate the error location i expressed by the following formula.

This error location i is the code word W shown in equation (1)
(However, here, from the left of L-1-M-1=35>
The th element (t=o, 1, 2..., 35) is error 2, Ci' = Ci +e, (12
).

Therefore, from equations (10) and (12), c, ' + e,
=c= ' +S =C6(13)+ ++
By performing the operation O+, the correct value of the i-th element C1 can be obtained.

Calculation of location i at this time can be obtained by the circuit shown in FIG. In FIG. 10, the syndromes So and Sl output the exponent part of α,
With reference to logarithm tables 25 and 26 stored in advance in read-only memory (ROM>), logarithm table 26 is
The result obtained is further supplied to the complement circuit 27 and
It is converted to the complement of 3 (=26-1>).

The values obtained by the logarithm table 25 and the complement circuit 27 are supplied to the adder 28 of the modulator 063 and multiplied by 10G, (81/S□) = l0Qa (S
□ / 81). The output of this adder 28 is supplied to an adder 29, where it is added with a constant value "35" and outputted to an output terminal 30 as an error location i shown in equation (11).

This error location 1 enters the input terminal 31 in the circuit system diagram of one embodiment of the error correction calculation circuit which is the essential part of the present invention shown in FIG. 33 input terminals. A constant value "36" is applied to the other input terminal B of the magnitude comparator 32, and outputs a high level signal when i is less than 36 from its output terminal, and a low level signal when i≧36. That is, from the magnitude comparator 32,
An error location check signal indicating whether or not the error location i is within the range of 0 to 35 of the code word consisting of 36 elements shown in FIG. , error location i
Only when is within the range of 0 to 35, this is considered an inter-gate state.

Further, the magnitude comparator 33 has a constant value "31" applied to its other input terminal A, and from its output terminal outputs a low level signal when i≦31 and a high level signal when i>31 to the OR gate 33. and is output to the other duck input terminal of the AND gate 34.Therefore, the magnitude comparator 33 outputs a low level when the code word ①Lar location i points to any of the data D-831; When pointing to any one, a high level discrimination signal is extracted.

The output signal of the AND gate 34 is a two-man power AND gate 38.
is supplied to one input terminal of A correction/rewrite clock is applied from the input terminal 39 to the other input terminal of the AND gate 38, and the clock is outputted to the output terminal 40 via the AND gate 38 only when the output signal of the AND gate 34 is at a high level. Furthermore, it is applied to a write enable terminal of a memory (not shown), for example.

On the other hand, each of the two-man exclusive OR circuits 361 to 366 receives the bit signals of the error elements Q and l at one input terminal, and receives each of the errors e and (syndrome S) at the other input terminal. By the incoming bit signal, (13)
The error correction operation shown in the formula is performed and the error-corrected element C is output. This error corrected element C
1 is written into a memory (not shown) in synchronization with the correction rewrite clock outputted via the output terminal 40.

Here, when the error location i points outside the range of the code word, an error exceeding the encoding capability has occurred, resulting in an erroneous correction, and the error correction operation must be invalidated. Therefore, as described above, when the error location i points outside the range of the code word, the output signal of the magnitude comparator 32 becomes low level and the AND gate 34 is closed, so that the correction rewrite clock is output to the output terminal 40. The error correction operation can be disabled without being detected.

Also, when error location i points to any of data Do to D31, the fixed bit part of error 01 is set to the correct value in advance, so it should be "0".In other words, the added l The bit should be 0 bit.

Therefore, if the value of this added l-bit part is not "0pa", this will result in an erroneous correction, so the error correction operation must be invalidated.

Therefore, in this embodiment, a NOR gate 37 is provided which receives the above-mentioned fixed l bit of the input e.
If at least one of the bit values is not “0”, O
By supplying a low level signal to the AND gate 34 via the R gate 35 to open the gate, the correction rewrite clock is not output to the output terminal 40, thereby invalidating the error correction operation. There is.

However, error location i has parity P.

~P3, the above fixed l
Since the value of the bit does not originally exist, NOR gate 3
The error pattern check signal taken out from 7 is itself invalid. Therefore, in this case, the output signal of the magnitude comparator 33 becomes high level, so the NOR
AND gates 34 and 38 regardless of the output of gate 37.
is forced into an open state, and a correction/rewrite clock is taken out to the output terminal 40.

Note that if there are two error locations, they are sequentially input to the input terminal 31.

Above, l1=4. m=6. m=32. We have explained the example when there is one error in M-4, but m>2゜L+M≦2-
The present invention can be applied to any 2, m, L, or M as long as condition 1 is satisfied.

Further, if M≧4, two-step error correction is possible; if M≧2·t, error correction is possible even if there are t error elements, and error pattern checking and error location checking are possible for each of these errors.

If error correction is detected, it is sufficient to set the error status during normal data playback, and for digital audio applications, it is sufficient to set the error flag and use it to control data interpolation processing, etc. use

In addition, in the present invention, the fixed (m-JJ) bit position added to the data of this bit is not limited to the position shown in FIG. (However, it can be either 0 or 1).

Effects of the Invention As described above, according to the present invention, only the parity element is set to the bit number that satisfies an appropriate condition according to the word length of the code word.
Therefore, for example, when the number of bits of a data element is 8 bits and 512 bytes of actual data is transmitted as a Reed-Solomon code with four parities in the code word, conventionally it is divided into three. Since the data is transmitted using 40 bits (=10 bits x 4), a total of 91 bits of parity (=8 bits x 4 x 3) is required, but in the present invention, by setting the parity to 10 pits, only 40 bits (=10 bits x 4) are required. It has the advantage of being able to improve transmission efficiency and also being able to transmit data without making data handling unreasonable.

A diagram showing a signal format of an embodiment of the Lomon code, FIG. 2 is an explanatory diagram of an embodiment of the correspondence between data transmitted in the present invention and fixed bits to be added, and FIG. 3 is a diagram showing a signal format of an embodiment of the Lomon code. A block system diagram of an embodiment of a division circuit for generating a Reed-Solomon code, FIGS. 4 to 6 are circuit diagrams of each part of the block system shown in FIG. 3, and FIG. 7 is a block diagram of the block system shown in FIG. 3. A time chart for explaining the operation of the system, FIG. 8 is a block system diagram showing one embodiment of the syndrome calculation circuit of the receiving system according to the present invention, and FIG. 9 shows an example of the main part of the block system shown in FIG. 8. Configuration diagram, 10th
The figure is a block system diagram showing an example of an error location calculation circuit, and FIG. 11 is a circuit system diagram showing an embodiment of the receiving system error correction calculation circuit in the present invention.

DO””D31...Data, Po-P3...Parity, 1...Data input terminal, 21-24...Clinching device, 51-54.191-193...Ranking device, 61 ~6
4゜180-183...Register, 7...Parity output terminal, 16...Data conversion circuit, 21.22...
・Data selector, 31...Error location input terminal, 32.33...Magnitude comparator,
40... Correction and rewriting clock output terminal.

Patent applicant: Victor Japan Co., Ltd. Figure 4 to7JT-7 Drawing 9 Figure 1O

Claims (2)

[Claims] (1) Add a fixed bit value to specific (ml) bits among m bits (where m>l) for a total of L data of l bits each, and add a fixed bit value to the remaining l bits and data. Perform a parity generation operation of m bits as an element of m bits of the finite field GF(2^m) by associating it with l bits, and
A finite field GF (2
^m) means for generating the above (L+M,L) Reed-Solomon code and sending it out to the transmission path;
For bit data, there is an error in performing an error correction operation by treating the m bits obtained by adding the fixed bit value to the specific (ml) bit position as an element of the finite field GF(2^m). 1. A Reed-Solomon code transmission system comprising a correction calculation means. (2) When the error location points to a data element in the code word, the error correction calculation means
ml) The error correction operation is invalidated only when the pattern of the additional bit part of the bits is different from the bit pattern fixed in the Reed-Solomon code generation means, and even one error location points outside the element of the code word. 2. The Reed-Solomon code transmission system according to claim 1, further comprising means for invalidating the error correction operation even when the error correction operation is performed.