TWI808098B - Device for supporting error correction code and test method thereof - Google Patents

Abstract

A device for supporting a test mode for memory testing according to an example embodiment of the inventive concepts may include a memory configured to receive and store writing data and output reading data from the stored writing data; an error correction code (ECC) engine configured to generate the writing data by encoding input data and to generate output data by correcting error bits of N bits or less included in receiving data when N is a positive integer; and an error insertion circuit configured to provide the reading data to the ECC engine as the receiving data in a normal mode and to provide data obtained by inverting at least one bit of less than N bits of the reading data to the ECC engine as the receiving data in the test mode.

Description

Device for supporting error correction code and testing method thereof

The inventive concepts are related to devices for supporting error correction codes, and more particularly to devices for supporting error correction codes and/or testing methods thereof.

An error correction code (ECC) system can be used to correct errors in data that has passed through a noisy channel. For example, an error-correcting code system can be used to correct errors in data received over a communication channel, or in data read from memory. According to an error-correcting code system, codewords can be generated that add redundancy to original data, and the original data can be restored by correcting errors that occur in data that have passed through a noisy channel. An error correcting code system can have a correctable error count, and the larger the correctable error count, the more resources are available to implement the error correcting code system, and the redundancy added to the error correcting code can also increase. Therefore, the number of errors that can occur in a noisy channel can be limited to the range of the number of errors that can be corrected by a given error correction code system. For example, if the noisy channel is a memory in an ECC system, it may be necessary to verify that the number of errors that may occur in the memory is within the range of the number of errors that can be corrected by a given ECC system.

The inventive concept provides an apparatus for supporting error correction codes (ECC), and more specifically, an apparatus for supporting error correction codes to easily determine whether a noisy channel has a range of the number of errors correctable by an error correction code system and/or a testing method thereof.

According to an exemplary embodiment, an apparatus supporting a test mode for a memory test may include: a memory configured to receive and store write data and output read data from the stored write data; an error correction code (ECC) engine configured to generate the write data by encoding input data and generate output data by correcting error bits of N bits or less included in the received data, where N is a positive integer; and an error insertion circuit configured to provide the read data to the An error correction code engine serves as the received data, and data obtained by inverting at least one bit less than N bits of the read data is provided to the error correction code engine as the received data in the test mode.

According to an exemplary embodiment, an apparatus supporting a test mode for a memory test may include: a memory configured to receive and store write data and output read data from the stored write data; an error correction code (ECC) engine configured to generate encoded data by encoding input data and generate output data by correcting error bits of N bits or less included in the read data, where N is a positive integer; and an error insertion circuit configured to provide the encoded data in a normal mode. to the memory as the write data, and providing data obtained by inverting at least one bit less than N bits of the encoded data to the memory in the test mode as the write data.

According to an exemplary embodiment, a method of testing a device including an error correction code (ECC) engine and a memory configured to correct error bits of N bits or less (wherein N is a positive integer) may include: generating write data by encoding input data by the error correction code engine; writing the write data into the memory, reading the write data, and outputting the read data; and generating output data by correcting an error of the read data by the error correction code engine, wherein the writing the write data data and said outputting said read data includes inverting at least one bit less than N bits of at least one of said write data and said read data.

FIG. 1 is a block diagram of an apparatus 10 for supporting error correction code (ECC) according to an exemplary embodiment of the inventive concept. In more detail, FIG. 1 shows device 10 including memory 300, which is a noisy channel in an ECC system. As shown in FIG. 1 , the device 10 may include an error correction code engine 100 , an error insertion circuit 200 and/or a memory 300 .

The device 10 may be any device 10 comprising a memory 300 for storing input data D_IN and using the stored data as output data D_OUT. In some example embodiments, device 10 may be, but is not limited to, a system-on-chip (SoC), such as an application processor (AP). In some exemplary embodiments, the device 10 may be, but not limited to, a semiconductor memory device for storing input data D_IN and outputting output data D_OUT according to external commands, such as dynamic random access memory (DRAM), flash memory, and the like. In some exemplary embodiments, the device 10 may be, but not limited to, a memory system for storing the input data D_IN and outputting the output data D_OUT in response to a host request, such as a solid state drive (SSD), a memory card, and the like.

The ECC engine 100 can generate encoded data D_ENC by encoding input data D_IN, and can generate output data D_OUT by decoding received data D_RX. The memory 300 in the device 10 may be a noisy channel. For example, the reason for the noise may be but not limited to: the memory cell storing data in the memory 300 is defective, and/or the movement path of the write data D_WR set in the memory 300 or the movement path of the read data D_RD output from the memory 300 is defective. The device 10 may include an error correction code engine 100 , and the error correction code engine 100 may generate encoded data D_ENC by adding redundancy to input data D_IN to be stored in the memory 300 , and may generate output data D_OUT by correcting errors based on redundancy in received data D_RX received from the memory 300 . In some exemplary embodiments, the encoded data D_ENC may be provided to the memory 300 in units of codewords, the codewords including a part of the input data D_IN (or data generated from the input data D_IN) and redundancy.

Error correcting code engine 100 may perform encoding and decoding in various ways. For example, the ECC engine 100 can perform encoding and decoding based on but not limited to ECC codes (such as AN codes, BCH codes, Hamming codes, Polar codes, Turbo codes, etc.). In some exemplary embodiments, the ECC engine 100 may include a processor and a memory for storing instructions executed by the processor, or in some exemplary embodiments may include a logic circuit designed by logic synthesis.

The error correcting code engine 100 may have a number of correctable errors. For example, when the ECC engine 100 is designed according to the 2-bit correction type ECC system, the ECC engine 100 can detect and correct errors of less than or equal to 2 bits in the received data D_RX, for example, 1-bit errors and 2-bit errors. In some exemplary embodiments, the ECC engine 100 may detect that the number of errors in the received data D_RX exceeds the number of errors that the ECC engine 100 can correct, or may generate a signal indicating that error correction cannot be performed.

As the number of errors correctable by the ECC engine 100 increases, the redundancy added to the input data D_IN to generate the encoded data D_ENC may increase, and the storage capacity of the memory 300 for storing the input data D_IN may decrease. Furthermore, as the number of errors correctable by the ECC engine 100 increases, the resources (such as area, power, and/or time) consumed by the ECC engine 100 may also increase. Therefore, the ECC engine 100 can be designed with a correctable error amount determined based on the noisy channel (ie, the bit error rate (BER) occurring in the memory 300 ). For example, when the expected bit error rate of the memory 300 is 0.2 and the data unit processed by the ECC engine 100 is a 10-bit data unit, the number of errors correctable by the ECC engine 100 can be designed to be 2 bits or more. When the error correction code engine 100 has an N-bit correctable error number (N>0), the error correction code system can be called an N-bit correction type error correction code system, and the error correction code engine 100 can be called an N-bit correction type error correction code engine 100.

The error insertion circuit 200 can selectively insert errors between the ECC engine 100 and the memory 300 according to the mode signal C_MODE. As shown in FIG. 1 , the error insertion circuit 200 can receive the encoded data D_ENC from the ECC engine 100 and provide the write data D_WR to the memory 300 . The error insertion circuit 200 can also receive the read data D_RD from the memory 300 and provide the received data D_RX to the ECC engine 100 . The mode signal C_MODE can indicate the mode of the device 10, and the device 10 can operate in the normal mode and the test mode according to the mode signal C_MODE. The error insertion circuit 200 may include a processor and a memory for storing instructions executed by the processor, or may include a logic circuit designed by logic synthesis in some example embodiments.

The error insertion circuit 200 may include at least one bit error circuit BE. The bit error circuit BE can receive an input signal IN indicating a value of a bit, and can output an output signal OUT indicating a value of a bit. As shown in FIG. 1, the bit error circuit BE may include an inverter INV and a switch SW, and the output signal OUT may be the same as the input signal IN or may be the same as a signal obtained by inverting the input signal IN. In some exemplary embodiments, the switch SW of the bit error circuit BE may be controlled based on the mode signal C_MODE input to the error insertion circuit 200 . For example, when the mode signal C_MODE indicates the normal mode, the switch SW can be controlled to make the output signal OUT coincide with the input signal IN. For example, when the mode signal C_MODE indicates the test mode, the switch SW can be controlled to make the output signal OUT consistent with the signal obtained by inverting the input signal IN. When the output signal OUT consistent with the input signal IN is output, it may indicate that the bit error circuit BE is disabled, and when the output signal OUT obtained by inverting the input signal IN is output, it may indicate that the bit error circuit BE is enabled.

In the test mode, the error insertion circuit 200 may use the bit error circuit BE to insert errors into the data received by the error insertion circuit 200 . In some exemplary embodiments, the error insertion circuit 200 may generate the write data D_WR by inserting at least one bit error into the encoded data D_ENC provided by the error correction code engine 100 in response to the mode signal C_MODE indicating a test mode, as described later below with reference to FIG. 2A . In some exemplary embodiments, in response to the mode signal C_MODE indicating the test mode, the error insertion circuit 200 may also generate the received data D_RX by inserting at least one bit error into the read data D_RD provided from the memory 300 , as described later with reference to FIG. 2B . Furthermore, in some exemplary embodiments, the error insertion circuit 200 may insert at least one bit error into the encoded data D_ENC and the read data D_RD respectively in response to the mode signal C_MODE indicating the test mode.

Thus, in the test mode, the error insertion circuit 200 can insert at least one bit error, and thus can verify whether the memory 300 is acceptable or defective. Defects that lead to memory 300 errors may include not only initial defects that occur during the manufacturing process of memory 300 , but also defects that occur later during the cycle of shipping and/or using memory 300 or device 10 including memory 300 . Therefore, during the manufacturing process of the memory 300 or the device 10 , whether the memory 300 has a specific error margin can be verified according to the number of errors correctable by the ECC engine 100 . For example, when the ECC engine 100 corresponds to a 3-bit ECC system, the memory 300 can be manufactured with a 1-bit error tolerance. Therefore, even if a 1-bit error occurs due to a defect of the memory 300, the memory 300 can still be used normally. Therefore, during the manufacturing process of memory 300 or device 10, memory 300 may be tested to ship only memory 300 with 2-bit errors or less, ie, memory 300 with 1-bit error tolerance. That is, the memory 300 or the device 10 can be tested during the manufacturing process so that errors can be corrected by the 3-bit error correction code engine 100, so that even a 1-bit error will not cause problems with the device 10 when the user uses the device 10.

The error insertion circuit 200 can artificially reduce the number of errors of the ECC system correctable by the ECC engine 100 by inserting the number of errors corresponding to the error tolerance of the memory 300 . For example, when the device 10 includes a 3-bit correction type ECC engine 100 and the error insertion circuit 200 inserts 1-bit errors, then the memory 300 can be considered to always contain 1-bit errors, and thus the device 10 can correspond to a 2-bit ECC system. In addition, in the test mode, the error insertion circuit 200 can use a bit error circuit BE (as shown in FIG. 1 ) with a simple structure to insert errors between the error correction code engine 100 and the memory 300 . Whether the memory 300 or the device 10 is acceptable or faulty can be determined according to whether the error correction code engine 100 has successfully performed error correction. For example, when the memory 300 is manufactured to be 1-bit error tolerant, the error insertion circuit 200 may test the memory 300 or the device 10 in the test mode by inserting 1-bit errors and determining whether the error correction code engine 100 successfully corrects the error. Therefore, the memory 300 can be easily verified in the device 10 including the memory 300 and supporting the error correction code, and thus the productivity of the device 10 can be improved. Although FIG. 1 shows an example of memory 300 as a noisy channel, it should be appreciated that an error correction code system that provides additional tolerance to the number of errors predictable by an otherwise noisy channel (e.g., a communication channel) can be readily verified according to example embodiments of inventive concepts.

The memory 300 can receive and store the write data D_WR and can output the read data D_RD from the stored write data D_WR. The memory 300 may include a plurality of memory cells for storing data. In some exemplary embodiments, the memory 300 may include non-volatile memory (for example, electrically erasable programmable read-only memory (EEPROM), flash memory, phase change random access memory (phase change random access memory, PRAM), resistive random access memory (resistance random access memory) memory, RRAM), nano floating gate memory (nano floating gate memory, NFGM), polymer random access memory (polymer random access memory, PoRAM), magnetic random access memory (magnetic random access memory, MRAM) or ferroelectric random access memory (ferroelectric random access memory, FRAM)). In some exemplary embodiments, the memory 300 may include a volatile memory (for example, DRAM, SRAM, mobile DRAM, double data rate synchronous DRAM (DDR SDRAM), low power double data rate (low power double data rate, LPDDR) synchronous SRAM, graphic double data rate (graphic do uble data rate (GDDR) synchronous static random access memory or Rambus dynamic random access memory (rambus RDRAM)).

2A and 2B are block diagrams illustrating an example of device 10 shown in FIG. 1, according to an example embodiment of the inventive concept. As described above with reference to FIG. 1 , the device 10 a of FIG. 2A and the device 10 b of FIG. 2B can respectively support the normal mode and the test mode according to the mode signal C_MODE provided from the outside. Hereinafter, in FIGS. 2A and 2B , the same reference numerals as in FIG. 1 designate the same elements, and therefore, detailed description thereof will not be given herein.

Referring to FIG. 2A, the device 10a may include an error correction code engine 100a, an error insertion circuit 200a, and a memory 300a. The error insertion circuit 200a may provide the encoded data D_ENC provided from the error correction code engine 100a in the normal mode to the memory 300a as the write data D_WR, and/or may provide the write data D_WR generated by inserting at least one bit error into the encoded data D_ENC to the memory 300a. The ECC engine 100a can receive the read data D_RD output from the memory 300a, and thus the read data D_RD and the received data D_RX of FIG. 1 can be consistent with each other in the test mode.

In the test mode, the input data D_IN can be stored in the memory 300a, and then the output data D_OUT can be generated from the read data D_RD output from the memory 300a. For example, after the operation of sequentially storing the same input data D_IN in the entire memory 300a is performed, the output data D_OUT can be generated from the read data D_RD sequentially output from the entire memory 300a. In some exemplary embodiments, the input data D_IN may be compared with the output data D_OUT generated by the ECC engine 100a, and when the input data D_IN and the output data D_OUT are inconsistent with each other, it may be determined that the memory 300a is defective. In some exemplary embodiments, when the error correction code engine 100a cannot correct errors in the read data D_RD (that is, the errors in the read data D_RD exceed the number of errors correctable by the error correction code engine 100a), the error correction code engine 100a may output a signal indicating this situation. In addition, it can be determined whether the memory 300a is defective according to the signal output from the ECC engine 100a.

The error insertion circuit 200a can change the position of at least one bit error inserted in the test mode. For example, the error insertion circuit 200a may write the write data D_WR generated by inserting at least one bit error into the encoded data D_ENC into a specific area of the memory 300a, and may output the read data D_RD by reading the data stored in the specific area of the memory 300a. Next, the error insertion circuit 200a may write the write data D_WR including at least one bit error in a location different from the previous location of the same encoded data D_ENC in the same area as the previous area of the previous memory 300a, and may read data stored in the same area as the previous area of the memory 300a, thereby outputting the read data D_RD. When the actual bit errors caused by the memory 300a appear in the bit errors inserted by the error insertion circuit 200a, the bit errors inserted by the error insertion circuit 200a cannot be used as the error tolerance of the memory 300a. Therefore, the operation of writing the generated write data D_WR and outputting the read data D_RD can be repeated while changing the bit error insertion position of the same area and the same encoded data D_ENC. Examples of making changes to the positions of bit errors inserted by the error insertion circuit 200b will be explained later below with reference to FIGS. 3A and 3B and FIG. 4 .

Referring to FIG. 2B, the device 10b may include an error correction code engine 100b, an error insertion circuit 200b, and a memory 300b. The error insertion circuit 200b may provide the read data D_RD provided from the memory 300b in the normal mode to the error correction code engine 100b as the reception data D_RX, and/or may provide the reception data D_RX generated by inserting at least one bit error into the read data D_RD to the error correction code engine 100b in the test mode. The memory 300b can receive the write data D_WR output from the ECC engine 100b. According to the example of FIG. 2B , the encoded data D_ENC and the written data D_WR of FIG. 1 may be consistent with each other in the test mode.

As described above with reference to FIG. 2B , the error insertion circuit 200b can change the position of at least one bit error inserted in the test mode. For example, the error insertion circuit 200b may provide the received data D_RX generated by inserting at least one bit error into the read data D_RD output by reading the area written into the write data D_WR to the ECC engine 100b. Thereafter, the error insertion circuit 200b may provide the error correction code engine 100b with the received data D_RX including at least one bit error inserted into the read data D_RD output by reading the same area as before at a position different from the previous position. In the device 10 a of FIG. 2A , the read data D_RD can be output multiple times by writing the write data D_WR to the same area multiple times according to the bit error position and reading the written data multiple times. However, in the device 10b of FIG. 2B, the read data D_RD may be output multiple times by writing the write data D_WR to the same area once and reading the write data multiple times. In addition, as will be explained later with reference to FIG. 6B , in the device 10 b of FIG. 2B , the read operation can be performed once on the same area of the memory 300 b.

Hereinafter, an exemplary embodiment of the inventive concept will be explained mainly with reference to the following example: the error insertion circuit 200a stores the write data D_WR generated by inserting bit errors into the encoded data D_ENC in the memory 300a in the test mode, but is not limited thereto. Exemplary embodiments of the inventive concept may also be applied to a device including all of the device 10 b of FIG. 2B and the error insertion circuit 200 a and the error insertion circuit 200 b of FIGS. 2A and 2B .

3A and 3B are block diagrams illustrating an example of the error insertion circuit 200 shown in FIG. 1, according to an example embodiment of the inventive concept. In more detail, FIGS. 3A and 3B illustrate an example of the error insertion circuit 200a of FIG. 2A. As mentioned above with reference to FIG. 2A , in the test mode, the error insertion circuit 200 a ′ of FIG. 3A and the error insertion circuit 200 a ″ of FIG. 3B can insert at least one bit error into the n-bit encoded data D_ENC to generate n-bit written data D_WR (n>0). In the following, FIG. 3A and FIG. 3B will be described with reference to FIG. 2A , and no further description will be given here.

Referring to FIG. 3A , the error insertion circuit 200 a ′ may include a bit selection circuit 210 ′ and m bit error circuits 220 ′ (n>m>0). The m bit error circuits 220' may include a plurality of bit error circuits BE1 to BEm. The bit selection circuit 210' can receive the mode signal C_MODE, and provide up to m bits of the selection signal SEL to m bit error circuits 220' respectively. In response to the mode signal C_MODE indicating the normal mode, the bit selection circuit 210' can generate the selection signal SEL to disable all the m bit error circuits 220', that is, directly output the bit signal of the encoded data D_ENC as the bit signal of the write data D_WR. On the other hand, in response to the mode signal C_MODE indicating the test mode, the bit selection circuit 210' can generate the selection signal SEL to enable at least one of the m bit error circuits 220', that is, output the bit signal obtained by inverting the bit signal of the encoded data D_ENC as the bit signal of the written data D_WR.

As illustrated in FIG. 3A, m bit error circuits 220' may be arranged to correspond to m bits out of n bits of encoded data D_ENC. The arrangement of the m-bit error circuits 220' shown in FIG. 3A is only exemplary, and unlike the arrangement shown in FIG. 3A, the m-bit error circuits 220' may be arranged in m-bit D_ENC[n:n-m+1] order starting from the most significant bit (MSB) of the encoded data D_ENC, or may be arranged in m-bit D_ENC[m:1] order starting from the most significant bit of the encoded data D_ENC.

In the test mode, the bit selection circuit 210' can simultaneously enable bit error circuits corresponding to the error tolerance of the memory 300a among the m bit error circuits 220'. For example, if the required error tolerance in the memory 300a is one bit, the bit selection circuit 210' can enable one of the m bit error circuits 220'. In addition, the bit selection circuit 210' can replace the bit error circuit to be enabled. For example, the bit selection circuit 210 ′ can generate the selection signal SEL so that when the same encoded data D_ENC is continuously written K times into the same area of the memory 300 a, different K bit error circuits are enabled. As described later below with reference to FIG. 4 , the number of times K of writing data D_WR generated from the same encoded data D_ENC to be written into the same area of the memory 300a can be determined based on the number of bits correctable by the error correction code engine 100a and the error tolerance of the memory 300a.

Referring to FIG. 3B, the error insertion circuit 200a" may include a bit selection circuit 210" and n bit error circuits 220". That is, the error insertion circuit 200a" may include n bit error circuits 220" respectively corresponding to n bits of the encoded data D_ENC. The n bit error circuits 220" may include a plurality of bit error circuits BE1 to BEn. The bit selection circuit 210" can receive the mode signal C_MODE, and can provide n bits of the selection signal SEL to n bit error circuits 220" respectively. The bit selection circuit 210" can generate the selection signal SEL in response to the mode signal C_MODE indicating the normal mode, so that all n bit error circuits 220" are disabled. On the other hand, the bit selection circuit 210" can generate the selection signal S in response to the mode signal C_MODE indicating the test mode EL such that at least one of the n bit error circuits 220" is enabled.

FIG. 4 is a view of an example of writing data D_WR shown in FIG. 2A in a test mode according to an exemplary embodiment of inventive concepts. Referring to FIG. In more detail, FIG. 4 shows the written data D_WR generated from the same encoded data D_ENC and continuously written into the memory 300 a of FIG. 2A . In the example of FIG. 4, the ECC engine 100a of FIG. 2A may correspond to a 2-bit correction ECC system, and the required error tolerance in the memory 300a may be 1 bit. Therefore, the error insertion circuit 200a can generate the write data D_WR with 1-bit error inserted by inverting 1 bit in the encoded data D_ENC. In FIG. 4, shaded portions represent bits inverted by the error insertion circuit 200a. Hereinafter, FIG. 4 will be explained with reference to FIG. 2A.

The number K of writing data D_WR generated from the same encoded data D_ENC to be written into the same area of the memory 300a can be determined based on the number of bits correctable by the ECC engine 100a and the error tolerance of the memory 300a. As shown in the example of FIG. 4, when N is 2 and the error tolerance of the memory 300a is 1 bit, the memory 300a outputting read data D_RD including two or more true bit errors caused by the defect of the memory 300a can be determined to be defective. When the bit error generated by the error insertion circuit 200a is inserted into the same position as the real bit error caused by the defect of the memory 300a, since the real bit error is corrected by the inserted bit error or the inserted bit error and the real bit error are included in the read data D_RD as one bit error so that the read data D_RD includes less bit errors than the real bit error, the effect of the inserted bit error can be eliminated. Therefore, during the processing of the read data D_RD by the error correction code engine 100a, the errors of the read data D_RD can be corrected normally and the memory 300a determined to be defective can be determined to be acceptable. In order to prevent the bit errors inserted by the error insertion circuit 200a from being arranged in the same position as the real bit errors, the error insertion circuit 200a may change the position where the bit errors are inserted. In the example of FIG. 4 , in order to determine that the memory 300a outputting the read data D_RD including two true bit errors is defective, the error insertion circuit 200a may sequentially generate the write data D_WR including bit errors at three different positions.

Referring to FIG. 4, the write data D_WR may include x number of data bits and y number of parity bits (n=x+y), and the error insertion circuit 200a may insert bit errors by inverting the first data bit D1 among the data bits. The write data D_WR obtained by inverting the first data bit D1 of the encoded data D_ENC may be written in the memory 300a, and the read data D_RD may be provided to the ECC engine 100a by reading the data stored in the area of the memory 300a where the write data D_WR is written.

Then, the error insertion circuit 200a may insert bit errors by inverting the third data bit D3 of the data bits. The write data D_WR obtained by inverting the third data bit D3 of the encoded data D_ENC may be written in the memory 300a, and the read data D_RD may be provided to the ECC engine 100a by reading the data stored in the area of the memory 300a where the write data D_WR is written.

Finally, the error insertion circuit 200a can insert bit errors by inverting the fifth data bit D5 of the data bits. The write data D_WR obtained by inverting the fifth data bit D5 of the encoded data D_ENC may be written in the memory 300a, and the read data D_RD may be provided to the ECC engine 100a by reading the data stored in the area of the memory 300a where the write data D_WR is written. It should be appreciated that the locations where bit errors are inserted in FIG. 4 are examples only, and that bit errors may be inserted into any of three different locations.

When the n-bit correcting ECC engine 100a is used and the error tolerance of the memory 300a is 1 bit, the number of repetitions K of writing and reading operations to the same area of the memory 300a may be equal to n+1. In some exemplary embodiments, if the number of bits for writing data or reading data is relatively large, that is, if the size of the data unit processed by the error correction code engine 100a is relatively large, it is unlikely that all bit errors inserted at different locations are at the same location as true bit errors. Therefore, the error insertion circuit 200a may perform less than three (eg, two) write operations and read operations instead of performing three write operations and read operations. For example, in the example of FIG. 4 , it is impossible for both the first data bit D1 and the third data bit D3 to have a true bit error, so the test time of the memory 300a or the device 10a can be shortened by only performing two write operations and a read operation.

FIG. 5 is a flowchart illustrating a method of testing a device for supporting error correction codes according to an exemplary embodiment of the inventive concept. Referring to FIG. In more detail, FIG. 5 illustrates a method of testing the device 10a of FIG. 2A in a test mode. Hereinafter, FIG. 5 will be explained with reference to FIG. 2A.

In operation S110, an initialization operation may be performed. For example, as shown in FIG. 5, the variable i may be set to 1, and the variable i may indicate the number of operations performed to insert bit errors at different positions in the encoded data D_ENC, that is, the number of times the subsequent series of operations (S121 to S126) are performed.

In operation S121, an operation of inverting at least one bit of the encoded data D_ENC may be performed. For example, the error insertion circuit 200a may generate the write data D_WR by inverting at least one bit of the encoded data D_ENC in response to the mode signal C_MODE indicating the test mode.

In operation S122, an operation of writing the write data D_WR to the memory 300a may be performed, and in operation S123, an operation of reading the written data from the memory 300a may be performed. The read data D_RD can be output from the memory 300a by reading the data stored in the area of the memory 300a where the write data D_WR is written.

In operation S124, an error in reading the data D_RD may be corrected. For example, the error correction code engine 100a can receive the read data D_RD from the memory 300a, and can correct errors in the read data D_RD. Then, in operation S125, it may be determined whether error correction is successful. For example, the error correction code engine 100a may have a correctable bit number, and therefore, when the error contained in the read data D_RD exceeds the correctable bit number, the error correction may fail. If the error correction fails, then operation S130 may be performed, and in operation S130, an operation of determining that the memory 300a is defective may be performed. On the other hand, if the error correction is successful, then operation S126 may be performed.

In operation S126, it may be determined whether the variable i is equal to K. That is, it can be determined whether the write operation and the read operation have been performed K times. As described above with reference to FIG. 4 , K can be determined based on the number of errors correctable by the ECC engine 100a and the error tolerance of the memory 300a. If the variable i is equal to K, then operation S140 may be performed, and in operation S140, an operation of determining that the memory 300a is acceptable may be performed. On the other hand, if the variable i is not equal to K, the variable i may be increased by 1 in operation S127, and then operation S121 may be subsequently performed. In operation S121, a bit at a position different from that of a previously inverted bit may be inverted.

6A and 6B are flowcharts illustrating a method of testing a device for supporting error correction codes according to an example embodiment of the inventive concept. In more detail, FIGS. 6A and 6B illustrate a method of testing the device 10b of FIG. 2B in the test mode. Hereinafter, FIG. 6A and FIG. 6B will be explained with reference to FIG. 2B . In addition, the same reference numerals as in FIG. 2B designate the same elements, and thus, repeated descriptions of FIGS. 6A and 6B will not be repeated herein.

Referring to FIG. 6A, in operation S210, an initialization operation may be performed. For example, as shown in FIG. 6A, the variable i may be set to 1, and the variable i may indicate the number of operations performed to insert bit errors at different positions of the read data D_RD, that is, the number of times a series of operations (S231 to S235) are performed.

In operation S220, the write data D_WR may be written. As illustrated in FIG. 6A, the write data D_WR for verifying a specific area of the memory 300b may be written once, and the operation of outputting the read data D_RD by reading the stored write data D_WR may be repeated, as described later below. In this way, compared with the example of FIG. 5 , the number of write operations can be reduced in the example of FIGS. 6A and 6B , and thus the time spent testing the memory 300 b can be relatively shortened.

In operation S231, the stored write data D_WR may be read. The read data D_RD can be output from the memory 300b by reading the data stored in the area of the memory 300b where the write data D_WR is written.

In operation S232, at least one bit of the read data D_RD may be inverted. For example, the error insertion circuit 200b can generate the received data D_RX by inverting at least one bit of the read data D_RD in response to the mode signal C_MODE indicating the test mode.

In operation S233, errors of the received data D_RX may be corrected. For example, the error correction code engine 100b can receive the received data D_RX from the error insertion circuit 200b, and can correct errors in the received data D_RX. Then, in operation S234, it may be judged whether error correction is successful. For example, the error correction code engine 100b may have a number of correctable bits, and thus when the received data D_RX contains errors exceeding the number of correctable bits, the error correction may fail. If the error correction fails, then operation S240 may be performed, and in operation S240, an operation of determining that the memory 300b is defective may be performed. On the other hand, if the error correction is successful, then operation S235 may be performed.

In operation S235, it may be determined whether the variable i is equal to K. That is, it can be determined whether the read operation has been performed K times. As described above with reference to FIG. 4 , K can be determined based on the number of errors correctable by the ECC engine 100b and the error tolerance of the memory 300b. If the variable i is equal to K, then operation S250 may be performed, and in operation S250, an operation of determining that the memory 300b is acceptable may be performed. On the other hand, if the variable i is not equal to K, the variable i may be increased by 1 in operation S236, and then operation S231 may be subsequently performed. In operation S231, the bit at a position different from that of the previously inverted bit may be inverted.

Referring to FIG. 6B , compared with the example of FIG. 6A , the write operation to the write data D_WR can be performed once to verify a specific area of the memory 300b, and the read operation to the stored write data D_WR can also be performed once. That is, since the read data D_RD output by repeatedly reading the stored write data D_WR is the same, the operation of changing only the position of a bit error in the read data D_RD by the error insertion circuit 200b can be repeatedly performed.

As illustrated in FIG. 6B, the operations of FIG. 6B may be the same or similar to the corresponding operations of FIG. 6A. However, if the variable i is not equal to K in operation S235' of FIG. 6B, the variable i may be increased by 1 in operation S236', and operation S232' may be performed instead of operation S231' after operation S236'. Therefore, the operation of writing the write data D_WR in operation S220' and the operation of reading the written data in operation S231' may each be performed once, and in operation S232', the operation of inverting at least one bit of the read data D_RD may be repeatedly performed. Therefore, compared with the example of FIG. 6A , according to the example of FIG. 6B , the number of read operations to the memory 300 b can be reduced.

7A to 7C are block diagrams illustrating examples of bit selection circuits according to example embodiments of inventive concepts. As described above with reference to FIG. 3A and FIG. 3B , the bit selection circuit 210 a , the bit selection circuit 210 b , and the bit selection circuit 210 c of FIGS. 7A to 7C can receive the mode signal C_MODE and output the selection signal SEL. Hereinafter, FIG. 7A to FIG. 7C will be explained with reference to FIG. 1 , and repeated explanations in FIG. 7A to FIG. 7C will not be repeated herein.

Referring to FIG. 7A , the bit selection circuit 210 a may include a bit pattern 211 . The bit selection circuit 210 a can generate a selection signal SEL in response to the mode signal C_MODE indicating a test mode, so that bit errors appear at a certain position according to the bit pattern 211 . For example, as described above with reference to FIG. 4, bit pattern 211 may include three different patterns when bit errors are inserted in three different locations.

Referring to FIG. 7B , the bit selection circuit 210 b may include a random number generator 212 . In response to the mode signal C_MODE indicating the test mode, the bit selection circuit 210b can generate the selection signal SEL so that a bit error occurs at a position according to the random number generated by the random number generator 212 . In some example embodiments, random number generator 212 may be a pseudo-random number generator.

Referring to FIG. 7C , the bit selection circuit 210c can further receive the setting signal C_SET. The setting signal C_SET may, for example, be generated by a signal received from outside the device 10 in FIG. 1 , and may include setting information about the bit selection circuit 210c. In some exemplary embodiments, the setting signal C_SET can determine the number of error correction operations, ie, K, for the same area of the memory 300 . For example, if the number of errors correctable by the ECC engine 100 is fixed, K can be changed according to the setting signal C_SET to adjust the error tolerance of the memory 300 . In addition, as described above with reference to FIG. 4 , in order to shorten the test time, K can be changed, for example, according to the setting signal C_SET so that it is equal to or smaller than the number corresponding to the number of errors correctable by the ECC engine 100 .

FIG. 8 is a flowchart illustrating a method of testing a device for supporting error correction codes according to an exemplary embodiment of the inventive concept. For example, the method of FIG. 8 may represent a method of testing device 10 of FIG. 1 in test mode. In FIG. 8 , the encoded data D_ENC and the written data D_WR in FIG. 1 may be collectively referred to as the written data, and the read data D_RD and the received data D_RX may be collectively referred to as the read data. For example, "generating write data D_WR by inserting errors into encoded data D_ENC" in FIG. 1 may be referred to as "inserting errors into write data", and "generating reception data D_RX by inserting errors into read data D_RD" may be referred to as "inserting errors into read data". Hereinafter, FIG. 8 will be explained with reference to FIG. 1 .

In operation S20, write data may be generated by encoding the input data. For example, the ECC engine 100 in FIG. 1 can generate written data by adding redundancy to the input data D_IN.

In operation S40 , write data can be written into the memory 300 , and read data can be output from the memory 300 . For example, write data can be written in a specific area of the memory 300, and the read data can be output by reading data stored in the area where the write data is written. The error insertion circuit 200 can insert errors into data to be written into the memory 300 (ie, write data), or can insert errors into data read from the memory 300 (ie, read data). Furthermore, in some example embodiments, the error insertion circuit 200 can insert errors into both write data and read data. As illustrated in FIG. 8, operation S40 may include operation S42.

In operation S42, at least one bit of the write data and/or read data may be inverted. For example, the error insertion circuit 200 may include a bit error circuit BE, and at least one bit of the write data and/or the read data may be inverted by enabling at least one bit error circuit BE. The disabled bit error circuit BE can output the input bit signal.

In operation S60, the output data D_OUT may be generated by correcting errors in the read data. For example, the error correction code engine 100 in FIG. 1 can generate output data D_OUT by correcting errors in read data.

In operation S80, defects of the memory 300 may be detected. In some exemplary embodiments, as described above with reference to FIG. 5 , etc., the defect of the memory 300 can be detected according to whether the error correction is successful in operation S60. In some exemplary embodiments, as described later below with reference to FIG. 9 , defects in the memory 300 may be detected based on the output data generated in operation S60.

FIG. 9 is a flowchart illustrating an example of operation S80 shown in FIG. 8 according to an exemplary embodiment of the inventive concept. As described above with reference to FIG. 8, memory defects can be detected. As illustrated in FIG. 9 , operation S80 ′ may include a plurality of operations S82 , S84 and S86 , and FIG. 9 may be explained with reference to FIGS. 1 and 8 .

In some example embodiments, operation S80' may be performed by a test device that provides input data D_IN to device 10 and receives output data D_OUT outside device 10 of FIG. 1 . The test device can use the mode signal C_MODE to set the device 10 into the test mode. The input data D_IN can be provided to the device 10 set in the test mode, and the output data D_OUT corresponding to the provided input data D_IN can be received.

In operation S82, it may be determined whether the input data D_IN and the output data D_OUT are consistent with each other. For example, the test device can determine whether the input data D_IN provided to the device 10 and the corresponding output data D_OUT are consistent with each other. The error-corrected output data D_OUT may be received from the data read from the memory 300 after the input data D_IN is stored in the memory 300 by an encoding process, and the test device may compare the input data D_IN with the output data D_OUT. As described above with reference to the drawings, errors can be inserted into the data encoded from the input data D_IN, and errors can be inserted into the data read from the memory 300 .

If the input data D_IN and the output data D_OUT are still consistent with each other even though the error is inserted, it can be determined that the memory 300 has sufficient error tolerance and the memory 300 is acceptable in operation S84. On the other hand, if the input data D_IN and the output data D_OUT are inconsistent with each other, it may be determined that the error tolerance of the memory 300 is insufficient, and it may be determined that the memory 300 is defective in operation S86.

FIG. 10 is a block diagram illustrating an example of a device for supporting error correction codes according to an example embodiment of the inventive concept. In more detail, FIG. 10 shows a memory device 20 as a noisy channel, and the memory device 20 includes a cell array 21 .

The memory device 20 can receive the command CMD and the address ADDR, and can receive or transmit the data DATA. For example, the memory device 20 may receive a command CMD such as a write command, a read command, and an address ADDR corresponding to the command CMD from the memory controller. In addition, the memory device 20 can receive data DATA (ie, input data) from the memory controller or provide the data DATA (ie, output data) to the memory controller. Although FIG. 10 shows the command CMD, the address ADDR, and the data DATA separately, in some example embodiments, at least two of the command CMD, the address ADDR, and the data DATA may be transmitted through the same channel. As shown in FIG. 10 , the memory device 20 may include a cell array 21, a read/write circuit 22, an error insertion circuit 23, an error correction code engine 24, a column decoder 25_1, a row decoder 25_2, an address register 26_1, a data register 26_2, a control logic 27, and an input/output circuit 28.

The cell array 21 can include a plurality of memory cells and can store data. Since the cell array 21 contains defects, an error may occur that the data read from the cell array 21 by the read/write circuit 22 is different from the data written into the cell array 21 . To correct the error, the error correction code engine 24 may generate data by encoding data DATA (ie, input data) received together with the write command CMD, and may generate data DATA (ie, output data) generated by correcting errors in data read from the cell array 21 in response to the read command CMD.

The error insertion circuit 23 can receive the mode signal C_MODE from the input/output circuit 28 , and can insert errors into the data transmitted between the read/write circuit 22 and the error correction code engine 24 in response to the mode signal C_MODE indicating a test mode. Furthermore, the error insertion circuit 23 can change the position where errors are inserted. The number of errors inserted by error insertion circuit 23 may correspond to the error tolerance of cell array 21 . Therefore, it can be easily verified whether the cell array 21 has sufficient error tolerance, and thus defects in the memory device 20 can be easily detected.

The column decoder 25_1 can enable at least one of the plurality of word lines connected to the cell array 21 according to the column address provided from the address register 26_1 . The row decoder 25_2 can select some of the signals output from the memory cells connected to the enabled word line according to the row address provided from the address register 26_1.

The address register 26_1 can receive and store the address ADDR from the input/output circuit 28 . The data register 26_2 can store the data received from the I/O circuit 28 and can provide the stored data to the ECC engine 24 . In addition, the data register 26_2 can store the data received from the ECC engine 24 and provide the stored data to the input/output circuit 28 .

The control logic 27 can generate control signals for operating the memory device 20 according to the command CMD received from the input/output circuit 28 , and the control signals can be respectively provided to components included in the memory device 20 .

The input/output circuit 28 can receive the command CMD, the address ADDR and the data DATA from outside the memory device 20 and output the data DATA. In some example embodiments, input/output circuitry 28 may decode command CMD and provide the decoded result to control logic 27 .

FIG. 11 is a block diagram illustrating an example of a device for supporting error correction codes according to an example embodiment of the inventive concept. In more detail, FIG. 11 shows a memory system 30 and a host 40 communicating with the memory system 30. The memory system 30 includes a memory device 32 as a noisy channel.

The memory system 30 can communicate with the host 40 through the interface 50 . The interface 50 that enables the memory system 30 and the host 40 to communicate with each other can use electrical signals and/or optical signals, and can be implemented by, but not limited to, the following: serial advanced technology attachment (SATA) interface, serial advanced technology attachment express (SATA express, SATAe) interface, serial attached small (serial attached small, SAS) computer system interface, peripheral component interconnection express (per ipheral component interconnect express (PCIe) interface, nonvolatile memory-express (nonvolatile memory-express, NVMe) interface, advanced host controller interface (advanced host controller interface, AHCI) or a combination of the above interfaces.

In some exemplary embodiments, the memory system 30 can communicate with the host 40 by being removably coupled to the host 40 . The memory device 32 may be a non-volatile memory, such as a resistive memory, and the memory system 30 may be referred to as a storage system. For example, the memory system 30 may be implemented by but not limited to: a solid-state drive or a solid-state disk (solid-state disk, SSD), an embedded solid-state disk (embedded SSD, eSSD), a multimedia card (multimedia card, MMC), an embedded multimedia card (embedded multimedia card, eMMC), and the like.

As illustrated in FIG. 11 , the memory system 30 may include a controller 31 and at least one memory device 32 . The at least one memory device 32 can receive the command CMD and the address ADDR received from the controller 31, and can receive or transmit the data DATA.

The controller 31 can control at least one memory device 32 in response to a request received from the host 40 through the interface 50 . For example, the controller 31 may write the data received together with the write request into the at least one memory device 32 in response to the write request, or may provide the data stored in the at least one memory device 32 to the host 40 in response to the read request. As shown in FIG. 11 , the controller 31 may include an error insertion circuit 31_1 and an error correction code engine 31_2 .

In some exemplary embodiments, the error insertion circuit 31_1 may insert errors into data obtained by encoding the data requested to be written from the host 40 in the test mode by the error correction code engine 31_2, and may provide the error-inserted data to the at least one memory device 32 as write data. In some exemplary embodiments, the error insertion circuit 31_1 can insert errors into the data read from at least one memory device 32 in response to the read request of the host 40 in the test mode, and can provide the error-inserted data to the error correction code engine 31_2. In addition, the error insertion circuit 31_1 can change the position where errors are inserted. The number of errors inserted by the error insertion circuit 31_1 may correspond to the error tolerance of the at least one memory device 32 . Therefore, it can be easily verified whether the at least one memory device 32 has sufficient error tolerance.

While the inventive concepts have been particularly shown and described with reference to exemplary embodiments thereof, it should be understood that various changes in form and details may be made without departing from the spirit and scope of the following claims.

10, 10a, 10b‧‧‧Devices 20, 32‧‧‧memory device 21‧‧‧cell array 22‧‧‧Read/write circuit 23, 31_1, 200, 200a, 200a', 200a'', 200b‧‧‧wrong insertion circuit 24‧‧‧Error Correction Code Engine 25_1‧‧‧column decoder 25_2‧‧‧Row Decoder 26_1‧‧‧address register 26_2‧‧‧data register 27‧‧‧Control Logic 28‧‧‧Input/Output Circuit 30‧‧‧memory system 31‧‧‧Controller 31_2, 100, 100a, 100b‧‧‧Error Correction Code Engine 40‧‧‧host 50‧‧‧Interface 210', 210'', 210a, 210b, 210c‧‧‧bit selection circuit 211‧‧‧bit patterns 212‧‧‧Random Number Generator 220', 220'', BE, BE1 to BEm, BEn‧‧‧bit error circuit 300, 300a, 300b‧‧‧memory ADDR‧‧‧address CMD‧‧‧command/write command/read command C_MODE‧‧‧mode signal C_SET‧‧‧set signal D1‧‧‧first data bit D2, D4, Dx, P1-Py‧‧‧bit position D3‧‧‧The third data bit D5‧‧‧fifth data bit DATA‧‧‧data D_ENC‧‧‧encoded data D_IN‧‧‧Input data D_OUT‧‧‧output data D_RD‧‧‧Read data D_RX‧‧‧receive data D_WR‧‧‧write data IN‧‧‧input signal INV‧‧‧Inverter OUT‧‧‧output signal S20, S40, S42, S60, S80, S80', S82, S84, S86, S110, S121, S122, S123, S124, S125, S126, S127, S130, S140, S210, S210', S220, S220', S231, S231', S2 32. S232', S233, S233', S234, S234', S235, S235', S236, S236', S240, S240', S250, S250'‧‧‧operation SEL‧‧‧select signal SW‧‧‧Switch

Exemplary embodiments of the inventive concept will be more clearly understood from the following detailed description when read in conjunction with the accompanying drawings, in which: FIG. 1 is a block diagram of an apparatus for supporting error correction code (ECC) according to an exemplary embodiment of the inventive concept. Referring to FIG. 2A and 2B are block diagrams illustrating an example of the device shown in FIG. 1, according to an example embodiment of the inventive concept. 3A and 3B are block diagrams illustrating an example of the error insertion circuit shown in FIG. 1, according to an example embodiment of the inventive concept. FIG. 4 is a view of an example of writing data shown in FIG. 2A in a test mode according to an exemplary embodiment of the inventive concept. FIG. 5 is a flowchart illustrating a method of testing a device for supporting error correction codes according to an exemplary embodiment of the inventive concept. Referring to FIG. 6A and 6B are flowcharts illustrating a method of testing a device for supporting error correction codes according to an example embodiment of the inventive concept. 7A to 7C are block diagrams illustrating examples of bit selection circuits according to example embodiments of inventive concepts. FIG. 8 is a flowchart illustrating a method of testing a device for supporting error correction codes according to an exemplary embodiment of the inventive concept. FIG. 9 is a flowchart illustrating an example of operation S80 shown in FIG. 8 according to an exemplary embodiment of the inventive concept. FIG. 10 is a block diagram illustrating an example of a device for supporting error correction codes according to an example embodiment of the inventive concept. FIG. 11 is a block diagram illustrating an example of a device for supporting error correction codes according to an example embodiment of the inventive concept.

10‧‧‧Devices

100‧‧‧Error Correction Code Engine

200‧‧‧Wrong insertion into the circuit

300‧‧‧memory

BE‧‧‧bit error circuit

C_MODE‧‧‧mode signal

D_ENC‧‧‧encoded data

D_IN‧‧‧Input data

D_OUT‧‧‧output data

D_RD‧‧‧Read data

D_RX‧‧‧receive data

D_WR‧‧‧write data

IN‧‧‧input signal

INV‧‧‧Inverter

OUT‧‧‧output signal

SW‧‧‧Switch

Claims (6)

A device supporting a test mode for memory testing, the device comprising: a memory configured to receive and store write data and output read data from the stored write data; an error correction code (ECC) engine configured to generate the write data by encoding input data and generate output data by correcting error bits of N bits or less included in the received data, where N is a positive integer; and an error insertion circuit configured to provide the read data to the error correction in a normal mode A code engine serves as the received data, and provides data obtained by inverting at least one bit less than N bits of the read data to the error correction code engine as the received data in the test mode, wherein the error insertion circuit is further configured to change a position of the at least one bit in the read data continuously output from the memory in the test mode K times, wherein K is an integer equal to or greater than 2, and K is equal to or smaller than N and is determined based on the size of data processed by the error correction code engine. A device supporting a test mode for memory testing, the device comprising: a memory configured to receive and store write data and output read data from the stored write data; an error correction code (ECC) engine configured to generate encoded data by encoding input data and by correcting N bits included in the read data and an error insertion circuit configured to receive the encoded data directly from the error correction code engine, wherein the error insertion circuit is further configured to provide the encoded data to the memory as the write data in a normal mode, and provide data obtained by inverting at least one bit less than N bits of the encoded data to the memory in the test mode as the write data. The device according to claim 2, wherein the error insertion circuit is further configured to change the position of the at least one bit in the encoded data continuously written into the memory K times in the test mode, wherein K is an integer greater than or equal to 2. A method of testing a device comprising an error correcting code (ECC) engine and memory configured to correct error bits of N bits or less, where N is a positive integer, comprising: generating encoded data by encoding input data by the error correcting code engine; writing write data into the memory, reading the write data, and outputting read data; and generating output data by correcting errors of the read data by the error correcting code engine, wherein Writing the write data includes directly obtaining the encoded data from the ECC engine, and writing the write data further includes providing the obtained data as the write data in a normal mode, and generating the write data by inverting at least one bit less than N bits of the obtained data in a test mode. The method described in claim 4 of the claimed invention further includes: detecting a defect of the memory based on the input data and the output data. The method described in claim 4, wherein generating the output data includes: detecting by the error correction code engine whether correction of error bits in the read data is successful, and detecting defects of the memory based on whether the correction is successful.