JPS6237420B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention provides a processing device equipped with a key storage unit for memory protection of the main storage unit, which improves the speed of access to the main storage unit and the reliability of the key storage unit. The present invention relates to a key storage controller with improved performance.

(2) Prior art and problems Conventionally, in computers that perform virtual memory control on the main memory (MS), a key memory (KS) is used to protect the memory and keep a history of references to the main memory. is used. KS is main memory (MS)
The KEY part is compared with the key in the PSW (Program Status Word) of the program that refers to it, and the RC stores the status of whether or not the content paged in from the virtual memory to the main memory has been read or written.
It has a department.

FIG. 1 shows the configuration of the KS, which is divided into four sections, KEY, F, R, and C, according to logical fields, and further functionally divided into the KEY part and the RC part, the first two and the latter two. The functions of each category are as follows.

KEY; MS access control key for memory protection F; MS fetch control bit for memory protection R; MS reference memory bit C; MS change memory bit In other words, the KEY part consisting of KEY and F
The validity of the access is confirmed by comparing it with the program key, and if there is even one read or write access to the RC section consisting of R and C, set R to "1".
If a change is written, C is set to "1".

This allows you to know how the program is being used.

Access operations for this KS include “KS read” (for reading with KS key commands, etc.) “KS write” (for writing with KS key commands etc.) “KS update” (for reading and writing for MS access) ) There are three types. What is actually written on the “KS update date” is
Although only the RC section is read, the KEY section is always read before that to protect the memory. In contrast, “KS read” and “KS light” are
Both the KEY section and RC section are eligible.

In the MS access operation of "KS update date," especially in computers equipped with a buffer storage (BS), access to MS data is usually performed at high speed in one cycle, so it is necessary to speed up the KS update operation. There is no effect using BS. On the other hand, in the update operation of KS,
Since the KEY part is read and the RC part is written, it usually takes two cycles, and the effect of the high-speed access of the BS, which has been achieved in the conventional method, is lost.

Therefore, it is desirable to adapt the BS to high-speed access without impairing the functions of the KS, depending on the content of the access operation to the KS.

Also, with "KS write", all the contents of KS will be rewritten, so you must be very careful not to write to the wrong address.

(3) Purpose of the invention The purpose of the present invention is to protect the main memory.
An object of the present invention is to provide a highly reliable key storage controller that allows high-speed access to a KS without impairing necessary functions.

(4) Structure of the Invention In order to achieve the above object, the key storage control device of the present invention includes a key section for memory protection of the main memory section and a history storage bit section for main memory reference for virtual memory control. In a computer equipped with a key storage section, the contents of the key storage section are divided into the key section and the history storage bit section, and address registers corresponding to each section are provided so that each section can be read and written separately. The present invention is characterized in that reading and writing are performed only on necessary parts among the respective parts according to the type of access operation to the key storage section.

(5) Embodiments of the Invention The principle of the present invention is that instead of controlling the entire KS in two cycles using one address register as in the past, the KS is divided into the KEY section and the RC section as described above. address registers are provided for each to perform separate control, and the above-mentioned
By variably setting the read and write timings after address setting in the KEY and RC sections and performing a series of pipeline controls, it is possible to maintain high reliability while adapting to the speed of the BS.

FIGS. 2a to 2c are explanatory diagrams of the operation of the embodiment of the present invention according to the above principle.

In the present invention, as shown in Fig. 1, the entire KS is
Divided into two parts, KEY part and RC part, KS address registers KSAR _K and KSAR _R for each.
are set up and controlled separately.

The following operations are performed using this KS address register depending on the type of access.

In the case of "KS read" in figure a, address registers KSAR _K and KSAR _R are set at the same time, and in the next cycle after both address registers are set.
Read both the KEY part and RC part of KS and write KSr.
(Read) Output data.

In the case of "KS write" in figure b, address registers KSAR _K and KSAR _R are set at the same time, and both address registers are set in the next cycle after setting.
KSAR _K and KSAR _R are checked, and only if there are no errors, they are checked again in the next cycle.
Write to both the KEY section and RC section. In this way, pipeline control is performed by sequentially shifting the read/write cycles of the KEY section and RC section, thereby preventing destruction of the contents of erroneous addresses and preventing system malfunctions.

In the case of "KS update" shown in FIG. 3c, that is, MS read/write, a memory protection check of the KEY part is performed by KS read in the same cycle as MS access, and KS write is performed in the next cycle. The KEY section is set so that the next cycle of KSAR _K set reads the KEY section and performs a memory protection check by comparing with the PSW key, and the next cycle of KSAR _R set writes to the RC section.
Pipeline control is performed by sequentially shifting read/write of the RC section.

Previously, the KS was controlled all at once, but the KEY section and
By dividing the data into two parts in the RC part, processing each cycle, and controlling the pipeline by shifting the data, high-speed access that matches the BS becomes possible. In this case, some tolerance is required since processing is performed every cycle.

For example, during "MS access" in figure c,
The RC part is written immediately in the cycle following the KSAR _R set, but in this case, the R bit of the RC part,
Since only "1" is written to each C bit, even if an error occurs in KSAR _R and a write is made to the wrong address, the R bit and C bit will always be referenced and changed in the MS data. There is no need for data to become garbled, as the data simply changes. Therefore, this point is tolerated and emphasis is placed on speeding up.

FIG. 3 is an explanatory diagram showing the configuration of an embodiment of the present invention.

In the figure, KS1 is divided into a KEY section ₁₁ and an RC section ₁₂ , as shown in FIG. 1, and accessed by KSAR _K2 and KSAR _R3 , respectively.
Then, write data KSw (write) data such as KS key command is input to the R and C of the KEY section 1 ₁ and the RC section 1 ₂ , and in the case of MS access, the R and C of the RC section 1 ₂ are input.
with multiplexers 1 ₃ and 1 ₄ for C, respectively.
KSw (write) data and switching, MSr/w (read/write), and MSw (write) are input.

First, in the case of “KS read”, KEY part 1 of KS1
The contents of ₁ and RC section 1 _{and 2} are accessed by KSAR _K 2 and KSAR _R 3, and KSr (read) data is obtained from the KEY section and RC section in the procedure shown in FIG. 2a.

In the case of “KS Lite”, KEY1 ₁ of KS1 and
RC parts 1 and ₂ are accessed by KSAR _K 2 and KSAR _R 3, respectively, and this KSAR _K 2 and
Check the contents of KSAR _R 3 for errors using checkers 5 and 6, and check the inverted signals after checking.
It is assumed that one input of each of the AND circuits 8 and 10 is used, and the other input is a KSWOP (write operation) signal that is input to the flip-flop 7 and is delayed by one cycle from KSw (KSw+1).

The output of the AND circuit 8 is passed through the flip-flop 9 to output a write enable signal _KEK for the KEY section, and the output of the AND circuit 10 is passed through the OR circuit 14 and sent to the flip-flop 15 as an RC signal.
Outputs a write enable signal _WER for the section. These WE _K and WE _R are shown in Figure 2b.
KEY part and RC part are obtained.

For “MS Access”, in the first cycle
Access KEY part 1 ₁ of KS1 with KSAR _K2 ,
The comparator 11 compares the KEY read out from the KEY unit 1 ₁ and the program state word key (PSWKEY) 4 of the MS, and outputs the inverted signal via the NOT circuit 12. yon) signal to the AND circuit 13,
The output is passed through an OR circuit 14 and a flip-flop 15 to output a write enable ( _WER ) signal.

If there is a mismatch, the RC
Part _1-2 is not accessed. If there is a match, it outputs the WE _R signal and outputs the KSAR _{R signal} in the next cycle.
3 accesses the RC section ₁₂ and rewrites R and C in the RC section ₁₂ .

In this case, in the next cycle after setting KSAR _R3 , the RC unit ₁₂ is set without waiting for the error check result.
By writing R and C, the RC part shown in FIG. 2c is obtained. This alone enables high-speed access using "MS access." Also, errors in KSAR _K and KSAR _R are checked separately, and if an error is detected, the instruction can be retried.
Even if the RC part of another address were to be rewritten, both the R and C bits would only change in the direction of "1", so although the efficiency may decrease somewhat, there will be no malfunction. .

In any case, in this "MS access", the KEY part is read in the first cycle and a memory protection check is performed, and the RC part is written in the next cycle, but the permissible procedure is omitted and each cycle By adopting a pipeline control method that performs processing in parallel, high-speed access that matches the BS becomes possible.

(6) Effects of the Invention As explained above, according to the present invention, the contents of the KS are divided into a plurality of logical field units, address registers corresponding to each part are provided and operated separately, and access to the KS is improved. The read and write timings of the fields in the above section are variably set according to the operations "KS read", "KS write", and "MS access", and a series of pipeline controls are performed. This provides a highly reliable KS control method that enables high-speed access that matches the speed of the BS.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the configuration of a KS used in the present invention, FIGS. 2 a to c are explanatory diagrams of the operation of an embodiment for explaining the principle of the present invention, and FIG. 3 is an explanatory diagram of the configuration of an embodiment of the present invention. , 1 in the figure is the key storage unit (KS), 1 ₁ is the key storage unit (KS),
KEY section, 1 ₂ is RC section, 2 and 3 are KS address registers, 4 is program status word key section, 5 and 6 are checkers, 7, 9, and 15 are flip-flops, 8,
10 is an AND circuit, 11 is a comparison circuit, 12 is NOT
The circuit 14 shows an OR circuit.

Claims (1)

[Claims] 1. In a computer equipped with a key storage section consisting of a key section for memory protection of the main memory section and a history storage bit section for main memory reference for virtual memory control,
The contents of the key storage section are divided into the key section and the history storage bit section, and address registers corresponding to each section are provided so that each section can be read and written separately, and access operations for the key storage section are performed. A key storage unit control device characterized in that reading and writing are performed only to necessary portions among the respective portions according to the type of the key storage portion.