JPS57134704A - Programmable logical controller - Google Patents
Programmable logical controllerInfo
- Publication number
- JPS57134704A JPS57134704A JP56019814A JP1981481A JPS57134704A JP S57134704 A JPS57134704 A JP S57134704A JP 56019814 A JP56019814 A JP 56019814A JP 1981481 A JP1981481 A JP 1981481A JP S57134704 A JPS57134704 A JP S57134704A
- Authority
- JP
- Japan
- Prior art keywords
- output
- status
- flag
- control means
- user
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/461—Saving or restoring of program or task context
- G06F9/463—Program control block organisation
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
- Safety Devices In Control Systems (AREA)
- Programmable Controllers (AREA)
Abstract
PURPOSE:To execute an operation where the status of each output terminal is set to a specific content in accordance with the failure state, with a user's grogram with a minimum length, by providing a specific flag and an output status control means. CONSTITUTION:Every time when a user's program is executed, the content of an output buffer memory is renewed with the output data obtained from this execution and the content of the output buffer memory is transferred to an output interface circuit at each renewal. In such a programmable logical controller (PLC), a flag which can be operated by using a user's program and an output status control means which inhibits the transfer of the output data to the said output interface circuit from the said output buffer memory in accordance with the status of the flag are provided. For example, said flag is provided in a status storage section 5 and said output status control means is provided in a central processing device 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56019814A JPS57134704A (en) | 1981-02-13 | 1981-02-13 | Programmable logical controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56019814A JPS57134704A (en) | 1981-02-13 | 1981-02-13 | Programmable logical controller |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57134704A true JPS57134704A (en) | 1982-08-20 |
JPS648841B2 JPS648841B2 (en) | 1989-02-15 |
Family
ID=12009788
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56019814A Granted JPS57134704A (en) | 1981-02-13 | 1981-02-13 | Programmable logical controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57134704A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5947602A (en) * | 1982-09-13 | 1984-03-17 | Omron Tateisi Electronics Co | Programmable controller |
JPS62150434A (en) * | 1985-12-24 | 1987-07-04 | Nippon Denso Co Ltd | Loop control type data processor |
-
1981
- 1981-02-13 JP JP56019814A patent/JPS57134704A/en active Granted
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5947602A (en) * | 1982-09-13 | 1984-03-17 | Omron Tateisi Electronics Co | Programmable controller |
JPH0375883B2 (en) * | 1982-09-13 | 1991-12-03 | Omron Tateisi Electronics Co | |
JPS62150434A (en) * | 1985-12-24 | 1987-07-04 | Nippon Denso Co Ltd | Loop control type data processor |
JPH0578856B2 (en) * | 1985-12-24 | 1993-10-29 | Nippon Denso Co |
Also Published As
Publication number | Publication date |
---|---|
JPS648841B2 (en) | 1989-02-15 |
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