JPH0344739A - Instruction exception detecting device - Google Patents

Abstract

PURPOSE:To miniaturize the scale and to increase the working speed of an instruction exception detecting device by providing an instruction decoding PLA which outputs the valid data showing the undefined and defined instructions and an undefined instruction detecting circuit which decides an undefined or defined decoding instruction based on the valid data. CONSTITUTION:An instruction decoding PLA 2 decodes an instruction and outputs the data (valid data) showing a defined or undefined instruction. An undefined instruction detecting circuit 6 decides an undefined input instruction when the valid data outputted from the PLA 2 shows an undefined instruction and an instruction decoding control circuit 8 decides a valid input instruction of the PLA 2. Then a control memory address generating circuit 3 produces the head address of an instruction exception process routine as an address of a control memory 4. The memory 4 produces a corresponding microinstruction (instruction exception process). Thus it is possible to obtain a compact and high speed instruction exception detecting device having a simple decoding method.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an instruction exception detection device for detecting undefined instructions and privileged instruction execution violations during processor instruction decoding and microinstruction issuance. As a conventional instruction exception detection device (for example, JP-A-59
10 shows the constituent countries of this conventional instruction exception detection device, 100 is an instruction decoder, 101 is an initial address generator, and 4102 is an address selection device. In the circuit 103 is the micro address register, %
104 is a microprogram storage device 4 10
Reference numeral 5 denotes a microinstruction register.The operation of the conventional instruction exception detection device configured as described above will be explained below.Instruction decoder 10
0 and the initial address generator 101 store only information related to defined instructions. However, if the instruction is an undefined instruction (above), any AND term is unselected in the instruction decoder 100 (does not correspond to any defined instruction). However, even if address 0 is output from the initial address generator 101 (because of this), the contents of address O of the microprogram storage device 104 are selected and an undefined instruction processing routine is activated. If the instruction decoder and initial address generator are implemented using PLA, etc.,
When generating addresses etc. using multiple selection, some AND terms are selected even if it is an undefined instruction, and address O is not output. For example, if the addressing mode specification field, which is a field common to multiple instructions, is decoded independently of the operation field of the instruction, it will be considered an undefined instruction and the common field will not be decoded. Even if some AND terms are selected (this phenomenon is called ghosting due to PLA), if undefined instruction is detected at address O, the instruction decoding method is fixed and the number of PLA terms (
The AND term and the OR ring corresponding to the AND term are collectively referred to as a term). Furthermore, the effect of multiple selection, which is a feature of PLA, is reduced.

In addition, when a predefined instruction that has an addressing mode that is prohibited from use (referred to as a prohibited addressing mode) is decoded, the base initial address is generated only by the operation field of the instruction. For example, when decoding an instruction that is allowed to be used in register indirect addressing mode and prohibited to use in register relative indirect addressing mode, only some microinstructions are different. , since the address is determined by the Operator 3 system, exactly the same address will be generated.

-X One way to solve the above problems is to always output the initial address even for undefined instructions and allocate a microinstruction for undefined instruction processing routine branching in the microprogram storage device. Corresponding to definition instructions would result in an increase in the size of the instruction decoder, initial address generator, and microprogram storage device.

As mentioned above, conventional instruction exception detection devices have problems such as the large 4L instruction decoding device, which increases the decoding time, that is, reduces the speed, and reduces the flexibility of the instruction decoding method. As a definition instruction detection method, there is a method shown in Japanese Patent Application Laid-Open No. 62-70937, and although the principle is the same, the present invention takes into account these points. It is an object of the present invention to provide an instruction exception detection device that allows easy modification of instructions and functions. If the bit pattern of the field specifying the basic operation is not defined as an instruction, the data indicating that it is an undefined instruction is decoded independently, and if the bit pattern of the field specifying the basic operation is defined as an instruction and the accompanying If the basic action has an accompanying action, the data indicating the accompanying action permitted by the basic action is stored, and if the bit pattern of the field specifying the basic action is defined as an instruction and does not have an accompanying action, the basic action has an accompanying action. The field that specifies the accompanying action is decoded independently of other fields L/% An instruction decoding control means for managing data indicating whether the instruction is valid or invalid; and an instruction decoding control means for managing data indicating whether the instruction is valid or invalid; and if the data output from the instruction decoding control means indicates that the instruction being decoded is valid, the instruction decoding control means The fourth aspect of the invention according to claim 2 is an instruction exception detection device comprising undefined instruction detection means for detecting an undefined duplicated instruction from data output from the instruction.
an instruction decoding means for decoding a field specifying the basic operation of the instruction independently of other fields and generating data indicating a state of the processor in which execution of the instruction is permitted; and an instruction decoding control means for managing the state of the processor. , an instruction execution method that determines whether execution of the instruction is currently permitted or not based on data indicating the state of the processor whose execution is permitted output from the instruction decoding means and the state of the processor output from the instruction decoding control means; An exception detection device having violation detection means according to claim 3, wherein a field specifying a basic operation of an instruction is decoded independently of other fields, and a bit pattern of the field specifying the basic operation is detected as an instruction. If the bit pattern of the field specifying the basic operation is defined as an instruction and has an additional operation, the data indicating that it is an undefined instruction if it is not defined, and the accompanying operation permitted by the basic operation. If the bit pattern of the field specifying the basic action is defined as an instruction and does not have an accompanying action, output data indicating that the basic action does not have an accompanying action. An instruction decoding means that decodes data independently of other fields and outputs data indicating a specified accompanying action, and an instruction decoding control that manages data indicating whether the instruction being decoded by the instruction decoding means is valid or invalid. If the data output from the instruction decoding control means indicates that the instruction being decoded is valid, an undetermined copy instruction is detected from the data output from the instruction decoding control means. Definition instruction detection means An exception detection device equipped with a control memory storing a microprogram is used.The invention according to claim 1 decodes the instruction in the instruction decoding means by the above-mentioned means, and the data output from the instruction decoding control means. indicates that the instruction being decoded is valid, and the data output from the instruction decoding means indicates that the instruction being decoded is an undefined instruction. If the data output from the decoding control means indicates that the instruction being decoded is valid, and if the data output from the instruction decoding means indicates that the instruction being decoded is a defined instruction with an accompanying action, If a combination of ancillary operations that are not permitted based on the data indicating the ancillary operations permitted by the basic operation of the instruction and the data indicating the ancillary operations specified in the instruction occurs, the instruction is determined to be an undefined instruction. In the invention according to claim 2, the instruction is decoded by the instruction decoding means by the above-mentioned means, and the state of the processor is compared with data indicating the state of the processor that is permitted to execute.
Rather than determining that the instruction is currently not allowed to be executed,
Although an instruction exception is detected, the invention according to claim 3 decodes the instruction in the instruction decoding means by the above-mentioned means, and the data output from the instruction decoding control means indicates that the instruction being decoded is valid, and the instruction is decoded. If the data output from the instruction means indicates that the instruction being decoded is an undefined instruction, it is detected that the instruction is an undefined instruction, and the data output from the instruction decoding control means indicates that the instruction being decoded is valid. , and the data output from the instruction decoding means indicates that the instruction being decoded is a defined instruction with accompanying actions, the data output from the instruction decoding means is data indicating the accompanying actions permitted by the basic action of the instruction. If a combination of ancillary operations that are not allowed occurs based on the data indicating the ancillary operations specified in the instruction, it is detected that the instruction is an undefined instruction. When it is determined that the instruction is a defined instruction, the undefined instruction processing microroutine stored in the control memory is activated from the address output by the 6th instruction decoding means.In particular, when an undefined instruction is detected, the embodiment shown in FIG. This is a block diagram of the instruction exception detection device of the present invention. , microinstruction,
Data indicating available addressing modes for the instruction (
4 bits) (referred to as possible addressing mode data)
, data (2 bits) indicating the addressing mode specified by the instruction being decoded (referred to as specified addressing mode data), and data (1 bit) indicating the fixed copy instruction or undefined instruction (referred to as valid data). Instruction decoding PLA, on 3ζ Table 41 of control memory address generation times that generate control memory addresses Control memory that stores microprograms (AtoI node is 1
0 bit), 5 (top) Microinstruction register register that temporarily holds macroinstructions output by control memory 4.
6 (Part 1: Undefined instruction detection to determine whether the decoded instruction is undefined or fixed copy 71 Yo Instruction decoding P
Prohibited addressing mode detection circuit that detects the use of a prohibited addressing mode from the data indicating usable addressing modes of the instruction output by LA2 and the data indicating the addressing mode specified by the instruction being decoded 8 (
Friend: Whether the command currently being decoded is valid or invalid ("valid" and "invalid" used here)
Management of instructions (instructions that have no meaning in treating them as instructions are called "invalid instructions") and whether or not the processor is currently operating in a privileged state Command deciphering control loop to manage 2nd
Although the instruction format used in this example uses 16 bits as a unit of decoding, the following two formats are used for simplification: 6-bit operation specification section 4-bit register direct mode specification on 4tOAi!
An instruction format with a 6-bit addressing mode designation section 410B+1 a 10-bit operation designation section 6-bit addressing mode N An instruction format with a window section 410Ci & 16
Only the bit oberhesion specification part is transferred. It is also an instruction format that does not have an addressing mode specification.
Above 201 in FIG. 3 is a list of instructions and bit patterns used in this embodiment. For the sake of simplicity, only the instructions used in the explanation are described. Figure 4 shows the addressing modes and bit patterns of the instructions used in this example. There are three types of addressing mode ((Rn)), immediate addressing mode (I m m ), and register direct addressing mode (Rn).
The address mode that can be used for the instruction and the address mode that can be used for the instruction and whether the instruction is a privileged instruction (an instruction that can only be executed when the processor is operating in a privileged state. A privileged instruction is executed in a non-privileged state. If an attempt is made to do so, a privileged instruction violation exception will occur), or the bit pattern of the data field indicates that the available addressing modes for a certain non-privileged instruction are
Imrrz! :Rn is 1ヱ field is oi
Output io'. Outputs "tit o o o o" for instructions that do not have an addressing mode.
In addition, if the addressing mode is 75 ((Rn), which can be used for a certain privileged instruction, the field contains "100".
Outputs 1'. In the case of an instruction that does not have an addressing mode, it outputs ``1000'' (501 in Figure 6).
This is the bit pattern of the data field that indicates the addressing mode of the instruction being decoded.For example, if the addressing mode specification part of the instruction being decoded is (Rn), it will output "'01".
If it is not in the addressing mode bit pattern, 00" is output as there is no addressing mode. Also, 606 in FIG. 7 is a list of patterns used in the prohibited addressing mode detection circuit 7 to detect the use of prohibited addressing modes. Prohibited Since addressing mode detection does not matter whether the instruction is a privileged instruction or not, the 0th bit is DON.
' T CARE LOGIC (value 0 or 1
However, it does not affect the operation).
701 in the figure is the data stored in the instruction decoding PLA 2 used in this embodiment. 71 to 85 correspond to each term of the instruction decoding PLA 2. Here, only the terms necessary for explaining in this embodiment are shown. Since the microinstructions are not related to this embodiment, their values are not described here. 90 in FIG. 9 is a microprogram to be stored in the control memory 4 used in this embodiment. 91
96 is a microinstruction corresponding to each address, but if it is written as data, the meaning will be unclear. The meaning of the microinstruction will be described. Regarding the instruction exception detection device of this embodiment configured as described above, (A) First, defined instruction A “ORR5, R9” (bit pattern” 001001. 0101 00100
(AI) is temporarily held in the instruction register 1 and is manually input to the instruction decoding PLA2 (A2) In the instruction decoding PLA2, term 71, ? 4.
77, 79 are selected and control memory address field = 00101001i0'' (74, 77, 79) Possible Addressing Mode Booter Field = 01
01' (74, 77) Specified addressing mode data field = it''
(79> Valid data field=]" (71) is output. The selected term is clear from FIG. 8. (A3) Instruction decoding control circuit 8 GL Instruction decoding PLA
Assume that the input command 2 is determined to be a valid command.
Therefore, even if all output fields of the instruction decoding PLA2 are valid (A4), the undefined instruction detection circuit 6 confirms that the output field of the instruction decoding PLA2 is valid data field -1, and that the instruction decoding control circuit 6 inputs the input of the instruction decoding PLA2. Since the command is judged to be a valid command, it is determined that the manual command is a defined command.(A5) Is the prohibited addressing mode detection circuit? The possible addressing mode data field of the C & instruction decoding PLA2 output is 0101, the specified addressing mode data field of the instruction decoding PLA2 output is 11, and the input instruction of the instruction decoding PLA2 is Since it is determined to be a defined instruction, it is determined that it is not a prohibited addressing mode. In the list 60 of patterns for detecting the use of prohibited addressing modes, it is clear that the prohibited addressing mode detection item is "0", but since this instruction is not a privileged instruction, it is a violation of privileged instruction execution. No need to perform detection 1. % (80〉 Control memory address generation circuit 3) Since the manual instruction is a defined instruction, is not in a prohibited addressing mode, and does not cause a privileged instruction execution violation, the instruction decoding PLA
The output address of 2 is used as the address for control memory 4 (A7), but control memory 4 is set to address 'ooiox001.
10” (A8) The microinstruction is temporarily held in the microinstruction register 5 and issued to the execution unit of the processor, etc.
Regarding the execution unit and subsequent operations (tomo), the explanation is omitted as it is not directly related to this embodiment (B) Next, undefined instruction B (bit pattern n1101
01 0010 001010") is temporarily held in instruction register 1. Instruction decoding PL
Even if input to A2 (B2> instruction decoding PLA, 2, term 79
only selected Control Memory Address Field = 0000000010'' (79) Possible Addressing Mode Data Field = 0000' (-
) Specified addressing mode data field = 11
” (79) Valid data field = 0” Even if (-) is output, the selected term is clear from FIG. 8 (B3) Instruction decoding control circuit 8 G& Instruction decoding PLA
Assuming that the manual command in 2 is judged to be a valid command,
Therefore, even if all output fields of the instruction decoding PLA2 are valid (B4), the undefined instruction detection circuit 6 (friend)
Since the output valid data field = O and the instruction decoding control circuit 6 has determined that the input instruction of the instruction decoding PLA 2 is a valid instruction, the input instruction is determined to be an undefined instruction (B5) Prohibited. Addressing mode detection circuit 7 (undefined instruction detection circuit 6 on the bottom) Instruction decoding PL
Since the input command of A2 is judged to be an undefined command,
There is no need to check prohibited addressing mode and detect violations of privileged instruction execution (B6) On control memory address generation circuit 3ζ Undefined instruction detection circuit 6 has determined that the input instruction is an undefined instruction. In particular, the start address of the instruction exception handling routine"
1111110000" is used as the address for the control memory 4. However, in this embodiment, the undefined instruction exception is handled as one of the instruction exceptions (B7), but the control memory 4 is used as the address "1111110.
Microinstruction (instruction exception handling) 96 corresponding to “QOO”
(B8) The microinstruction is temporarily held in the microinstruction register 5 and issued to the execution unit of the processor. Therefore, the explanation will be omitted, but even if an instruction exception is detected when undefined instruction B is decoded (C), undefined instruction C (bit pattern "001
011 0101 001001")) (C1) is temporarily held in instruction register 1. Instruction decoding PL
Even if input to A2 (C2) is a term in instruction decoding PLA2? 1°74
, 75. 77, 79 are selected Control memory address field = 0010101110'' (74, 75, 77, 79) Possible addressing mode data field = ''0101
” (74, 77) Specified addressing mode data field = “11”
(79) Valid data field = l" (71) is output. Although the selected term is clear from FIG. Therefore, even if all output fields of instruction decoding PLA2 are valid (C4> undefined instruction detection circuit 6), instruction decoding PLA2
Since the output valid data field = 1 and the instruction decoding control circuit 6 judges that the input instruction of the instruction decoding PLA 2 is a valid instruction, the manual instruction is judged to be a defined instruction (C5) prohibited. Addressing mode detection circuit 71 - Possible addressing mode data field of instruction decoding PLA2 output = 0101, specified addressing mode data field of instruction decoding PLA2 output = 11, and undefined instruction detection circuit 6 cut Instructions Since the input command of the decoding PLA2 is determined to be a defined instruction, it can be determined that the prohibited addressing mode is not in use.In the list 60 of patterns for detecting the use of prohibited addressing modes, the item of prohibited addressing mode detection is "0". ``It is clearer than what is happening.

Also, since this instruction is not a privileged instruction, there is no need to detect privileged instruction execution violations (1 (C6> Control memory address generation circuit 3). The input instruction is a defined instruction and is not in prohibited addressing mode. , and since no privileged instruction execution violation has occurred, the output address of the instruction decoding PLA 2 is set to the control memory 4.
The control memory 4 generated as an address for (C7) is the address "oo1o1011
10" (branch instruction to instruction exception handling routine) 94 (C8) The microinstruction is temporarily held in the microinstruction register 5 and issued to the execution unit of the processor, etc. Regarding the subsequent instruction exception handling operation, the explanation is omitted as it is not directly related to this embodiment, but even if an instruction exception is detected when undefined instruction C is decoded (D), the fixed copy instruction D' POP $5 (Ino
n)” (bit pattern”101000 0001
010001"> will be explained below (D
l) Temporarily held in instruction register 1 Instruction decoding PLA2
(D2) In command decoding PLA2, the term 72°81.
84 is selected Control Memory Address Field 0100000111” (81,84) Possible Addressing Mode Data Field = 010
1” (84) Specified addressing mode data field = “lO’”
(81) Even if valid data field = ``1'' (72) is output, the selected term is clear from Figure 8 (D3> Instruction decoding control circuit 8 (upper instruction decoding PLA 2 input command is a valid instruction) Therefore, even if all the output fields of the instruction decoding PLA2 are valid (D4), the undefined instruction detection circuit 6 (the instruction decoding PLA2
Since the output valid data field = 1 and the instruction decoding control circuit 6 determines that the input instruction of the instruction decoding PLA 2 is a valid instruction, the input instruction is determined to be a fixed copy instruction (D5> Prohibited addressing). Possible addressing mode data field of instruction decoding PLA2 output on mode detection circuit 7ζ = o i o i, specified addressing mode data field of instruction decoding PLA2 output = 10, and undefined instruction detection circuit 6 Since the input command of PLA2 is determined to be a fixed copy instruction, it can be determined that the prohibited addressing mode is in use.In the list 60 of patterns for detecting the use of prohibited addressing modes, the term for prohibited addressing mode detection is lH. Also, since this instruction is not a privileged instruction, there is no need to detect a violation of privileged instruction execution. In addition, since it is a prohibited addressing mode, the start address of the instruction exception handling routine is
1111110000' is used as the address for the control memory 4. However, in this embodiment, the prohibited addressing mode occurrence exception is handled as one of the instruction exceptions (Dl).
The microinstruction (instruction exception handling) 96 corresponding to 00' is issued (D8), but the microinstruction is temporarily held in the microinstruction register 5, and is issued to the execution unit of the processor, etc. Regarding instruction exception handling operation ji Since it is not directly related to this embodiment, the explanation will be omitted, but even if an instruction exception (prohibited addressing mode exception) is detected when a fixed copy instruction with a prohibited addressing mode is decoded, (E) Continuation Explaining the operation of decoding privileged instruction E"LPSWR6n (hit pattern "101000 0010 000110") (El) temporarily held in instruction register 1. Instruction decoding PL
Even if it is input to A2 (C2), the term 72°79.
85 is selected Control Memory Address Field = 0100001010'' (79,85) Possible Addressing Mode Data Field = 111
1” (85) Specified addressing mode data field = 11”
(79) Valid data field = 1" (72) Even if the selected term is clear from FIG. 8 (B3) Instruction decoding control circuit 8c Instruction decoding PLA2
Assume that the input instruction is determined to be a valid instruction. Therefore, even if all output fields of instruction decoding PLA2 are valid (B4) undefined instruction detection circuit 6 (upper instruction decoding PLA2)
Since the output valid data field = 1 and the instruction decoding control circuit 6 judges that the input instruction of the instruction decoding PLA 2 is a valid instruction, the manual instruction is judged to be a defined instruction (B5) prohibited. Addressing mode detection circuit 7 Upper instruction decoding Possible addressing mode data field of PLA2 output = 1111, specified addressing mode data field of instruction decoding PLA2 output = 11, and undefined instruction detection circuit 6 Instruction decoding Since the input command of PLA2 is determined to be a defined command, it can be determined that the prohibited addressing mode is not present. Even if it's more obvious than it is
This instruction also detects privileged instruction execution violations from privileged instructions. Since the state of the processor managed by the instruction decoding control circuit 6 is a "non-privileged state," privileged instructions cannot be executed. (B6) Control memory address generation circuit 3 (friend) Since the input instruction is a defined instruction and a privileged instruction execution violation has been detected, the start address of the instruction exception handling routine is
1111110000" as the address for the control memory 4. However, in this embodiment, even though privileged instruction execution violation is handled as one of the instruction exceptions (B7), the control memory 4 is set to the address "1111110.
Microinstruction (instruction exception handling) 96 corresponding to “000”
(B8) Temporarily retains the microinstruction in the microinstruction register 5 and issues it to the execution unit of the processor, etc. Regarding the execution unit and subsequent instruction exception handling operations, note C. Not directly related to this embodiment. Therefore, the explanation will be omitted, but when the processor decodes the privileged instruction E when the processor is in the non-privileged state, an instruction exception (privileged instruction execution violation) is detected.As described above, according to this embodiment, (B) undefined copying of the instruction. By providing an instruction decoding PLA with a valid data field indicating the valid data field and an undefined instruction detection circuit that determines unspecified duplication of the decoding instruction from the valid data field, the following effects can be obtained (Bl) Multiple selection is used. Although the decoding method and the output data generation method can easily generate valid data fields and detect undefined instructions (B2), the instruction decoding PLA and control memory are the minimum required to decode defined instructions. By generating a valid data field using a part of the operation specification field of the instruction, which requires only a capacity of (t (B3)), the capacity of the instruction decoding PLA is reduced. (C) Instruction decoding PLA with valid data field, which makes it easier to modify instructions for addition and deletion.
and the undefined decoding instruction from the valid data field.
By simultaneously detecting undefined instructions using an undefined instruction detection circuit that determines fixed duplication, and using a control memory in which a branch microinstruction to an instruction exception handling routine is written for undefined instructions, Although the following effects can be obtained (CI), there is a general method of generating addresses in control memory for defined instructions with continuous bit patterns. Amo If only some of these patterns are undefined instructions ζ By detecting undefined instructions in the control memory, decoding becomes easier and the capacity can be reduced and microscopically improved by a small amount of control memory. Even more important is the reduction in the capacity of the instruction decoding PLA.Although the overall amount of hardware will decrease (
C2> Addition of instructions, etc. 4 friends In general, 1 above A nail that is often assigned to a pattern that is only partially undefined L For such additions L A branch instruction to an instruction exception handling routine already written in the control memory It can be handled simply by changing the original microinstruction, and does not involve changing the instruction decoding PLA.In this way, it is easy to respond to changes, and the increase in capacity due to changes can be handled with a minimum amount. Amata In general, changing the ROM is easier than changing the PLA, and it is easier to create hardware and perform medical verification. an instruction decoding PLA having a possible addressing mode field that is decoded and determined independently of the other fields; a designated addressing mode field that is determined by decoding the addressing mode of the instruction independently of other fields; a possible addressing mode field; A prohibited addressing mode detection circuit is provided to compare the addressing mode fields and detect a prohibited addressing mode. However, in the (DI) instruction decoding PLA, if a prohibited addressing mode is attempted to be detected by decoding the operation field and addressing mode in combination, the instruction decoding PLA becomes complicated and its capacity increases. In the instruction set used, when combinatorial decoding is performed, even a simple calculation using three types of addressing modes results in an increase of approximately three times. (D2) There are instructions that do not have an addressing mode, such as "CPSTRING" in this example. "No addressing mode" in the L Possible addressing mode data
(E) An addressing mode field that allows the operation field of an instruction to be decoded independently of other fields to indicate that it is a privileged or non-privileged instruction. An instruction decoding PLA that has an instruction decoding PLA and an instruction decoding control circuit that manages the state of the processor are installed. , even if the following effects are obtained (El) Instruction decoding and privileged instruction execution violations can be detected independently of instruction execution. Identification and instruction decoding PLA
Even though it can be changed easily in response to changes in the instruction specifications, it is recommended to use some patterns in the possible addressing mode field (C3), which can be used to detect prohibited addressing modes.Instruction decoding PLA capacity The increase is extremely small L%
(If unused patterns in the possible addressing mode field are used, the capacity of the instruction decoding PLA will not increase.) In reality, the number of possible addressing mode data patterns is limited to several types, and as the number of addressing modes increases, the number of patterns increases. does not increase exponentially (in this embodiment, l bits are provided for each addressing mode for simplicity).Also, in the instruction decoding PLA2, an l bit valid data field is provided. This is to speed up the detection of undefined instructions, and if the possible addressing mode data "oooo" is assigned to the undefined instruction (the previously assigned "o o o o'" will be changed), it will become independent. This can be easily achieved without providing a valid data field.

In addition, the number of privileged instructions is usually less than 10% of all instructions, and the types of possible addressing modes are limited. Therefore, in order to distinguish between privileged instructions and non-privileged instructions, the patterns of possible addressing mode data are set to 2. (In this embodiment, for simplicity, a bit representing a privileged instruction is provided orthogonal to the pattern of possible addressing mode data.) Therefore, the output field of the PLA has a realizable bit length. In this embodiment, the control memory etc. are ROM (R
ead 0nly Memory), an undefined instruction detection circuit, a prohibited addressing mode detection circuit, and
Although control memory address generation circuits can be realized with a small amount of combinational circuits, this is a great advantage considering that they can be easily realized in microprocessors and can be easily incorporated into microprogram control. As described in detail, according to the present invention, it is possible to obtain an instruction exception detection device in which the CL instruction decoding device is small and fast, the instruction decoding method is simple, and the instruction can be easily added and changed. The practical effect is significant (1

[Brief explanation of drawings]

FIG. 1 shows the configuration of an instruction exception detection device according to an embodiment of the present invention. FIG. 2 shows an explanation of the instruction format used in the embodiment. FIG. 3 shows an explanation of the instructions and bit patterns used in the embodiment. The figure shows an explanation of the addressing mode and bit pattern of the instruction used in the same embodiment. Figure 5 shows the instruction decoding used in the same embodiment. The explanation of the possible addressing mode fields output by the PLA is shown. Figure 6 shows the instruction decoding used in the same embodiment. An explanation of the addressing mode field specified in the command output by the PLA is shown in Fig. 7. An explanation of the prohibited addressing mode detection used in this embodiment is shown in Fig. 8. An explanation of the terms stored in the PLA is shown in Fig. 8. FIG. 9 shows the explanation of the microprogram stored in the control memory used in the same embodiment. FIG. 10 shows the configuration of the conventional instruction exception detection device. Generation floor plan 4... Control memo 180... Undefined instruction detection circuit 7... Prohibited addressing mode detection circuit
8...Command decoding control same area

Claims (2)

[Claims] (1) Multiple fields that specify the basic operation of the instruction,
In an instruction consisting of a plurality of fields specifying one incidental operation from among incidental operations that are incidental to and orthogonal to the basic operation, the field specifying the basic operation is decoded independently of other fields, and the If the bit pattern of the field specifying the basic operation is not defined as an instruction, the bit pattern of the field specifying the basic operation is defined as an instruction and has an accompanying operation. In this case, data indicating the ancillary operations permitted by the basic operation,
If the bit pattern of the field that specifies the basic operation is defined as a command and does not have an accompanying operation, outputs data indicating that the basic operation does not have an accompanying operation, and sets the field that specifies the accompanying operation to another. an instruction decoder that decodes data independently of the fields of the field and outputs data indicating a specified accompanying operation; and an instruction decoder that manages data indicating whether the instruction being decoded by the instruction decoder is valid or invalid. data output from the control means and the instruction decoding control means indicates that the instruction being decoded is valid; and data output from the instruction decoding means indicates that the instruction being decoded is an undefined instruction. If so, it is detected that the instruction is an undefined instruction, the data output from the instruction decoding control means indicates that the instruction being decoded is valid, and the data output from the instruction decoding means is If the instruction being decoded indicates that it is a defined instruction with accompanying actions, the data indicating the accompanying actions permitted by the basic action of the instruction and the data indicating the accompanying actions specified by the instruction indicate that the instruction is not permitted. If a combination of incidental operations that are not specified occurs, it is detected that the instruction is an undefined instruction, and the data output from the instruction decoding control means indicates that the instruction being decoded is valid, and the instruction is If the data output from the decoding means indicates that the instruction being decoded is a defined instruction without an accompanying action, it is detected that the instruction is a defined instruction regardless of the data indicating the specified accompanying action. An instruction exception detection device characterized by comprising an undefined instruction detection means for detecting an undefined instruction. (2) multiple fields that specify the basic operation of the instruction;
In an instruction consisting of a plurality of fields specifying one incidental operation from among incidental operations that are incidental to and orthogonal to the basic operation, the field specifying the basic operation is decoded independently of other fields, and the an instruction decoding means for generating data indicating the state of the processor in which the instruction is permitted to be executed; an instruction decoding control means for managing the state of the processor; Exception detection characterized by comprising an instruction execution violation detection means for determining whether execution of the instruction is currently permitted or disallowed from data indicating the state and the state of the processor outputted from the instruction decoding control means. Device (3) In an instruction consisting of a plurality of fields specifying a basic operation of the instruction and a plurality of fields specifying one incidental operation from among incidental operations that are incidental to and orthogonal to the basic operation, the basic operation The field that specifies the basic operation is decoded independently from other fields, and if the bit pattern of the field that specifies the basic operation is not defined as an instruction, data indicating that it is an undefined instruction is sent to the field that specifies the basic operation. If the bit pattern of the field that specifies the basic operation is defined as a command and has an accompanying operation, the bit pattern of the field that specifies the basic operation is defined as an instruction, and the data indicating the accompanying operation permitted by the basic operation is If the basic action does not have an accompanying action, data indicating that the basic action does not have an accompanying action is output, the field specifying the accompanying action is decoded independently of other fields, and the specified accompanying action is executed. an instruction decoding means for outputting data indicating whether the instruction being decoded by the instruction decoding means is valid or invalid; and an instruction decoding control means for managing data indicating whether the instruction being decoded by the instruction decoding means is valid or invalid; detecting that the instruction is an undefined instruction if the instruction being decoded indicates that the instruction is valid, and the data output from the instruction decoding means indicates that the instruction being decoded is an undefined instruction;
The data output from the instruction decoding control means indicates that the instruction being decoded is valid, and the data output from the instruction decoding means indicates that the instruction being decoded is a defined instruction having an accompanying action. If a combination of ancillary operations that are not permitted by the data indicating the incidental operations permitted by the basic operation of the instruction and the data indicating the incidental operations specified in the instruction occurs, the instruction is undefined. The data output from the instruction decoding control means indicates that the instruction being decoded is valid, and the data output from the instruction decoding means indicates that the instruction being decoded performs an accompanying operation. If the instruction is a defined instruction that does not have a specified instruction, an undefined instruction detection means that detects that it is a defined instruction regardless of the data indicating the specified accompanying operation, and a control memory that stores the microprogram. the undefined instruction detection means detects an undefined instruction from data output from the instruction decoding means and data output from the instruction decoding control means indicating that the instruction is valid; The instruction is decoded by the decoding means, and it is determined that the instruction is a defined instruction, and an undefined instruction processing microroutine stored in the control memory is activated from the address output by the instruction decoding means. An instruction exception detection device characterized by detecting defined instructions.