KR0135927B1 - Access apparatus of main memory for multiprocessor system - Google Patents

Abstract

The present invention relates to a multiprocessor system in which a plurality of processors (CPUs) are connected to main memory via a bus. A bus matching unit connected to the CPU to perform a main memory access operation through the system bus, and a predetermined number of memory access cycles connected to the control bus and the address bus to read and input address and control information. A memory controller for generating a control signal of the memory; and a register connected to the central processing unit through the data bus to store or output data according to a control signal of the memory controller; and a data stored in the register and the data bus. Being entered through In the multiprocessor system, a main memory access device using a data buffer is provided when performing an atomic instruction in a multiprocessor system.

Description

Main Memory Access Device Using Data Buffer When Performing Atomic Instruction in Multiprocessor System

1 is an exemplary configuration diagram of a multiprocessor system configured to access a main memory using a data buffer when performing an atomic instruction according to the present invention.

2 is a flow chart of the process of performing atomic instructions in the multiprocessor system shown in FIG.

* Explanation of symbols for main parts of the drawings

SB: System Bus 100A to N: Processor Board

200: main memory 10: central processing unit

20: bus matching unit 30: memory control unit

41: Register 42: Comparators

The present invention relates to a multiprocessor system in which a plurality of processors (CPUs) are connected to main memory via a bus. In particular, the system efficiency of accessing main memory for execution of atomic instructions in each processor connected to the bus is improved. A main memory access device using a data buffer to increase.

In general, a multi-processor system such as Pentium, which is gaining popularity recently, provides atomic instructions to support synchronization of individual processors. When each processor executes an atomic instruction, it reads and writes to the same memory address. The cycle occurs continuously.

In addition, during the execution of this instruction, the processor drives the lock signal LOOK # so that read and write cycles are performed exclusively on other processors.

Logic outside the processor senses the lock signal and performs exclusive read and write access to another processor for a given address.

For example, Intel Pentium's XCHG (Excahnge) is a method that operates as described above. For more information about the Pentium processor and atomic instructions, see Pentium Processor User's Manual Vol. See I.

Hereinafter, data accessed while performing an atomic instruction of a processor is called atomic data.

In addition, multiprocessor architectures using buses have a significant effect on bus performance.

In order to solve this problem, cache memory is generally used. The cache memory is located in close proximity to the data of the main memory, which not only provides the processor with the desired data quickly but also reduces the bus utilization rate.

The function and operation of the Pentium to which the cache memory (I82496 / I82491) is applied are described in Pentium Processor User's Manual Vol. Ⅰ, Pentium Processor User's Manual Vol. Ⅱ, Pentium Processor User's Manual Vol. Ⅰ, Pentium Processor User's Manual Vol. Explained in III.

Briefly, the content of the data is that the atomic data must be accessed exclusively in multiple processors, and therefore requires the help of hardware logic located outside the processor.

This logic allows one to perform arbitration by arbitrating access requests for atomic data, which are performed independently by a plurality of processors.

When a processor drives a lock signal and accesses data, it considers it as atomic data and accesses the bus to inform other processors of the atomic data access.

Unlike general data for this operation, atomic data has limited use of cache memory.

In addition, the Intel Pentium processor drives a lock signal on accessing the atomic data, and the cache memory receives this signal to prevent the atomic data from being read or stored in the cache memory.

In other words, atomic data flows directly between the processor and main memory without going through the cache.

Therefore, the atomic instruction input / output scheme generally used for synchronization among a plurality of processors has a high possibility that several processors are accessed by atomic data at the same time, which temporarily increases bus utilization and adversely affects system performance. .

An object of the present invention to solve the above problems is to provide a data buffer between each processor and the bus and to store the atomic data using the data buffer to execute the atomic instructions so that each processor accesses the atomic data. To provide a main memory access device using a data buffer when performing atomic instructions in a multiprocessor system to prevent the increase in bus utilization caused by accessing the main memory unnecessarily frequently.

In order to achieve the above object, a feature of the present invention is that a plurality of processor boards are connected to the system bus to access the main memory for data communication with the main memory connected to the system bus. In the multi-processor system, each processor board is connected to the central processing unit to perform a unique function, an address bus, a data bus, and a control bus to perform a main memory access operation through the system bus. A bus matching unit, a memory control unit connected to the control bus and the address bus to read an input address and control information to generate a predetermined number of control signals for controlling a memory access cycle, and the central processing unit through the data bus. Connected with the memory And a comparator for storing or outputting data according to a control signal of the controller, and a comparator for comparing the data stored in the register with data input through the data bus and inputting the data to the memory controller.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a diagram illustrating a configuration of a multiprocessor system configured to access a main memory using a data buffer when performing an atomic instruction according to the present invention, and with a main memory 200 connected to a system bus SB. A plurality of processor boards 100A to N are connected to the system bus SB for data communication.

Each of the processor boards 100A to N includes a central processing unit 10 for performing a unique function for each board, the central processing unit 10, an address bus AB, and a data bus DB. And a bus matching unit 20 connected to a control bus CB to perform a main memory access operation through the system bus SB, a control bus CB and an address bus AB of the CPU 10. Is connected to the memory control unit 30 and the data bus DB of the CPU 10 to generate a predetermined number of control signals for controlling a memory access cycle by decoding the address and control information. And a comparator 42 for comparing the data stored in the register 41 and the data input through the data bus DB.

The register 41 and the comparator 42 are referred to as a data buffer.

Brief description of the operating characteristics of the above configuration as follows.

The memory controller 30 drives the input control signal ICS of the register 41 to be true in the read cycle of the atomic data so that the value of the data bus DB is input to the register 41 and stored. By actually driving the output control signal OCS in the write cycle of data, the contents stored in the register 41 are outputted.

In addition, the comparator 42 compares the data I1 inputted from the register 41 with the data I2 inputted through the data bus DB and outputs a comparison value.

At this time, the memory controller 20 receives the output signal of the comparator 42 in the write cycle of the atomic data of the central processing unit 10 and controls the write cycle of the central processing unit 10.

In addition, the main memory 200 receives information such as an address required for memory access through the bus 3 from an arbitrary processor board 100, and responds to data through the system bus SB when the memory read access is completed.

When the CPU 10 requests access of the main memory 200, the memory controller 30 inputs a control signal to the bus matching unit 20, and accordingly, the bus matching unit 20 accesses the bus. When the control is finished, the control signal is input to the memory controller 30 to notify that the access operation of the main memory 200 is completed through the control bus CB of the CPU 10.

A detailed operation example of the multiprocessor system according to the present invention configured as described above will be described in detail with reference to FIG. 2.

FIG. 2 is a flowchart of the process of performing atomic instructions in the multiprocessor system shown in FIG.

When the memory control unit 30 receives the request signal for the atomic data access from the central processing unit 10 in step S101, the memory control unit 30 proceeds to step S102 to determine whether the request signal according to the atomic access received in the step S101 is read or write. Determine.

If it is determined in step S102 that the read is made, the flow advances to step S103 to perform a memory read.

In this case, if the address is an area of the main memory 200, a control signal is input to the bus matching unit 20 to access the system bus SB. Accordingly, the bus matching unit 20 receives the memory when the bus access is completed. The control signal is input to the controller 30 to notify that the access operation of the main memory 200 is completed through the control bus CB of the CPU 10. Thereafter, as the main memory is accessed in step S103, the data bus DB is driven to supply the read data to the CPU 10. FIG.

At this time, the memory control unit 30 drives the input control signal of the register 41 to 'true' in step S104, and the data input to the CPU 10 via the data bus DB is stored in the register. Store in (41).

Thereafter, when data input to the central processing unit 10 is completed, the flow proceeds to step S105 to end the read cycle and abandon the system bus SB.

If it is determined in step S102 that it is a write cycle, the process proceeds to step S106, in which step S106 is used to compare the data stored in the register 41 with the data output from the central processing unit 10 during the read cycle operation. Comparator 42 is used and the output of comparator 42 is checked.

In step S107, it is determined whether the output signal of the comparator 42 examined in step S106 is the same or different. At this time, if it is determined in step S107 that the comparison signal value is true (equal), the flow advances to step S109 to end the write cycle.

If the comparison signal value is false (different) in step S107, the flow advances to step S108.

In step S108, memory write is performed, and if the address is a main memory area, write access to the memory is performed through the system bus.

Briefly describing the above operation, in order to prevent the processor from increasing the bus utilization rate by accessing the atomic data, a data buffer is stored between the processor and the bus, and then the atomic data is stored and compared to prevent unnecessary performance. As an atomic instruction, the processor continuously reads and writes to a given address.

At this time, the data read from the memory in the read cycle of the atomic data is stored in the data buffer.

In the write cycle of atomic data, the data output from the processor is compared with the contents of the buffer.

If the comparison shows the same content, the write cycle ends without accessing the bus and main memory.

On the other hand, if the comparisons are not the same, write cycles are sent to the main memory via the bus.

That is, the data buffer of the present invention can be used to prevent unnecessary data writes from accessing the bus and memory.

In the multiprocessor system operating as described above, a main memory access device using a data buffer is provided when performing an atomic instruction to store the data buffer between the processor and the bus, and then compare and store the atomic data to perform unnecessary operations. In addition, the present invention can be used in a computer system using only one processor, can be used even without using Intel Pentium as a processor, and can be applied with or without cache memory between the processor and the bus. can do.

To be more precise, it is possible to distinguish atomic data access from outside the processor and to apply it to any computer system using a processor that continuously reads and writes atomic data.

Claims (3)

In a multiprocessor system in which a plurality of processor boards are connected to the system bus to access the main memory for data communication with main memory connected to a system bus, each processor board has a unique function. A central processing unit for performing; A bus matching unit connected to the CPU through an address bus, a data bus, and a control bus to perform a main memory access operation through the system bus; A memory control unit connected to the control bus and the address bus and generating a predetermined number of control signals for decrypting an input address and control information to control a memory access cycle; A register connected to the central processing unit through the data bus to store or output data according to a control signal of the memory controller; And a comparator for comparing the data stored in the register with the data input through the data bus and inputting the data to the memory control unit. . The method of claim 1, wherein the memory controller transfers an input control signal to the register in a read cycle of atomic data so that a value of the data bus is input to and stored in the register, and transmits an output control signal in a write cycle of atomic data. Main memory access device using a data buffer when performing an atomic instruction in a multiprocessor system, characterized in that the contents stored in the register (41) to be output. The memory controller of claim 1, wherein the memory controller examines an output signal of the comparator and stores data output from the CPU in a write cycle of atomic data and data stored in the register in a read cycle of atomic data. In the same case, the main memory access device using a data buffer when performing an atomic instruction in a multiprocessor system, characterized in that for stopping the write operation requested from the central processing unit.