JPH03220683A - Microcomputer - Google Patents

Abstract

PURPOSE:To reduce a chip size in the case of integration by connecting the outputs of plural data pointers to a second address bus, connecting the input/ output parts of respective data processing parts to a second data bus and reducing the number of first and second gate circuits and memories to one respectively. CONSTITUTION:A first data processing part 6a controls a first data pointer 5a by a first control line 11a and the output of the first data pointer 5a is inputted through a second data bus 7 to the address input of a memory 4. The input/output of the memory 4 is connected through a second data bus 8 to the input/output part of the first data processing part 6a and data is transferred between the first data processing part 6a and the memory 4. Similarly, the second-(n)th data processing parts execute the transfer of the data through a second address bus 2 and a second data bus 3 with the memory 4 and execute data processings. Thus, in the case of integration, the clip size can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer having a plurality of data processing sections.

[Conventional technology]

FIG. 2 is a block diagram showing the configuration of a conventional microcomputer having a plurality of data processing units. In the figure, 1 is a CPU, 2 is a first address bus connected to the program counter of the CPU 4a is a first memory;
4n is the nth memory, 5a is the first data pointer, 5
n is the n-th data pointer, 6a is the first data processing section, 6n is the n-th data processing section, 9a selects the output of the address bus 2 and the first data pointer 5a,
A first
An n-th gate circuit 9n selects the output of the address bus 2 and the n-th data pointer 5n, and transmits the selected output to the address input of the n-th memory 4n.
0a is the data output of the first memory 4a.
A first gate circuit, Ion, selects and transmits data to the data bus 3 and the input/output of the first data processing section 6.
The data input/output of the memory 4n is connected to the first data bus 3.
An n-th gate circuit 11a selects and transmits data to the input/output of the n-th data processing section 6n, and 11a is the first data processing section 6.
A is a first control signal line for controlling the first data pointer 5a, and lln is an n-th signal line for controlling the n-th data pointer 5n by the n-th data processing section 6n.

Next, the operation will be explained.

The CPU designates an address in the first memory using the first address bus 2, outputs data to the first data bus 3, and writes data to the first memory 4a.

At this time, it is assumed that address bus 2 and data bus 3 are selected for gate circuits 9a and 10a, respectively. Similarly, data is written to the second and subsequent n-th memories 4n. Next, gate circuits 9a and 10a each input data pointer 5.
a and the data processing unit 6a, the first data processing unit 6a controls the first data pointer 5a via the first control line 11a, accesses the first memory 4a,
Perform data processing. Similarly, the second and subsequent n-th data processing units 6n each individually process data.

[Problem to be solved by the invention]

Since conventional microcomputers are configured as described above, they require as many gate circuits as the number of data processing sections, and when incorporated into an integrated circuit, there are problems such as an increase in chip size.

This invention was made to solve the above-mentioned problems, and its purpose is to obtain a microcomputer with a small chip size when integrated.

[Means to solve the problem]

The microcomputer according to the present invention connects the output of each data pointer to the second address bus, and
The input/output section of each data processing section is connected to the second data bus, and each gate circuit and memory are integrated into one.

[Effect]

In the microcomputer according to the present invention, the data of each data pointer is output onto the second address bus, and the data of the memory is accessed to each data processing unit via the second data bus.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is a CPU, 2 is a first address bus connected to the program counter of this CPU 1, 3 is a first data bus connected to the data input/output section of the CPUI, 4 is a memory, and 5a is the first data pointer, 5
n is an n-th data pointer, 6a is a first data processing section, 6n is an n-th data processing section, and 7 is a second data pointer to which the outputs of the first data pointer 5a to n-th data pointer 5n are connected. 8 is a second data bus connected to the data input/output section from the first data processing section 6a to the nth data processing section 6n, and 9 is the address bus connected to the first address bus 2 and the above. A first gate circuit 10 selects the second address bus 7 and transmits it to the address input of the memory 4; a second gate circuit that selects and transmits a signal to a second gate circuit;
lln is an n-th control signal by which the n-th data processing unit 6n controls the n-th data pointer 5n.

Next, the operation will be explained.

The CPU designates a certain address in the memory 4 via the first address bus 2, outputs data to the first data bus 3, and writes the data into the memory 4. At this time, it is assumed that gate circuits 9 and 10 select first address bus 2 and first data bus 3, respectively. Next, the first. Second gate circuit 9
．． 10 selects the second address bus 7 and the second data bus 8, respectively, the first data processing section 6a selects the second address bus 7 and the second data bus 8, respectively.
The first data pointer 5a is controlled by the control line 11a, and the output of the first data pointer 5a is outputted to the address input of the memory 4 via the second data bus 7. The input/output of the memory 4 is connected to the input/output section of the first data processing section 6a via the second data bus 8, and data is transferred between the first data processing section 6a and the memory 4. Similarly, the second and subsequent n-th data processing units also use the second address bus 2.
Data is transferred to and from the memory 4 via the second data bus 3, and data processing is performed.

In the above embodiment, a read/write memory is provided as the memory, but this memory may be a read-only memory.

〔Effect of the invention〕

As described above, according to the present invention, the outputs of a plurality of data pointers are connected to the second address bus, the input/output sections of each data processing section are connected to the second data bus, and the outputs of the plurality of data pointers are connected to the second data bus. Since the second gate circuit and the memory are each made into one, the chip size becomes smaller when integrated, which has the effect of making the device cheaper.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a microcombination system according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional microcomputer. 1 is a CPU, 2 is a first address bus, 3 is a first data bus, 4 is a memory, 5 is a data pointer, 6 is a data processing unit, 7 is a second address bus, 8 is a second data bus , 9 is the first gate circuit, IO is the second gate circuit,
11 is a control signal. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) at least two data processing units, at least two data pointers, a first address bus connected to a program counter of the CPU, a second address bus connected to the output of the data pointer, and a CPU. a first data bus connected to the data input/output section of the data processing section; a second data bus connected to the input/output section of the data processing section; a memory; and the first address bus and the second address bus. a first gate circuit that selects a data bus and transmits the data to the address input of the memory; and a second gate circuit that selects and outputs data output of the memory to the first data bus and the second data bus. A microcomputer equipped with a gate circuit.