JPH0635801A - Hierarchical memory control system - Google Patents

Abstract

PURPOSE:To increase the capacity of the buffer storages while suppressing the increase of the hardware quantity and also controlling these buffer storages in a store-in system in regard of a hierarchical memory control system which applies a hierarchical memory including a buffer storage of a CPU, the intermediate buffer storage of a storage controller, and a main storage. CONSTITUTION:A buffer storage 2 uses the combination of an intra-page real address and the low order part of a logical address as a line address. At the same time, a tag means 7 of an intermediate buffer storage 5 controls the real address and the low order part of the logical address designated by a CPU 1. Meanwhile a storage controller 4 contains a mapping tag means 8 which controls the copy of the tag means of the storage 2 in addition to the means 7 of the storage 5. In such a constitution, the coincidence of data secured between both storages 2 and 5 is controlled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an intermediate buffer having a relatively large capacity between a plurality of central processing units having a buffer storage unit and one or a plurality of main storage units shared by the central processing units. Regarding a hierarchical memory control method in a data processing system having a configuration including a storage device, in particular,
The present invention relates to a hierarchical memory control method for increasing the capacity of a buffer storage device while suppressing an increase in the amount of hardware, and for controlling these storage devices by a store-in method.

[0002]

2. Description of the Related Art In a large-scale computer system, the performance of a single processor and the system performance of a multiprocessor have been improved.

CP is a method for improving the performance of a single processor.
The main focus is on improving pipeline technology in U and increasing cache capacity. Usually, the cache is configured by a set associative method in which a plurality of ways and one way is made up of a plurality of entries. To increase the capacity of the set associative cache, the number of ways or the number of entries must be increased.

Conventionally, a method of increasing the capacity of the cache by increasing the number of ways has been adopted. This is for the following reason. In the computer system using the virtual memory system, the addresses 1 to 31 generated as an instruction address or an operand address are treated as a logical address. This logical address is
It is converted to a real address according to the following procedure. That is,
As shown in FIG. 15, the segment table origin address represented by bits 1 to 19 of the control register is added to the segment index (bit 1) of the logical address.
~ Bit 11) is multiplied by 4 to create the desired segment table address, and the page table origin address (bit 1 to bit 25) managed by the segment table pointed to by the segment table address is created.
To the page index (bit 11 to bit 19) of the logical address multiplied by 4 to create a desired page table address, and the page frame real address (bit 1) managed by the page table pointed to by the page table address is created. ~ Bit 19) and the byte address represented by bits 20 to 31 of the logical address are concatenated to convert to a real address.

In a computer using such an address translation process, the real address associated with bits 1 to 19 of the logical address cannot be used for accessing the buffer storage without waiting for the address translation. from now on,
In the conventional computer system, the cache entry is accessed by bits 20 to 31 where the logical address and the real address are equal.

However, if the cache entry is accessed by using the bit in which the logical address and the real address are equal, 1 of the cache is naturally used.
Way capacity will be limited. For example, if the block size of an entry is 64 bytes, the number of entries will be 64 entries defined by 6 bits from bit 20 to bit 25, and the capacity for one way of the cache will be "64 entries x 64 bytes". It will be 4K bytes.

Conventionally, therefore, when the cache capacity is insufficient, a method has been adopted in which the cache capacity is increased by increasing the number of ways of the cache.

On the other hand, in order to improve the system performance by the multiprocessor, it is considered that the memory access time is shortened and the memory throughput is improved. Therefore, between the cache of the CPU and the main storage device. The method of placing a medium-speed / large-capacity intermediate buffer storage device is being adopted.

In the conventional data processing system, when such an intermediate buffer storage device is provided, when the cache is rewritten, the corresponding main storage data in the main storage device is also rewritten to use the store-through method. This is because if previous data processing systems do not have such intermediate buffer storage,
The reason is that the through method is adopted.

However, when the multi-processor configuration is adopted and the store-through method is adopted, the frequency of memory access for store processing increases and the system performance deteriorates. Thus, in recent data processing systems, the main storage device is not rewritten at the time of rewriting the cache of the CPU, and when the entry is returned to the main storage device, the rewritten main storage data is reflected in the main storage device. In many cases, the store-in method of letting it go is adopted.

[0011]

However, by increasing the number of cache ways as in the prior art,
If the method of increasing the capacity of the cache is adopted, the amount of hardware such as a comparator prepared for the way will increase accordingly. From this point of view, according to the prior art, there is a problem in that the capacity of the cache cannot be increased to a desired value in terms of practicality.

When a store-through method is used when an intermediate buffer device is provided between a cache and a main storage device when a multiprocessor configuration is adopted as in the prior art, the store processing is performed. However, there is a problem that the system performance cannot be sufficiently improved due to the increase in the memory access frequency.

Moreover, the intermediate buffer storage device of the prior art has a structure in which the block size of the entry is the same as the block size of the entry of the cache, and the capacity of the intermediate buffer storage device is also small. However, even if the store-through method is sufficiently supported, the control processing when the block size of the intermediate buffer storage device is made larger than that of the cache and the capacity is made larger No
Furthermore, the current situation is that no store-in method has been proposed.

In consideration of the current state of the prior art when such an intermediate buffer storage device is provided, the present applicant has previously filed Japanese Patent Application No. 3-186712 (Title of Invention: Hierarchical Memory Control System). , The intermediate buffer memory stores a bit indicating whether the entry is valid or invalid, a bit indicating whether the block of the entry is exclusively accessed by one central processing unit, and each block of the entry. A bit that indicates whether it has been modified since it was transferred from main storage, and a bit that indicates in which buffer storage a copy of the block for the entry exists.
The invention has been disclosed in which a tag that manages an address portion that displays a main memory address is provided, and that this tag is used to execute control of store-in type buffer storage.

According to the invention disclosed by the applicant of the present invention, it is possible to improve the system performance because the buffer storage can be controlled by the store-in method even when the intermediate buffer storage device is provided. Become. However, the present invention also has a problem that the hardware amount of the tag increases as the number of entries in the intermediate buffer storage device increases.

The present invention has been made in view of the above circumstances, and is provided between a plurality of central processing units having a buffer storage unit and one or a plurality of main storage units shared by the central processing units. In a data processing system equipped with a relatively large capacity store-in type intermediate buffer storage device, the capacity of the buffer storage device is increased while suppressing an increase in the amount of hardware, and the control of these storage devices is performed. It is intended to provide a new hierarchical memory control method realized by the store-in method.

[0017]

FIG. 1 shows the principle configuration of the present invention. In the figure, 1 is a plurality of central processing units provided with a buffer storage unit 3, 3 is one or a plurality of main storage units shared by the central processing unit 1, 4 is a storage control unit that controls the main storage unit 3, and 5 is a storage control unit. This is a relatively large capacity intermediate buffer storage device provided in the storage control device 4.

In the buffer storage device 2 of the present invention, the conventional buffer storage device uses the in-page real address of the logical address as the line address, whereas the in-page real address and the lower part of the logical address are combined. Is used as a line address. For example, bits 18 to 25 of the logical address are used as the line address. According to this configuration, if explained in this example, the number of entries of the buffer storage device 2 is 64 entries in the conventional case, whereas it is 25 entries.
By increasing the number of entries to 6, it is possible to increase the capacity of the buffer storage device 2 while suppressing an increase in the amount of hardware.

Reference numeral 6 denotes a data management means provided in the intermediate buffer storage device 5, which temporarily manages main storage data, and 7 denotes tag means provided in the intermediate buffer storage device 5, which is a part of the data management means 6. It manages the real address that points to the main memory address of the main memory data to be managed.

As can be seen from the address translation process of FIG. 15, each central processing unit 1 can map bits 1 to 19 of the logical address to bits 1 to 19 of the real address in any combination. From this, as described above, if the buffer storage device 2 uses a line address that digs into the lower part of the logical address, the same or another central processing unit 1 uses the same main memory data as another logical address. It is possible to bring it in (copy it). If this happens, the main memory data brought in will be rewritten by each other, and the consistency cannot be guaranteed.

In order to deal with this inconvenience, the central processing unit 1 of the present invention, when requesting data from the intermediate buffer storage device 5, is used for accessing the buffer storage device 2 in addition to the real address of the request display. The tag means 7 of the present invention adopts a configuration for designating the lower part of the logical address.
In addition to managing the real address that points to the main memory address,
The configuration is such that the lower part of the logical address designated by the central processing unit 1 that has brought in the main memory data is managed.

Reference numeral 8 denotes a mapping tag means included in the storage control device 4, which manages a copy of the management data of the tag means included in the buffer storage device 2. Buffer storage device 2
The tag means of has a valid bit that indicates whether the main memory data that was brought in is valid or invalid, a MODIFY bit that indicates whether or not the contents of the main memory data that was brought in has been changed, and the main memory data of which address has been brought in. However, the mapping tag means 8 does not need to manage all the copies, but at least manages the valid bits and the real address bits.

The mapping tag means 8 has a structure in which the buffer storage device 2 carries out the line address of the combination of the in-page real address and the lower part of the logical address, so that the in-page real address and the logic read from the tag means 7 are taken. It will be searched using the combination with the lower address part.

By providing the mapping tag means 8, it is possible to specify which buffer storage device 2 the main storage data managed by the data management means 6 of the intermediate buffer storage device 5 is brought into. When the central processing unit 1 of the present invention requests data from the intermediate buffer storage device 5 in order to enable the updating process of the mapping tag means 8, as described above, the real address of the request display and the buffer storage device are used. In addition to specifying the lower part of the logical address used for the second access, the way number of the buffer storage device 2 as the storage destination of the request data is further specified.

Reference numeral 9 denotes a buffer control means provided in the intermediate buffer storage device 5, which refers to the management data of the tag means 7 / mapping tag means 8 and refers to the main storage data managed by the data management means 6 and the buffer storage device. The control process for the main memory data managed by the second control unit 2 is executed.

[0026]

According to the present invention, since the data required by the central processing unit 1 is not stored in the buffer storage device 2 of the central processing unit 1, the actual address of the request display and the buffer storage device 2 are sent to the buffer control means 9. When the data transfer request is issued by designating the lower part of the logical address used for the access and the way number of the buffer storage device 2 as the storage destination of the requested data, the buffer control means 9 firstly By referring to the management data of the tag means 7, whether or not the request data is stored in the data management means 6 and the lower part of the logical address stored in association with the data are from the central processing unit 1. Search for a match with what was sent.

By this search processing, when the requested data is stored in the data management means 6, but when it is determined that the lower part of the logical address does not match, the buffer control means 9 next guarantees the matching of the data. In order to do so, the mapping tag means 8 is searched by using the lower logical address portion read from the tag means 7 to determine which central processing unit 1 the requested data is brought into.

Subsequently, the buffer control means 9 moves out the requested data to the specified central processing unit 1 of the carry-in destination (data transfer of a form in which the data of the transfer source is treated as invalid). ) Is issued and the move-out is completed, the lower logical address portion associated with the request data managed by the tag means 7 is updated to the lower logical address portion sent from the requesting central processing unit 1.

Next, the buffer control means 9 transfers the requested data to the requesting central processing unit 1 and also sends the way number (that data is stored therein) sent from the requesting central processing unit 1. The management data of the mapping tag means 8 is updated according to the way number of the buffer storage device 2).

As described above, in the present invention, when the hierarchical memory structure of three layers of the buffer memory device 2, the intermediate buffer memory device 5, and the main memory device 3 is adopted, the page address is used as the line address of the buffer memory device 2. The number of entries is increased by using the combination of the internal address and the lower part of the logical address, and the configuration that resolves the data consistency that occurs by adopting this configuration increases the amount of hardware. It is possible to increase the capacity of the buffer storage device 2 while suppressing the above.

In the present invention, when adopting this three-level hierarchical memory configuration, a configuration is provided in which a copy of the tag of the buffer storage device 2 is provided in the storage control device 4, and the request is made in accordance with this mapped tag. The configuration is used to specify which central processing unit 1 the data is brought into.

In order to perform buffer control of the three-level hierarchical memory configuration by the store-in method, it is specified which central processing unit 1 buffer storage unit 2 the data of the intermediate buffer storage unit 5 is brought into. Then, the central processing unit 1 of the specified destination is requested to perform a process of instructing invalidation of data or instructing moveout.
In the present invention, at the time of adopting this three-level hierarchical memory configuration, a configuration is provided in which a copy of the tag of the buffer storage device 2 is provided in the storage control device 4, and the central portion of the request data is determined according to this mapped tag. By adopting a configuration that specifies whether or not it is brought into the processing device 1, a store-in type buffer control configuration can be constructed.

As described above, according to the present invention, since the increase in the amount of hardware required for implementing the store-in type buffer control is not affected by the number of entries in the intermediate buffer storage device 5, the number of entries in the intermediate buffer storage device 5 is increased. Even when the number increases, the store-in type buffer control can be realized while suppressing the increase in the amount of hardware.

[0034]

EXAMPLES The present invention will be described in detail below with reference to examples. FIG. 2 illustrates an example of a system configuration of a data processing system implementing the present invention. In the figure, as described in FIG. 1, 1 is a central processing unit (CPU), 2 is a buffer storage unit (LBS), 3 is a main storage unit (MSU), 4 is a storage control unit (MCU), and 5 is an intermediate unit. A buffer storage device (GBS). Reference numeral 11 denotes a channel processing unit (CHP) that shares the intermediate buffer storage unit 5 with the central processing unit 1.

In this embodiment, four central processing units 1 having a buffer storage unit 2 are provided, these central processing units 1 share the intermediate buffer storage unit 5 provided in the storage control unit 4, and , This storage controller 4 is
One connected to the main storage device 3 is disclosed.

FIG. 3 shows an example of the memory configuration of the buffer storage device 2, and FIG. 4 shows an example of the memory configuration of the intermediate buffer storage device 5. As shown in FIG. 3, the buffer storage device 2 has, for example, a block size of 64 bytes, and bits 18 to 25 of the logical address (as described above, the bits 20 to 25 are the same as the real address). Is a line address, one associative level has 256 entries and has a capacity of 16 KB, and eight associative levels have a total of 128 KB.
It has a capacity of. The entries of the buffer storage device 2 are evicted to the intermediate buffer storage device 5 from the one with the lowest reference frequency according to, for example, the LRU method.

On the other hand, as shown in FIG. 4, the intermediate buffer storage device 5 has, for example, a block size of 256 bytes and one associative level having 16K entries, thereby having a capacity of 4 MB and four associative levels. It has a total capacity of 16 MB. The entries of the intermediate buffer storage device 5 are evicted to the main storage device 3 from the one with the lowest reference frequency according to, for example, the LRU method.

As described above, according to the present invention, the number of entries in the intermediate buffer storage device 5 is reduced and the hardware amount required for the tag configuration is reduced in response to the large capacity of the intermediate buffer storage device 5. In order to reduce the size, the block size of the intermediate buffer storage device 5 is set to four times the block size of the buffer storage device 2.
By adopting this configuration, it is possible to reduce the data transfer amount between the intermediate buffer storage device 5 and the main storage device 3.

FIG. 5 shows an embodiment of a tag provided for managing the entries of the buffer storage device 2, and FIG. 6 shows a tag provided for managing the entries of the intermediate buffer storage device 5. 1 illustrates an example of a configuration. The tag of the intermediate buffer storage device 5 is expanded to the storage control device 4, but as described with reference to FIG. 1, the storage control device 4 of the present invention further includes a buffer storage device in addition to this tag. A configuration for developing a copy of the tag of the device 2 will be adopted. FIG. 7 illustrates an embodiment of the configuration of the tag copy of the buffer storage device 2.

There is one entry corresponding to a block of 64 bytes in the buffer storage device 2. In order to manage this entry, the tag of the buffer storage device 2 is shown in FIG.
VAL to display the valid / invalid of the entry, as shown in
MODIFY indicating the ID bit (V) and whether or not the content has been changed after the data transfer from the storage controller 4.
It is configured to manage the bit (M) and the real address bits (B1 to B19) that indicate which block of the address of the main storage device 3 stores the copy. Here, when the MODIFY bit indicates the changed state, when the block is replaced, the block needs to be moved out to the storage controller 4.

On the other hand, there is one entry corresponding to a block of 256 bytes in the intermediate buffer storage device 5, and in order to manage this entry, the tag of the intermediate buffer storage device 5 is an entry as shown in FIG. VALID bit (V) that indicates whether the entry is valid or invalid, an EXCLUDE bit (E) that indicates whether or not one central processing unit 1 exclusively uses the entry, and data from the main storage device 3. Check whether the contents have been changed after transfer 6
Four MODIFY bits (M) displayed in 4-byte units and a real address bit (B indicating which block of the address of the main storage device 3 is stored)
1 to B9) and the logical address lower-order bits (L18, L18, which indicate the bit value of the logical address bits 18, 19 issued by the central processing unit 1 which brought in the block of the entry.
L19) is managed. In addition, in this embodiment, a configuration is disclosed in which only one set of logical address lower-order bits (L18, L19) is managed for a plurality of central processing units 1, but a configuration in which each central processing unit 1 is managed is disclosed. It is also possible to collect.

Here, when the M bit indicates the changed state, when the block is replaced with the main memory device 3, the changed contents are reflected in the main memory device 3, so that the block is changed. The moveout to the main storage device 3 is required. Further, when the E bit indicates acquisition of exclusion, the rewriting process by the central processing unit 1 is performed on the block whose data is transferred to the buffer storage device 2, so that the latest changed block is Corresponding to being stored in the buffer storage device 2, when a block transfer request issued by the central processing unit 1 is requested to move out the block copied to the buffer storage device 2 to the intermediate buffer storage device 5. In addition, when the block is replaced with the main storage device 3, it is required to move out the block copied in the buffer storage device 2 to the main storage device 3.

On the other hand, the copy of the tag of the buffer storage device 2 shown in FIG. 7 shows at a high speed which buffer storage device 2 of the central processing unit 1 the main storage data managed by the intermediate buffer storage device 5 is brought into. It is prepared in order to be searchable, and as shown in FIG. 7, it is prepared corresponding to the tags of the buffer storage device 2, and each buffer storage device 2
Is configured to manage the VALID bit (V) of the tag and the real address bit (B1 to B19). Here, the MODIFY bit (M) may also be managed. In the following, a copy of the tag of the buffer storage device 2 included in the storage control device 4 will be referred to as "T" in the drawings.
It may be described as "AG2".

8 and 9 show the detailed structure of the buffer control unit SU included in the central processing unit 1 shown in FIG. Here, the wiring of the symbols shown in “A” to “G” in FIG. 8 is connected to the wiring of the corresponding symbol in FIG. 9. Reference numeral 20 in the figure is an LBS data management mechanism that serves as a data management mechanism (having the memory structure described in FIG. 3) of the buffer storage device 2, and 21 is a tag mechanism of the buffer storage device 2 (the information described in FIG. 6). It is the LBS tag mechanism that manages).

The buffer control unit SU of the central processing unit 1 is an address sent from the instruction control unit IU (a unit for controlling the entire pipeline of the central processing unit 1 and a unit for calculating an address for accessing the buffer). It is a unit that accesses the LBS data management mechanism 20 and processes the block of main memory data read by this access so as to be sent to the instruction control unit IU. In addition to the buffer control unit SU and the instruction control unit IU, the central processing unit 1 has an arithmetic control unit EU that actually performs arithmetic operations such as addition, subtraction, multiplication and division.

In FIG. 8 and FIG. 9, the logical address from bit 1 to bit 31 sent from the instruction control unit IU is set in the EAR 22, and in parallel with this, bits 13 to 19 of the lower address are It is input to the TLB 23 as a line address for accessing the TLB 23. In response to the input of this line address, two entries of primary and alternate are simultaneously read from the TLB 23, and the read logical address is compared with bits 1 to 12 of the EAR 22 by the comparators 24 and 25.

The LBS tag mechanism 21 is accessed by bits 18-25 of the logical address sent from the instruction control unit IU (bits 20-25 of which match the real address). That is, in this embodiment, the LBS tag mechanism 21 is accessed by 8 bits of bits 18 and 19 of the logical address and bits 20 to 25 of the real address. This LBS tag mechanism 21 is composed of eight associative levels from way 0 to way 7 in accordance with the LBS data management mechanism 20, and responds to the input of bits 18 to 25 of the logical address, from way 0 to way 7. The 8 pieces of real address information stored in are read out.

The 8 × 2 comparators 26 are provided to compare the real address read from the LBS tag mechanism 21 with the real address read from the TLB 23. Here, the comparator 26 enters the comparison processing of the real address without waiting for the comparison result of the logical address of the TLB 23 executed by the comparators 24 and 25, thereby performing the search of the LBS tag mechanism 21 at high speed. Will be done. The LBS tag mechanism 21 uses the logical address bit
Since it is accessed by 18,19, the converted real address bits 18,19 are also compared by the comparator 26.

The ALIGH & SELECT circuit 27 receives the comparison result of the comparator 26 and the comparison results of the comparators 24 and 25 and checks whether or not the comparison results are both satisfied. The way of the LBS tag mechanism 21 in which the sent logical address exists is specified. On the other hand, LBS data management mechanism 2
0 is accessed by bits 18 to 25 of the output of the EAR 22 delayed by one machine cycle from the LBS tag mechanism 21 and processes to read a block of main memory data. Then, the ALIGH & SELECT circuit 27
After selecting the block of the LBS data management mechanism 20 output from the identified way and determining the storage format such as packing data from the beginning of the WORD register 28 or packing data from the end, According to the determined storage format, the process of storing the selected block in the WORD register 28 is executed.

The command word / operand data of the main memory data thus stored in the WORD register 28 is
The data is sent to an instruction control unit IU (not shown) and used as instruction decode and operand data for operation.

On the other hand, when a write logical address is sent from the instruction control unit IU, it is converted into a real address by the TLB 23 and the LBS tag mechanism 21 is accessed, so that the LBS data management mechanism 20 receives a desired address. It is checked whether the address block exists. When the desired block address exists, the write data sent from the arithmetic and control unit EU is set in the SDR 30 via the ALIGN circuit 29 and then written in the LBS data management mechanism 20. Will be processed as follows.

On the other hand, if the desired block address does not exist, the real address of RAR31 is the MS.
It is set in the AR 32 and processed so as to be sent out as a move-in request address to the storage controller 4. At this time, the bits 18 and 19 of the logical address used for the search of the LBS tag mechanism 21 are sent to the storage control device 4 for data matching control, and the buffer storage device 2 of the storage control device 4 is also sent. For updating the copy of the tag, the way number determined by the procedure described below is also processed to be transmitted. In addition, unless otherwise specified as exclusive type, the move-in means a data transfer in a form in which the transfer source data is also treated as valid.

The buffer control unit SU receives the move-in request to the storage control device 4 from the LBS data management mechanism 2
A way number of 0 to be ejected is determined according to the LRU method. The block determined at this time is the storage controller 4
If the block has been changed after being read from, it is necessary to move out the block to the storage controller 4 according to the store-in method. In the move-out processing executed at this time, the real address of the way to be moved out is read from the LBS tag mechanism 21, and the selection circuit 3
Move out address via M3 32
In parallel with this, the move-out block data read from the LBS data management mechanism 20 is buffered in the MO buffer 34, and the acceptability state of the storage controller 4 is confirmed before passing through the MOR 35. Then, it is executed by sending it to the storage control device 4.

The SRAR 36 is the storage controller 4
It is used when the real address of the forced moveout / invalidation instruction to the buffer storage device 2 is received from the and the LBS tag mechanism 21 is searched. At this time, SRAR36
Stores the logical address bits 18 and 19 together with the real address bits 1 to 25 for data matching control.
Will be received from.

10 and 11 show an embodiment of the detailed configuration of the storage control device 4 shown in FIG. here,
Wiring indicated by symbols "A" to "E" in FIG.
1 is connected to the wiring of the corresponding symbol. 40 in the figure is a GBS that serves as a data management mechanism (having the memory structure described in FIG. 4) of the intermediate buffer storage device 5.
A data management mechanism, 41 is an intermediate buffer storage device 5.
G which becomes the tag mechanism (manages the information explained in FIG. 6) of G
Reference numeral 42 denotes a BS tag mechanism, and reference numeral 42 denotes a CPUTAG2 mechanism that manages copying of tags in the buffer storage device 2.

In the storage control device 4 shown in FIGS. 10 and 11, of the six ports 43 provided, five ports 43 actually receive the requests from the central processing unit 1 and the channel processing unit 11. The address, the operation code, and various control signals are held, and the received request is prioritized by the priority circuit 44 to acquire the access right to the GBS tag mechanism 41.

In the case of a read access request from the GBS data management mechanism 40, the GBS tag mechanism 41
The real address accessed by the address information set in the address register 45 and read by this access processing is compared by the comparator 46 with the access address of the register 47 set at the timing of G2. On the other hand, the address information set in the address register 45 is set in the GBSADRS 48, and a block of main memory data is read from the GBS data management mechanism 40 in accordance with this setting process.

Then, the way selection processing of the selection circuit 52 is controlled according to the comparison result of the comparator 49 shifted by the register 49, the register 50, the register 51, and the GBS data management is performed according to the way selection processing of the selection circuit 52. The block data from the mechanism 40 is selected and G
After being set in the BSDO 53, it is sent to the central processing unit 1 (channel processing unit 11) which has issued the request via the MDO 54. In parallel with this, the read main memory data is CHK55
SYD56 checks the ECC syndrome code, and if there is a 1-bit error, correct it by COR57 and then MDO5
4 via the central processing unit 1 (channel processing unit 1
The process of re-sending for 1) is executed.

On the other hand, in the case of a write access request to the GBS data management mechanism 40, the contents of the GBS tag mechanism 41 are compared by the same processing as the read access, and at the same time, the central processing unit 1 (channel processing device) is compared. The write data from 11) is temporarily buffered in the data pool circuit 60 via the registers 58 and 59, and then merged with the read data in the MRG 61. And
It is input to the GEN 62, an ECC code is created by the GEN 62, and then processed to be written in the GBS data management mechanism 40 via the GBSDI 63.

When searching the GBS tag mechanism 41, if the desired address does not exist, the move-in from the main memory 3 is required. When performing this move-in, among the plurality of ways in the intermediate buffer storage device 5,
The way block having the least reference frequency is processed so as to be selected as the replacement block. Then, when the replacement block is selected, if the M bit of the way is set to 1 indicating the changed state, the corresponding block is moved out from the intermediate buffer storage device 5 to the main storage device 3. There is a need. At this time, the block to be moved out is checked for ECC by SYD56 and COR57 via GBSDO53.
After the correction is executed, it is sent to the main storage device 3 via the MOR64.

When performing move-in or move-out from the intermediate buffer storage device 5, the access address is processed so as to be sent to the main storage device 3 via the register 65. In addition, the move-in from the main memory device 3 to the intermediate buffer memory device 5 is performed by the GBSDI after the ECC check / correction is executed by the SYD 56 and the COR 57 via the MSMI 66.
Processed to be written to the GBS data management mechanism 40 via 63.

FIG. 12 shows a detailed structure of the main memory device 3 shown in FIG. As shown in this figure, the main storage device 3 is composed of four MSU banks 70.
The U bank 70 is interleaved in units of 64 bytes,
At the time of data transfer to the intermediate buffer storage device 5, the four MSU banks 70 are sequentially accessed to execute data transfer of 64 bytes × 4 times. When moving out from the intermediate buffer storage device 5, only the changed block is sent from the storage control device 4,
It is processed as it is written on the corresponding MSU bank 70. In addition, in FIG. 12, MSUAR71 is
This is a register for receiving the address of the move-out request and the address of the data transfer request from the storage controller 4, and the MSU bank 70 is accessed according to the address information set in the MSUAR 71. The MSURDR 72 is provided for latching the data read from the MSU bank 70 at the time of data transfer, and will be transferred to the storage control device 4 via the MSURDR 72. In addition, MSUWR73,
It is provided for latching the data that is moved out from the storage control device 4 during the move-out processing from the storage control device 4, and through this MSUWR 73
The data to be moved out will be written into the bank 70.

FIG. 13 shows GBS of the storage controller 4.
FIG. 14 shows the detailed configuration of the tag mechanism 41, and FIG. 14 shows the detailed configuration of the CPUTAG2 mechanism included in the storage control device 4. Next, referring to this figure, the GBS tag mechanism 41 and the CPUTAG2 mechanism 42 which are characteristic of the present invention.
The function of will be described in detail.

First, the GBS tag mechanism 41 shown in FIG.
The function of will be described. If the desired data does not exist in the buffer storage device 2, M
The request address is sent to the storage control device 4 via the SAR 32. Upon receipt of this request address, the storage control device 4 first searches the GBS tag mechanism 41 to check whether or not the requested data is managed. That is, as shown in FIG. 13, GBS is set by the real address bits 10 to 23 of the address register 45 set at the timing of G1.
Ways 0 to 3 of the tag mechanism 41 are simultaneously searched, one of 16K entries is read and set in each of the four registers 80 provided.

The four comparators 46-1 (corresponding to one of the comparators 46 shown in FIG. 10) provided for the register 80 correspond to the real address bits 1 to 9 set in the register 80. By comparing the bit value with the bit values of the real address bits 1 to 9 of the request address of the register 47 set at the timing of G2, it is checked in which way the requested data exists. On the other hand, the four comparators 46-2 (corresponding to one of the comparators 46 shown in FIG. 10) provided corresponding to the register 80 have the bits 18 and 19 of the logical address set in the register 80. The bit value is compared with the bit value of bits 18 and 19 of the logical address sent from the central processing unit 1 together with the request address.

When both the comparator 46-1 and the comparator 46-2 produce a matching comparison result, the GBS data management mechanism 40
Means that there is data for which a request has been made, and that there is no problem even if that data is provided to the central processing unit 1 that made the request, so as will be described later, it is read from the GBS data management mechanism 40. Data will be transmitted. On the other hand, the comparator 46
When -1 gives a non-coincidence comparison result, it means that there is no request-requested data in the GBS data management mechanism 40, so that it will be moved in from the main memory 3, as will be described later.

On the other hand, even if the comparator 46-1 gives a matching comparison result, the comparator 46-2 may give a mismatching comparison result. This is done, for example, in the intermediate buffer storage device 5 (GB
The central processing unit 1 that has registered data in the S data management mechanism 40 / GBS tag mechanism 41) has an address conversion form different from the logical address-to-real address conversion form used at the time of registration. This happens when accessing 5. Further, when another CPU accesses the logical address bits 18 and 19 and the real address bits 1 to 9 registered by a certain central processing unit 1 with different logical address bits 18 and 19, that is, when they are registered. It also occurs when accessing with an address translation form different from the one. This happens because, as mentioned above, the mapping of logical addresses to real addresses is arbitrary.

In such a case, the GBS data management mechanism 4
If the data of the request request existing in 0 is provided to the central processing unit 1 of the request source, the data that should originally be the same data will be rewritten to different data, and the consistency of the data will be maintained. Disappears. from now on,
From the buffer storage device 2 of the central processing unit 1 which has brought in the data having the request request, the data is once moved out and the request request is issued for the logical address bits 18 and 19 registered in the GBS tag mechanism 41. It is necessary to provide the requested data with the requested data after rewriting it to the original one.

Next, the CPUTAG2 mechanism 4 shown in FIG.
The function 2 will be described in detail. This CPUTAG2
The mechanism 42 manages a copy of the tag of the buffer storage device 2, and can quickly search which central processing unit 1 of the buffer storage device 2 the data managed by the intermediate buffer storage device 5 is brought into. Which is prepared for each of the four central processing units 1, and has eight ways 0 to 7 in accordance with the associative level configuration of the buffer storage device 2. .
Since the CPUTAG2 mechanism 42 manages copying of the tag of the buffer storage device 2, access is performed by a combination of real address bits 20 to 25 and logical address bits 18 and 19 like the buffer storage device 2. Specifically, it is accessed by the real address bits 20 to 25 / logical address bits 18 and 19 of the register 90 set at the timing of G3.

Here, the logical addresses 18 and 19 set in the register 90 are set from the G2 timing register via the selection circuit 91 when the move-in access from the central processing unit 1 is performed, and are stored in the intermediate buffer. When the device 5 is moved out, the selection circuit 91 selects and sets the logical address bits 18 and 19 of the GBS data management mechanism 40 which are read from the way in which the real address matches.

The search result of the CPUTAG2 mechanism 42 is set in the register 92. The comparator 93 (which is the same as the comparator 93 shown in FIG. 10) provided corresponding to the register 92 has the bit values of the real address bits 1 to 19 of the search result set in the register 92 and the timing of G4. Real address bit 1 of register 94 set by
By comparing it with the bit values of .about.19, it is specified in which buffer storage device 2 of the central processing unit 1 the data to be searched is brought. Then, upon receipt of this identification result, a move-out request is issued to the identified central processing unit 1 via the register 67 shown in FIG.

Next, this GBS tag mechanism 41 / CPUT
It will be described in detail how the entries of the AG2 mechanism 42 will be used. [1] Shared Move-In Request from Central Processing Unit 1 When the central processing unit 1 issues a read-only shared move-in request to the storage controller 4, the control is as follows. This is the case where the real addresses of the GBS tag mechanism 41 match, that is, the requested data exists in the intermediate buffer storage device 5. The control at this time is as follows. (A) The logical addresses 18 and 19 of the GBS tag mechanism 41 match, and the E bit is 0. That is, the intermediate buffer storage device 5 has the requested data, and the uniqueness of the address conversion is maintained, and which central It also means that the processing device 1 is in a state of not exclusively bringing in data.

At this time, a desired 64-byte block is read from the intermediate buffer storage device 5 and sent to the requesting central processing unit 1 to register the real address in the corresponding entry of the CPUTAG2 mechanism 42, and at the same time Set the V bit to 1. Where CPUTAG
The entry to be updated by the second mechanism 42 uses the real address bits 20 to 25 / logical address bits 18 and 19 sent from the central processing unit 1 as the line address, and sends it as the way number from the central processing unit 1. It is an entry specified by using the one that has been received. (B) The logical addresses 18 and 19 of the GBS tag mechanism 41 match and the E bit is 1, that is, there is request data in the intermediate buffer storage device 5 and the uniqueness of the address conversion is maintained. This means that the central processing unit 1 of each unit is exclusively taking in data.

At this time, one entry of the intermediate buffer storage device 5 is 256 bytes and one entry of the buffer storage device 2 is 64 bytes, which corresponds to 64 bytes.
CPUTAG2 mechanism 4 while changing the address for each byte
By accessing 2 times 4 times, which central processing unit 1 is carrying in the data of the intermediate buffer storage device 5 is searched. According to this search result, when the same central processing unit 1 as the requesting central processing unit 1 exclusively takes in data, a desired 64-byte block is read and sent to the requesting central processing unit 1, and CPUTAG2 The real address is registered in the corresponding entry of the mechanism 42, and the V bit of that entry is set to 1.

On the other hand, according to the retrieval result, when another central processing unit 1 different from the requesting central processing unit 1 exclusively takes in the data, the central processing unit 1 which has exclusively taken in the data Request moveout, G
Set the E bit of the BS tag mechanism 41 to 0 and set the CPUTAG
The V bit of the corresponding entry of the 2nd mechanism 42 is also set to 0.
Then, as a result of the move-out, when a 64-byte block that is exclusively brought in is returned from the central processing unit 1, GB
While writing to the S data management mechanism 40, the M bit of the corresponding entry of the GBS tag mechanism 41 is set to 1. After this, the GBS data management mechanism 40 sends 64 request data.
The byte block is read and sent to the requesting central processing unit 1, the real address is registered in the corresponding entry of the CPUTAG2 mechanism 42, and the V bit of that entry is set to 1. (C) The logical addresses 18 and 19 of the GBS tag mechanism 41 do not match, which means that there is request data in the intermediate buffer storage device 5, but the uniqueness of the address conversion is not maintained.

At this time, in order to guarantee the consistency of the data, it is necessary to temporarily move out the data brought into the central processing unit 1. Therefore, the logical addresses 18 and 19 read from the way of the GBS tag mechanism 41 having the same real address are selected by the selection circuit 91 of FIG. 14 and set in the register 90, and the CPUTAG2 mechanism 42 is selected.
Are searched four times as described above, the central processing unit 1 that uses the unmatched logical addresses 18 and 19 is specified.

If a valid entry exists in the CPUTAG2 mechanism 42, a moveout of the data is requested to the central processing unit 1 which has brought the data of the entry. GBS tag mechanism 4 after move out
The logical address bits 18 and 19 managed by 1 are updated to those sent from the requesting central processing unit 1. After this,
A 64-byte block of the request data is read from the GBS data management mechanism 40 and sent to the requesting central processing unit 1, the real address is registered in the corresponding entry of the CPUTAG2 mechanism 42, and the V bit of the entry is set to 1. . This is the case where the real addresses of the GBS tag mechanism 41 do not match, that is, the requested data does not exist in the intermediate buffer storage device 5. At this time, the main storage devices 3 to 2
It is necessary to replace the entry in the intermediate buffer storage device 5 by moving in a block of 56 bytes.
The control at this time is as follows. (A) The V bit of the entry of the replacement target intermediate buffer storage device 5 is 1 and the E bit is 0, that is, the entry of the replacement target intermediate buffer storage device 5 determined by the LRU is not exclusive to the central processing unit. It means that it is in the state brought in 1.

At this time, it is necessary to move out the data brought into the buffer storage device 2.
Since it is a non-exclusive carry-on, there is no rewriting by the central processing unit 1. From now on, when the central processing unit 1 of the carry-in destination is specified by searching the CPUTAG2 mechanism 42 four times, a short move out (instructing the central processing unit 1 to invalidate the corresponding entry of the buffer storage device 2). Data move out is not required).

When this short move out is completed, next, a process of moving out the entry of the GBS data management mechanism 40 to be replaced to the main memory 3 is executed. In this processing, first, it is searched whether or not there is one among the four M bits of the GBS tag mechanism 41 associated with the entry, and if there is one, the corresponding one is dealt with. The 64-byte block to be moved is moved out to the main storage device 3. Then, when all moveouts are completed, the V bit is set to 0. Subsequently, a block of 256 bytes corresponding to the request address from the central processing unit 1 is moved in from the main storage unit 3 and the V bit / real address bit / logical address bit is registered in the GBS tag mechanism 41. Thereafter, a 64-byte block of request data is read out and sent to the requesting central processing unit 1, and then the real address is registered in the corresponding entry of the CPUTAG2 mechanism 42, and the V bit of that entry is set to 1. (B) The V bit of the entry of the replacement target intermediate buffer storage device 5 is 1 and the E bit is 1, that is, the entry of the replacement target intermediate buffer storage device 5 determined by the LRU is exclusively the central processing unit 1. Means being brought into the

At this time, unlike the above-mentioned (a), since the data brought into the buffer storage device 2 has been rewritten, it is necessary to move out the data. From now on, when the central processing unit 1 of the carry-in destination is specified by searching the CPUTAG2 mechanism 42 four times, the central processing unit 1 is requested to move out the corresponding entry of the buffer storage device 2, and this move out is performed. Upon completion, the M bit associated with the moved out 64-byte block is set to 1.

After that, the process of moving out the entry of the GBS data management mechanism 40 to be replaced to the main memory 3 is executed. This process is the same as the above (a). That is, first of all, it is searched whether or not one of the four M bits of the GBS tag mechanism 41 associated with the entry indicates 1, and if there is one that indicates 1, the corresponding 64. The byte block is moved out to the main storage device 3. Then, when all moveouts are completed, the V bit is set to 0. Then, the block of 256 bytes corresponding to the request address from the central processing unit 1 is moved in from the main storage unit 3, and the GBS tag mechanism 41 is moved.
The V bit / real address bit / logical address bit is registered in. After that, after reading the 64-byte block of the request data and sending it to the central processing unit 1 of the request source,
The real address is registered in the corresponding entry of the CPUTAG2 mechanism 42, and the V bit of the entry is set to 1
To (C) The V bit of the entry of the intermediate buffer storage device 5 to be replaced is 0, which means that the entry of the intermediate buffer storage device 5 to be replaced determined by the LRU is in an empty entry state.

At this time, since it is an empty entry, eviction from the buffer storage device 2 or the intermediate buffer storage device 5 is unnecessary, and the move-in is directly performed from the main storage device 3 to read the 64-byte block of the requested data. After sending to the requesting central processing unit 1, CPUTA
The real address is registered in the corresponding entry of the G2 mechanism 42, and the V bit of that entry is set to 1. [2] Exclusive Move-In Request from Central Processing Unit 1 The following is control when the central processing unit 1 issues an exclusive move-in request for rewriting to the storage controller 4. This is the case where the real addresses of the GBS tag mechanism 41 match, that is, the requested data exists in the intermediate buffer storage device 5. The control at this time is as follows. (A) The logical addresses 18 and 19 of the GBS tag mechanism 41 match, and the E bit is 0. That is, the intermediate buffer storage device 5 has the requested data, and the uniqueness of the address conversion is maintained, and which central It also means that the processing device 1 is in a state of not exclusively bringing in data.

At this time, when the CPU TAG2 mechanism 42 is searched four times to identify the central processing unit 1 which is bringing in the data in the shared type, the corresponding entry of the buffer storage unit 2 is invalid for the central processing unit 1. Demand a short moveout to be directed.

When this short move out is completed, next, the E bit of the GBS tag mechanism 41 is set to 1 and
After reading the 64-byte block of the request data and sending it to the requesting central processing unit 1, the CPUTAG2 mechanism 4
The real address is registered in the corresponding entry of 2, and the V bit of that entry is set to 1. (B) The logical addresses 18 and 19 of the GBS tag mechanism 41 match and the E bit is 1, that is, there is request data in the intermediate buffer storage device 5 and the uniqueness of the address conversion is maintained. This means that the central processing unit 1 of each unit is exclusively taking in data.

At this time, the CPUTAG2 mechanism 42 is searched four times to search for the central processing unit 1 of the carry-in destination which is bringing in the data in the exclusive type. According to this search result, when the same central processing unit 1 as the requesting central processing unit 1 exclusively takes in data, a desired 64-byte block is read and sent to the requesting central processing unit 1, and CPUTAG2 The real address is registered in the corresponding entry of the mechanism 42, and the V bit of that entry is set to 1.

On the other hand, according to the retrieval result, when another central processing unit 1 different from the requesting central processing unit 1 exclusively takes in the data, the central processing unit 1 which has exclusively taken in the data is Request moveout, C
The V bit of the corresponding entry of the PUTAG2 mechanism 42 is also set to 0. Then, as a result of the move-out, when the 64-byte block brought in exclusively from the central processing unit 1 is returned, it is written in the GBS data management mechanism 40 and
Set the M bit of the corresponding entry of the GBS tag mechanism 41 to 1.
To Thereafter, a 64-byte block of the request data is read from the GBS data management mechanism 40 and sent to the requesting central processing unit 1, the real address is registered in the corresponding entry of the CPUTAG2 mechanism 42, and the V bit of that entry is set. Set to 1. (C) The logical addresses 18 and 19 of the GBS tag mechanism 41 do not match, which means that there is request data in the intermediate buffer storage device 5, but the uniqueness of the address conversion is not maintained.

At this time, similarly to the processing of [1] (c), the CPU TAG2 mechanism 42 is searched to identify the central processing unit 1 which is bringing in the requested data, and the central processing unit 1 is notified of that. Request moveout of requested data. Then, the logical address bits 18 and 19 managed by the GBS tag mechanism 41 are updated to new ones, and the E bit is set to 1. Thereafter, a 64-byte block of the request data is read from the GBS data management mechanism 40 and sent to the requesting central processing unit 1, the real address is registered in the corresponding entry of the CPUTAG2 mechanism 42, and the V bit of that entry is set. Set to 1. The real address of the GBS tag mechanism 41 does not match. The process is the same as [1] except that 1 is registered in the E bit of the GBS tag mechanism 41. [3] When the central processing unit 1 issues a request to change the shared-type entry to the exclusive-type entry, that is, after the central processing unit 1 issues a reference-only move-in request and brings in the data, It occurs when it becomes necessary to rewrite.

At this time, after confirming that the real address bit / logical address bit of the GBS tag mechanism 41 match and the E bit is 0, the CPUTAG2 mechanism 42
By retrieving, it is checked whether or not the central processing units 1 other than the requesting central processing unit 1 bring in the data to be rewritten. According to this check, when it is determined that the other central processing unit 1 is bringing in data, a short move out from the buffer storage device 2 is instructed. Then, by setting the E bit of the GBS tag mechanism 41 to 1, only the requesting central processing unit 1 can be used exclusively. [4] When a move-out request is issued from the central processing unit 1, that is, it means that the buffer storage unit 2 of the central processing unit 1 is in a state of replacement. (A) Long move out request When the M bit of the block data to be replaced in the buffer storage device 2 is 1, a long move out request to transfer the block data to the intermediate buffer storage device 5 is issued. At this time, the moveout data is written in the GBS data management mechanism 40, and the corresponding M bit is set to 1, and then the CPUTA
The corresponding V bit of the G2 mechanism 42 is set to 0. (B) Short move out request When the M bit of the block data to be replaced in the buffer storage device 2 is 0, a short move out request is issued. At this time, the corresponding V bit of the CPUTAG2 mechanism 42 is set to 0.

[0089]

As described above, according to the present invention,
At the time of adopting a hierarchical memory structure of three layers of a buffer memory device, an intermediate buffer memory device and a main memory device,
As the line address of the buffer storage device, the number of entries is increased by using the combination of the real address in the page and the lower part of the logical address, and the configuration for resolving the data consistency generated by adopting this configuration is constructed. Therefore, the capacity of the buffer storage device can be increased while suppressing an increase in the amount of hardware.

Further, according to the present invention, since the increase in the amount of hardware required for realizing the buffer control of the store-in system is not affected by the number of entries in the intermediate buffer storage device, the number of entries in the intermediate buffer storage device is Even when there is a large number of stores, it is possible to realize store-in type buffer control while suppressing an increase in the amount of hardware.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is an example of a data processing system implementing the present invention.

FIG. 3 is an explanatory diagram of a memory configuration of a buffer storage device.

FIG. 4 is an explanatory diagram of a memory configuration of an intermediate buffer storage device.

FIG. 5 is an example of a tag managing entries in a buffer storage device.

FIG. 6 is an example of a tag managing an entry in an intermediate buffer store.

FIG. 7 is an example of a copy of a tag in a buffer storage device.

FIG. 8 is an example of a buffer control unit included in the central processing unit.

FIG. 9 is an example of a buffer control unit included in the central processing unit.

FIG. 10 is an example of a storage control device.

FIG. 11 is an example of a storage control device.

FIG. 12 is a device configuration diagram of a main storage device.

FIG. 13 is a configuration diagram of an embodiment of a GBS tag mechanism.

FIG. 14 is a configuration diagram of an embodiment of a CPUTAG2 mechanism.

FIG. 15 is an explanatory diagram of an address conversion process.

[Explanation of symbols]

 1 Central Processing Unit 2 Buffer Storage Device 3 Main Storage Device 4 Storage Control Device 5 Intermediate Buffer Storage Device 6 Data Management Means 7 Tag Means 8 Mapping Tag Means 9 Buffer Control Means

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hidehiko Nishida 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (5)

[Claims] 1. A plurality of central processing units having a buffer storage device share one or a plurality of main storage devices, and a storage control device has a relatively large capacity intermediate buffer storage device. In a data processing system in which a processing device shares the intermediate buffer storage device, the storage control device is a tag means (7) of the intermediate buffer storage device.
In addition to the above, at least a configuration is provided that includes a mapping tag means (8) for managing a copy of the valid information / real address information possessed by the tag means of the buffer storage device, and according to the management data of the mapping tag means (8), By determining which buffer storage device the main storage data managed by the intermediate buffer storage device is brought into, the control processing of the data consistency between the buffer storage device and the intermediate buffer storage device is executed. Hierarchical memory control method characterized by the following processing. 2. A plurality of central processing units provided with a buffer storage device share one or more main storage devices, and a storage control device provided with a relatively large capacity intermediate buffer storage device. In a data processing system in which a processing device shares the intermediate buffer storage device, the buffer storage device uses a combination of a real address in a page and a lower part of a logical address as a line address, and the intermediate buffer storage The tag means (7) of the device manages the lower address of the logical address specified by the central processing unit that brought in the main memory data in addition to the real address that points to the main memory address. Equipment Tag Means (7)
By controlling so that the logical address managed by is unique to the corresponding real address, the processing to control the data consistency between the buffer storage device and the intermediate buffer storage device is executed. Hierarchical memory control method characterized by: 3. A plurality of central processing units having a buffer storage device share one or a plurality of main storage devices, and a storage control device comprises a relatively large capacity intermediate buffer storage device. In a data processing system in which a processing device shares the intermediate buffer storage device, the buffer storage device uses a combination of a real address in a page and a lower part of a logical address as a line address, and an intermediate buffer storage device. The tag means (7) of (3) manages the lower part of the logical address specified by the central processing unit that brought in the main memory data together with the real address that points to the main memory address, and In addition to the tag means (7) of the device, at least the valid information / real address information possessed by the tag means of the buffer storage device. Copy adopts a configuration including a mapping tag means for managing (8) of the storage controller, the tag unit of the intermediate buffer storage device (7)
Control is performed so that the logical address managed by is unique to the corresponding real address, and according to the management data of the mapping tag means (8), the main memory data managed by the intermediate buffer memory device is stored in which buffer memory Hierarchical memory control method characterized by performing processing to control the data consistency between the buffer storage device and the intermediate buffer storage device by determining whether or not it has been brought into the device. 4. The hierarchical memory control system according to claim 3, wherein the storage control device is a tag means (7) of the intermediate buffer storage device.
Mapping tag means using lower part of logical address read from
Hierarchical memory control method characterized by processing to access (8). 5. The hierarchical memory control system according to claim 3, wherein when the central processing unit requests data transfer from the intermediate buffer storage device, the central processing unit, together with a real address indicating a main storage address, The logical address lower part used for accessing the buffer storage device and the way number to be replaced in the buffer storage device are sent out, and the storage control device stores the sent real address / logical address lower part in the intermediate buffer storage. Device tag means
Compared with the real address / logical address lower part read from (7), if the real address matches but the logical address lower part does not match, the mapping tag means (8) The buffer memory device to which the main memory data pointed to by the real address is brought in is specified, the main memory data is moved out from the specified buffer memory device, and the tag means (7) of the intermediate buffer memory device manages it. The lower part of the logical address is rewritten to the lower part of the logical address issued by the data transfer request source, and then the main memory data is transferred to the central processing unit of the data transfer request source and is issued by the data transfer request source. A hierarchical memory control method characterized in that the management data of the mapping tag means (8) is updated according to the way number.