JPS63266560A - Buffer storage control system - Google Patents

Abstract

PURPOSE:To reduce the number of times of purging operation and to reduce the capacity of a tag storage by performing canceling operation in block units. CONSTITUTION:The canceling operation is performed in block units, so that purging operation at the time of cancellation is not performed in subblock units and the number of times of purging operation ins increased to reduce the probability that buffer storage referring operation is suppressed, thereby improving the performance. This results from that while the buffer storage referring operation is inhibited, a processor enters a purging operation end wait state temporarily. Further, the canceling operation is performed in block units and information corresponding to not subblocks, but blocks is stored in the tag storage; and the tag storage is therefore composed of a storage element which has relatively small capacity and the quantity of hardware is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is applicable to data processing devices VC having buffer storage.

[Conventional technology]

Data transfer between main memory and buffer memory (block transfer)
The above-mentioned block transfer method is generally known in which the block transfer is performed in units of sub-blocks obtained by further dividing the unit 1' (if there is a restriction, the block (unit for mapping between main memory and buffer memory)).

In this method, by making the blocks too small,
This is a method for avoiding a decrease in the buffer hit ratio and an increase in the size of the buffer address array. However, in conventional devices, in order to use common hardware for the reference operation to the buffer address array and the cancel operation, the cancel operation was also performed in sub-block units.

A method has also been proposed in which a large capacity buffer storage is realized with a relatively small amount of data by accessing the buffer storage using a logical address by using a partial tag storage. Below, I will explain the reasons why I chose to memorize tags, focusing on those related to cancellation. The lower pit of the page address portion of the logical address (address f: the portion converted into a physical address by conversion) is called a class. The technique of using not only the physical address but also a portion of the logical address to access the buffer address array and buffer storage is common, especially in large machines.

This method realizes large-capacity buffer storage by also using a logical address as the unique address of the buffer memory, and at the same time enables simultaneous access to the buffer address array and address conversion device, thereby speeding up the buffer storage access operation. It is characterized by

In order to achieve access to buffer memory using logical addresses in small machines, a memory bank of buffer address arrays is configured for each class (this increases the number of memory bits and increases the amount of memory). (There is a request to provide class bits as address bits of memory that constitutes a buffer address array.

However, if the class bit is supplied as the address of the buffer address array, it is necessary to access the buffer address array a number of times (4 times if the class bit is 2 bits) during the cancel operation. Japanese Patent Application Publication No. 5
No. 6-16982, ``Buffer Storage Control Method,'' provides a method in which a class bit is supplied as an address to a buffer address array, and the array is accessed multiple times as necessary. In this method, while the buffer memory is accessed multiple times for the cancel operation, reference operations to the buffer memory are suppressed, resulting in a decrease in performance. A separate tag memory is provided, and when a cancel operation is performed, only the tag memory is referenced, and if there is a copy to the buffer memory (the probability of this is very low), the process is delayed: by accessing the buffer address array. A method to avoid the above-mentioned deterioration in performance may also be considered.

However, when block transfer is performed in sub-block units and the tag memory holds information corresponding to the sub-blocks, the problem remains that the tag memory becomes huge.

[Problem that the invention seeks to solve]

In conventional sub-block type buffer storage, the amount of hardware is reduced by using common hardware for reference operations to buffer address arrays and cancel operations. Therefore, the cancellation operation is also performed for each subblock. However, access to the main memory by the input/output processing unit, which is generally the cause of cancellation, is
This is often performed on consecutive main memory addresses (
Immediately after purging a certain sub-block in response to a cancellation request, the purge operation must be performed again in response to generation of a cancellation request for a sub-block adjacent to the sub-block. As a result, the number of purge operations increases, leading to a decrease in performance (because the buffer address array cannot be referenced during the purge operation.On the other hand, the introduction of tag memory By inputting the amount of material, it is possible to access the buffer memory using logical addresses and achieve large-capacity buffer storage, but if the tag memory stores the presence or absence of a copy of the main memory in units of subblocks, the amount of material in the tag memory becomes huge. There was a problem of becoming

[Means for solving problems]

The present invention performs the cancellation operation on a block-by-block basis with the addition of a small amount of hardware.

Furthermore, even in a buffer storage system that introduces tag storage and uses logical addresses, the presence or absence of a main memory copy is maintained in the tag storage not in sub-block units but in block units, and the cancel operation is also performed in block units.

[For production]

In the present invention, since the cancellation operation is performed block by block, the purge operation does not occur for each subblock when canceling (the probability that the buffer memory reference operation is suppressed due to the increase in the number of purge occurrences decreases, and the performance This is because while the buffer memory reference operation is suppressed, the processing!!
This is because it will be in a waiting state.

In addition, by performing the cancellation operation on a block-by-block basis and storing information corresponding to sub-blocks in the tag memory (block-corresponding information), the tag memory can be configured with memory elements with a relatively small capacity. The amount of wear is reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

Note that although this explanation is based on the case where tag memory is provided, it is easy to analogize the operation when there is no tag memory.

When referring to the buffer storage, a logical address is set in the logical address register 1. The logical address register 10 bits 8 to 19 are the logical page address, and bits 20 to 19 are the logical page address.
51 is an address within the page.

Bits 26 to 51 are the intra-block address, bit 2
6-27 is a block address within the block. First, the operation when referencing buffer storage will be briefly explained. When referring to buffer memory, lower bits 18-1 of the page address
9 (class) is supplied to buffer address arrays 8 and 9 via selector 4 and class changer 7 (output of 7 = input of 7 when referencing), and bits 20 to 25 of the address within the page are supplied via selector 5 to buffer address arrays 8 and 9. be done. Buffer address array No. 8.9 K contains main memory address bits 8 to 19 and valid information for each subblock VO to ■3 in each two bins.
is stored. Address translation device (as shown)
The physical address line 2, which is the output of 1), is compared with the output of the buffer address array in a comparator 10.11.

Valid information ■0 to ■3 are selected as one pit each by selectors 12.11 by page addresses 26 to 27, and after passing through selectors 16.17, are ANDed with the outputs of comparators 10 and 11 by AND logic 1a;19. Rear encoder 20
The row address is determined. The 100 row address is supplied to the address of the buffer storage, and the data in the row storage is output to the data fIM22.

Next, the cancel operation will be explained. When requesting cancellation, the cancellation address is cancel address register 3.
is set to . To be precise, this cancel address is the address of the block to be canceled, and does not have bits 26-51, which are intra-block addresses.

This address is supplied to the tag storage via the selector 26. The tag memory has information on a block basis (not on a subblock basis) as to whether or not a copy of the main memory exists in the buffer memory. Therefore, tag storage can be realized with a capacity only because the main memory is divided into blocks. The output from the tag memory access is sent to the cancel control logic 25, and when the output is 11m, the cancel control logic activates an access operation using the cancel address to the buffer address array.

Cancel address bits 18-19, bits 20-
25 are supplied to buffer address arrays 8 and 9 via selectors 4 and 5, respectively. On the other hand, bits 8 to 19 of the puffer address array and cancel address bit 8
~19 are compared in comparator 10.11.

The valid information VO to (3) is ORed by the OR logics 14 and 15, passed through the selectors 16 and 17, and then ANDed with the output of the comparator by the encoder 20. OR logic 14.
15, the buffer address array cancel operation is realized not in sub-block units but in block units. As mentioned above, when referring to the buffer memory, the OR logic is 14,1.
5 (selectors 12 and 15 are used. The output of encoder 20 is sent to the cancel control logic and the two bins of the buffer address array corresponding to the appropriate row are purged. Cancel and cell operations are block-based. Therefore, when a purge operation occurs in sub-block units, reference operations to buffer storage using logical addresses and physical addresses are suppressed, and performance does not deteriorate.

〔Effect of the invention〕

If a block is composed of N subblocks,
Compared to a method in which cancellation is performed in subblock units, in this method, the number of times a purge operation occurs is reduced to about 1/N, and the tag storage capacity is reduced to 1/N.

[Brief explanation of drawings]

The figure is an explanatory diagram of buffer storage and its peripheral logic according to an embodiment of the present invention. 1... Logical address register 2... Physical address line 5... Cancel address register 7... Class changer 8.9... Back 7 address array 10.11... Comparator 14, 15 ...OR filling 18.19...AND logic 20...Encoder 21...Buffer memory 22...Buffer memory data line 24...Tag memory 25...Cancel control logic

Claims (1)

[Claims] 1. It has a main memory and a buffer memory that stores copies of data in a part of the main memory in units of blocks, and a buffer address array that stores the main memory addresses of the data stored in the buffer memory. A buffer storage control method characterized in that a data processing device transfers data between storage and buffer storage in units of subblocks obtained by further dividing a block, and in which a cancellation operation is performed in units of blocks.