JPS58185082A - Information processing system - Google Patents

Abstract

PURPOSE:To accelerate the information processing time, by dividing a main storage into plural spaces in response to the addresses and preparing a storage checking address array of each surface with each space and each CPU to decentralize the register/check requests. CONSTITUTION:A main storage 106 of a main storage device 105 is divided into two spaces, for example, in response to the storage addresses. Then address arrays for store checking SCAA 111, 601, 112 and 604 are provided. The SCAA 111 and 601 fetch a copy of a buffer storage address array BAA 109 of an arithmetic processor 101; while the SCAA 112 and 604 fetch a copy of an array BAA 110 respectively. As a result, both register requests and storage checking requests of the SCAA are decentralized to SCAAs of plural surfaces. This improves the processing capacity of the SCAA and attains a high speed for information processing.

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention The present invention relates to control of buffer storage used in an arithmetic processing unit in an information processing system.

BACKGROUND ART In information processing systems with high throughput, the cycle time of arithmetic processing units has been significantly shortened due to recent advances in semiconductor technology and packaging technology. Although there has been an improvement, access time and cycle time have not improved much.

As a means to fill this gap, high-speed RAM (Random Access Memory) is installed in the processing unit.
A buffer storage using an or)+) element is prepared, and a part of the data that is likely to be used in the future is taken in as a copy from among the data in the main memory, and the arithmetic processing unit A so-called buffer storage method that aims to shorten storage access time by using data on this buffer storage has become common.

FIG. 1 is an example of a conventional technology of an information processing system that uses such buffer storage to increase speed.

Arithmetic processing bag C (hereinafter referred to as CPU) 101.102 is a buffer storage (hereinafter referred to as BS) 107.1 and a buffer storage address array (hereinafter referred to as BS) for controlling this.
(hereinafter abbreviated as BAA) have 109 and 110, respectively.

The main storage unit (hereinafter referred to as MSU) 105 includes a main memory (hereinafter referred to as MS) 106, and the CPU 1o1 102 and channels (hereinafter referred to as CH) 105 and 104 are connected.

@Figure 2 shows BA in the so-called congruent method.
This is an abbreviation of the addressing mechanism of A109, B S 107, and M 8106. FIG. 2 shows a case where 51 address bits are used as the storage address of the MS, and access to the M8106 is performed by using a canned (8 byte) address.

Also, the capacity of B S 107 is 64 bytes (K) 102
4) shows the case where the block size is 64 bytes, and the BAA 109 has 1,024 entries. H
AA 109, B S 107, S U 10
(S is storage address pin) It is divided into 64 columns (Co to C63) specified by 20-25, and BAA109. B12O3 is 16 for each column
There are rows (RO to R15), which are divided into a total of 1,024 blocks. Furthermore, if the M8106 has a capacity of 16 Mbytes, it is divided into 4096 rows. Each entry of BAA1n9 stores 20 storage address bits 1-20 and a V bit indicating whether or not the entry is valid.

Now, move the block containing address 4160 of 8M106 (the shaded block at 5M106 in Figure 2) to 5M1.
06 reading and storing to B S 107
The operation of M is shown. FIG. 3 shows address 4160 in binary notation. From this, address 4160 is column address 1
It can be seen that it belongs to (CI). Although it is not shown which row in the BAA column, the BA
There is a circuit that determines the row address at the time of A registration, and if there is a row of V pit IQI, it allocates that row sequentially, and if the V bits of all rows in column 2 are +1+, LRU (Least Recently Used)
) 7 The row selected by the algorithm is replaced with a new address. In Figure 2, 0 row (RO
) is assigned. The registered address shown in Figure 3 is stored in the entry in column 1 and row 0 of BAA, and when the bit becomes "1", B S 1
The data of the block (64 bytes) including address 4160 read from 5M106 is stored in the 1 column, 0 row block of 07.

When the CPU 101 reads 5M106, it checks whether the data file B5107 of the block including the address has been taken in.

For example, when reading address 4160, one column from that storage address (pix) 20-25 is selected, and
Read all 160 bits in one column of the AA 109, and use the comparison circuit 201 provided for each row to compare the address registered in each row with the 1 bit of the storage address bit.
20 comparisons are made and a search is made to see if there is an entry in which they match and the V bit is '11'. In the case of address 4160, a match is taken in the 0 row, 1 column of B S 107,
Since it can be seen that the desired data is in the 0 row, the CPU 10
Since the desired data can be obtained by reading B S 107 without reading 5M 106, the access time is greatly shortened.

Since the data in the BS is a copy of the data in the MS, if the two values do not always match, this information processing system will malfunction.

The following four factors can be considered to cause a mismatch between the data in the MS and the data imported into the BS as a copy of a portion of the data.

■ When the CPU writes to the MS, if the block address corresponding to the write address is registered in BAAK and the V bit is “1°,” the CPU writes only to the BS and then writes to the MS. Don't do it.

■ When the CPU writes to the MS, if the block address corresponding to the write address is registered in the BAA and the V bit is “1”, it writes only to the M8 and writes to the BS. Do not write.

■ When the CPU writes to the MS, the block address corresponding to write address 1C is the BA of the other CPU.
t: is registered in A, and the v bit is 111.

(C) When J wrote to the MS, the block address corresponding to the write address was registered in the BAA of one or more CPUs, and its V bit was 01'.

In the prior art shown in FIG.
In order to prevent data mismatch in S, the following means are used.

First, as a means to prevent the occurrence of the above ■■, when the CPU 101 writes to the MS in FIG. Check to see if it is at 1°.

When it is registered and the V bit is 111, it is BS.

Write to both MSs. If the block is not registered or if the V bit is IQI even if it is registered, the corresponding block does not exist in the BS, so it is sufficient to write only to the MS.

In order to prevent the occurrence of
Store check address arrays (hereinafter abbreviated as 8CAA) 111 and 112 are provided within the MSU 105.

S CA A 111.112 are respectively B A A
109.11 [), and when writing is performed to M 8106, is the block corresponding to the address to which the writing was performed not taken into B 8107 or 108 of CPU 101 or 102? Please check it out.

J... As a result of checking, the corresponding block is B5107 or 0.
If it is found to be incorporated into M S U 10
5 is ■ For the CPU 101 or 102 that is importing the corresponding block into the BS, the block address where writing was performed and the row address where the corresponding block address of 5CAA was registered (this matches the row address of BAA) ) and instructs to invalidate the corresponding entry in BAA (set bit to °0').

At this time, the V pinto of the corresponding entry of 8CAA is also set to IO.

■ Send the block address, row address, and write data to which the writing was completed to the CPU 101 or 102 that is importing the corresponding block to the BS, and
The contents of BS and MS are also changed to maintain consistency between the contents of BS and MS.

Whether to perform (2) or (2) is not directly related to the purpose of the present invention, so it will not be discussed here.

FIG. 4 shows a Pronk diagram around 5CAA111 in FIG. 1. According to this diagram, CPU 1o1 B810
A conventional technique for a write address check (hereinafter abbreviated as store check) to prevent mismatch between M.7 and M.8106 will be described. Note that for CP 102, this is achieved in a similar manner.

The CPU 101 stores a certain block in the MS 106 as B510.
7, through the address line 404, the CP
The address signal sent from U 101 is latched in address register 409.

From this address, the column address of bits 20-25 is passed through the selector 413 to the decoder 4 as shown in FIG.
18 determines which of the columns 0 to 63 of 8CAA111. On the other hand, the CPU 101 uses the BAA 109
, register the corresponding block address, but at this time, BA
As mentioned above, how to create the column address for A is 8CA.
Same as A, (for the same block address, 5
(The column addresses of CAA and BAA match) Also, the row address is registered in an entry specified by the value determined by the row address determination circuit described above.

The CPU 101 sends the above row address to the M8U1n5 from the row address line 405K, and latches it in the address register 410.

The output of the address register 410 is input to the decoder 419 through the selector 414v, so that 5CAA1
One of the 11 rows from 0 to 15 is selected. (As a result, for the same block address, 8CAA and B
AA row address also matches), Register bits 1 to 20 of the block address in the 5CAA entry selected in this way, and set the V pit to 111 to indicate that this entry is valid. .

The following F completes the registration of 5CAA.

Address line 401 f”!, C) l 105, address line 402 from C11104, address line 403 from CPU 102, and when each device writes to 80106, address register 406, 407 respectively. The 1 address is latched into .408.

The latched write address is passed through the selector 411 and checked by the latch 412. Bits 20-25 of the write address stored in latch 412 are 5CA
One column is selected by the decoder 41B through the selector 41'5 as the column address of A111. Bits 1 to 20 of the write address stored in latch 412 are input to conveyor circuit 415 . The outputs of each of the 16 rows (registered address bits 1-20 and the V bit) of the column selected as described above of the 1.9 CAA 111 are input to the conveyor circuit 415. Selection circuit 41
5 compares the input from the 5CAA 111 and the input from the Lavchi 412, and searches for a row in which the values of address bits 1 to 20 match and the ■ bit is 1. If the above row exists, store the row address in register 417 and write address bits 1-2 at this time.
5 is stored in address register 416.

Due to the above operation, CPU 101 uses its B5107
CH103 or 1 for the pro I that is importing data to
04, it is possible to detect from CPU1Ω2 that convolution has been performed. If writing is done, B S
If you want to invalidate the corresponding block of 107, M
8U 105 sends the insertion address stored in the address register 416 and the row address stored in the register 417 to the CPU 101, and instructs the CPU 101 to set the V pit of the corresponding entry in the BAA to 0°, 5
Click 'O' for the ■period in the corresponding entry of CAA111.

FIG. 5 is an example of a timing chart showing the operation of 8CAA111 according to the prior art.

This timing chart shows the cycle time of 8CAA and the CPU102. We are considering a case where the generation cycle time of store check requests from CH103 and CH104 is hi], but in recent high-speed information processing systems,
The occurrence of such high-speed main memory write requests is not uncommon.

In Fig. 5, during time T, VC, CPU 101 Karano 5CA
A registration fee request was made once, C)' Store check request from U 102 was made 11 times, store check request from CH103 was made 2 (B), and store check request from cHtoa was made 1 time.
of these store check requests.
102, what is generated from CH103 is SCA
111, and V=1, and writing of ■=0 of 8CA111 is performed for these. Note that writing V=o in the 5CA 111 requires a store check and another cycle.

In Fig. 5, 15 store check requests and one 8CAA registration request are generated during time T, but only 7 store checks and 1 5CAA registration could be processed. Six store checks remain unprocessed. In the conventional technology, the following problems occur because such store checks are left unprocessed.

1 By providing a stack to store unprocessed store check requests, it is possible to postpone checking the number of stacks, but there is a limit to the number of stacks, and for the amount exceeding this, The writing to the SM 106 itself is made to wait, or the writing request of the CPU, C)l or h is stopped.

2 Providing a stack to store the above store check requests increases the time gap between writing 8M106 and invalidating the d-bronx in B5107, increasing the time for MS-BS mismatch. At the same time, the number of stacks cannot be increased too much because this will lead to an increase in the number of hard books.

3 From below, the throughput when writing to S U 106 is not the cycle time of 5M106 (, 5CA).
It is determined by how many store check requests can be processed by A111, and even if we try to increase the throughput of 5M106, the processing capacity of store checks of 8CAA111 will be 1. , the throughput of SM 1()6 could not be increased, and the processing capacity of 5CAA111 was 8M 10
This hinders the throughput improvement of 6.

OBJECT OF THE INVENTION An object of the present invention is to solve the problems of the prior art and
M106 write throughput is SCA A1
This is to avoid being limited by the processing capacity of 11.

An advantage of the invention is that the address array 5 for store checking is
Prepare multiple CAAs and use the storage address to
By changing the 5CAA to register and check, 5C
The objective is to improve the processing capacity of AA.

Embodiment of the invention @ Fig. 6 is an embodiment of the present invention, and compared with the prior art shown in Fig. 1, M 8 U 105 Ni 8 CA A 601
It can be seen that ゜602 has been added.

In FIG. 6, M2O is an address array for store checking, and 8 CA A 111.601°60
I have a total of 4 pieces, 2. Here, 8CAA111.6
01HA CPU101-BAA109 copy, 5CA
A 112,602 CPU102 BAA11017
) will import a copy.

S CA A 111 and 601, or 5CAA112
The following shows how to use 602 and 5CAA1.
11 and 601 will be explained, but this is 5CAA11
This also applies to 2 and 602.

In the embodiment of the present invention shown in FIG. 6, an example is shown in which the MS 106 is divided into two spaces based on its storage address, and the CPU 101 retrieves the data of the block mapped to either space into the B5107. 5CAA1￥ to store the block address depending on whether
I have decided.

FIG. 8 shows an example in which 5 CAAs are distributed according to even block addresses and odd block addresses.

In Figure 8, even block address (the first storage address of the block is 64X2n: n = 0
．． 1.2. ) is 8
Using CAA111, odd block address (first storage address of the block is 64X(2n+1)
: refers to the address of the block nriO, t2...) is designed to use SCA A 601. For example, the CPU 101 transfers one block starting from storage address 128 of 8 U 106 to B S 10.
7, the block address is 5CAA1.
11, when one block starting from storage address 192 of M8106 is to be imported into B5107, the block address is registered in SCA 601.

FIG. 7 is an embodiment of the present invention corresponding to FIG. 4 of the prior art. When the CPU 101 reads a certain block from the MS 106 and stores it in the BS 107, the block address is sent through the address line 404, and the row address of 8CAA is sent through the row address line 4Q5 as shown in FIG. is the same as In Fig. 7, if the block address at this time is an even block address, it goes to 5CAA111, and if it is an even number address, it goes to SCA.
A Register to 601. CH105, 104 and CP
When U102 writes to MS106, its scan address is on address lines 401, 402 and 402, respectively.
It is sent by 405. At this time, if the 1 address is an address that moves to an even block address, it is latched to the address register 412 through the selector 411, and if it is an address that moves to an odd block address, it is latched to the address register 702 through the selector 701.
is latched to. Write address bits set in address registers 412, 702) 20-25 are 8CA
Selectors 413 and 703 respectively as AO column at Vs
is supplied to decoders 41B, 7[]9 through 8CA
A 111 , S CAA 601 8 and select one column i-20 are each conveyor circuit 4
15. Search for a row that matches the address read out from the 16 rows of column addresses previously determined and whose V bit is 11". The conveyor circuit 415 or 705 reads the address. If it is detected that they match and the V bit at that time is 111, the write address at that time is set to the address register 416 through selectors 707 and 708'g, and the row address of 5CAA at that time is set to the address register 416 through selectors 707 and 708'g. 704, is set in the register 417, and sent to the CPU 101.
Set the v bit of the corresponding entry of BAA109 to 'C1' i
'n, and S CA A 111
Alternatively, the V bit of the corresponding entry in 601 is set to IQI.

CH1n3.104, CPU 1[]1.102noS
Since the commitment to U 106 is performed, for example, in units of 8 bytes at an 8-byte boundary address (8th address boundary address), one write does not span two blocks. Therefore, C) l 1[13, 1[+4, CP
For one write of U102 to 5U106,
It is sufficient to check either 5CAA111 or 601 once. For example, if Cu2O3 writes in an even block address and Cl1104 writes in an odd block address, S
CA A 111.601 can be operated simultaneously, and store check throughput can be doubled compared to the conventional technology. In addition, in FIG. 7, 706
is a selector, and 710 is a decoder.

According to an embodiment of the present invention, the time chart of FIG.
It will look like Figure 9. In FIG. 9, store check request 1.2.4.5.6.13 belongs to an odd block address, so SCAAll is used, and store check request 5.7.8.9.1011.12 uses SCAAll. Since it belongs to an even block address, 8 CA
I am using A601. Furthermore, since 5CAA registration request A is an odd block address, 5CAA111 is used.

Other Embodiments (,) Part 1 In explaining Embodiment 87 of the invention, in Fig.
'5CAA1 by storage address of M106
Deciding whether to use 11 or 601, 5
8 CAAv are used depending on whether the block address is odd or even when registering the CAA and whether the block address is odd or even when storing.

As another example, in the configuration shown in Figure @7, 5CA111 and 601 are not distinguished by storage address, but they are registered in both 8CAAs at the time of registration, and when the V bit is set to 0°, the corresponding entries in both 5CAAs are There is a method to set it to 0'.

An example of a time chart in this case is shown in FIG.

The example in FIG. 10 shows an example in which SCA 111 is used when two or more store check requests are not accumulated, and both 5CAA 111 and 5CAA 601 are used when two or more are accumulated.

In store check request numbers 2 and 3, the addresses match and the V bit becomes 111, and a store check occurs, so the relevant en) for both 8CAA111 and 601)
The V bit of IJ is set to 101, and in 8CAA registration request A, it is registered in both SCA~.

(b) Part 2 In the explanation so far, we have considered the case where only one M2O exists in the system. However, some systems provide multiple M2O units within the system.

An example where there are multiple M2Os in the system @
In addition to FIG. 1, M S
U 121 exists, M S U 121 is MS[J1
05 as well as S U 122 and 5CAA125.124
have.

The method of using 5CAA in the system of FIG. 11 is shown below.

When the CPU 101 reads a block within 8 U 106 and stores it in the B S 107, it registers the block address in the BAA 109 and also sends the block address to the SCA A 111.
Register the blocks in S U 122 one after another B 8
107, the block address is BA
When it is registered in A109, it is also registered in 1cscAA123. In addition, when CP [J102 reads a block in 5U106 and stores it in B S 108 K, the block address is registered in AAllo and [8CAA112
and read the block in S U 1'22 B5
108, the block address is BA
Register with Allo and also register with 8CAA124.

In the system shown in Figure 11, reading and writing to 8U of CPU%CH is distributed to two MSUs, so one 8CA
A. For example, the registration requests and store check requests that come to 5CAA111 will be about 1/2 compared to the case in Figure 1.
8CAA for CPU101 is SCA A 111.1
Since the total throughput of the 8CAA 111 shown in FIG. 1 is approximately twice that of the 8CAA 111 shown in FIG. 1, there is no accumulation of store check requests as in the other embodiments.

(C) Part 6 M 8 U 105.121 shown in Fig. 12 combines the 8CAA configuration of M S U 1os shown in Fig. 6 and the 8 CAA configuration of M S U 105.121 shown in Fig. 11. It is something.

In other words, as 8CAA corresponding to CPU 101, M
8 U 105 has S CA A 111.131 and M 8 U 121 has S CA A 125.
133, N8U105 has S CA A 112.152 as 8CAA corresponding to CPU 102, and N8U121 has S CA A 124.134.
There is.

CPU 101 reads the block in M8106,
When storing in B 8107, the block address is registered in AA1n9, and the block address is also registered in SCA A 111 or 131.

Cut the block in S U 122 and take out B S 107
When storing the block address in BAA10
9, and 8C by its block address.
Register with AA123 or 133.

The same applies when the CPU 102 successively stores blocks in the MS 106 or 122 in the B S 10B.

In FIG. 12, for example, when CH103 writes to MS, 8 U 10<
A write request is issued to either S or 122.

Now, if a write request is issued to the MS 106, the CPU 101 will receive 8CAA depending on the write address.
A store check is carried out at 111 or 131, and the CP
For U102, the store check is performed for 5CAAi 12 or 132, so the processing capacity of 5CAA is improved four times compared to the conventional technology.

Effects of the Invention Since the structure is as described above, the following effects can be obtained in the present invention. In other words, by dividing the main memory into multiple spaces according to their addresses, and having 5 CAA on each side for each CPU in each space, 5 CA
A's registration request, store check request, multiple 8CAA
This makes it possible to increase the processing power of the 5CAA, so that the throughput when writing to the main memory is not limited by the processing power of the 5CAA, and the throughput of the main memory can be increased. Ta.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an example of an information processing system having a BS, and Fig. 2 is an example showing how to assign column addresses and row addresses of BAA, BS%M8 when the so-called congruent system is adopted. FIG. 3 is a block diagram showing an example of a column address and a registered address among storage addresses, and FIG. 4 is based on the prior art. Figure 2 shows an example of the F A A surroundings, and Figure 5 shows an example of the time chart at that time, $6
The figure is a block diagram showing an example of an embodiment of the present invention, FIG. 7 is a program diagram showing an example of the FAA, and FIG. 9 is an example time chart showing the correspondence between storage addresses and FAA at that time. , FIG. 10 is a time chart at that time, and FIG. 811 and FIG. 12 are diagrams showing other embodiments of the present invention. 1n1.102...Arithmetic processing unit 107.108...Buffer storage 109.11
0... Buffer storage address array 105 ・Main memory 1i 106... Main memory 1
03.104...Channel agent patent attorney Usui 1) O (葎1 O 1 Tomoe third mouth O L! 50 O 4 Kuni O 80 O 9 (￥1

Claims (1)

[Claims] In an information processing system that has a buffer storage between an arithmetic processing unit and a main memory that is faster and has a smaller capacity than the main memory, the main memory is divided into multiple address spaces by the address area of the main memory, and each address space is divided into multiple address spaces. A dedicated address array is prepared for each processing unit to hold the main memory addresses loaded into the buffer storage, and registration requests and store check requests to the address array are sent to the address array, store check address, and registration request. An information processing system characterized by distributing information into several address arrays depending on the source of the store check request.