JPS548937A - Buffer memory unit - Google Patents
Buffer memory unitInfo
- Publication number
- JPS548937A JPS548937A JP7463677A JP7463677A JPS548937A JP S548937 A JPS548937 A JP S548937A JP 7463677 A JP7463677 A JP 7463677A JP 7463677 A JP7463677 A JP 7463677A JP S548937 A JPS548937 A JP S548937A
- Authority
- JP
- Japan
- Prior art keywords
- memory unit
- buffer memory
- lowering
- constituting
- sections
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE: To enable to output arbitrary byte as head without lowering the performance if the desired data bridge the blocks, by constituting the address array being the major component of memory and the data buffer with two sections.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7463677A JPS548937A (en) | 1977-06-22 | 1977-06-22 | Buffer memory unit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7463677A JPS548937A (en) | 1977-06-22 | 1977-06-22 | Buffer memory unit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS548937A true JPS548937A (en) | 1979-01-23 |
Family
ID=13552881
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7463677A Pending JPS548937A (en) | 1977-06-22 | 1977-06-22 | Buffer memory unit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS548937A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5616985A (en) * | 1979-07-23 | 1981-02-18 | Nec Corp | Buffer memory unit |
JPS57172584A (en) * | 1980-12-31 | 1982-10-23 | Honeywell Inf Systems | Cash-memory |
JPS57172585A (en) * | 1980-12-31 | 1982-10-23 | Honeywell Inf Systems | Cash-memory |
JPS58185082A (en) * | 1982-04-23 | 1983-10-28 | Hitachi Ltd | Information processing system |
US6112297A (en) * | 1998-02-10 | 2000-08-29 | International Business Machines Corporation | Apparatus and method for processing misaligned load instructions in a processor supporting out of order execution |
US6434666B1 (en) | 1995-02-20 | 2002-08-13 | Hitachi, Ltd. | Memory control apparatus and method for storing data in a selected cache memory based on whether a group or slot number is odd or even |
-
1977
- 1977-06-22 JP JP7463677A patent/JPS548937A/en active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5616985A (en) * | 1979-07-23 | 1981-02-18 | Nec Corp | Buffer memory unit |
JPS57172584A (en) * | 1980-12-31 | 1982-10-23 | Honeywell Inf Systems | Cash-memory |
JPS57172585A (en) * | 1980-12-31 | 1982-10-23 | Honeywell Inf Systems | Cash-memory |
JPH0361214B2 (en) * | 1980-12-31 | 1991-09-19 | Haneiueru Infuoomeishon Shisutemusu Inc | |
JPS58185082A (en) * | 1982-04-23 | 1983-10-28 | Hitachi Ltd | Information processing system |
US6434666B1 (en) | 1995-02-20 | 2002-08-13 | Hitachi, Ltd. | Memory control apparatus and method for storing data in a selected cache memory based on whether a group or slot number is odd or even |
US6611899B2 (en) | 1995-02-20 | 2003-08-26 | Hitachi, Ltd. | Memory control apparatus and method for storing data in a selected cache memory |
US6112297A (en) * | 1998-02-10 | 2000-08-29 | International Business Machines Corporation | Apparatus and method for processing misaligned load instructions in a processor supporting out of order execution |
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