JPH0277953A - Constitution system for conversion index buffer - Google Patents

Abstract

PURPOSE:To decrease the memory elements used by a conversion index buffer TLB without affecting the working of the TLB by deleting the I and C bits of the TLB (conversion index buffer). CONSTITUTION:A TLB1 holds the data on a physical page address PPA and a space identifier SID and owns a specific space number in an SID column for a common area and an invalid TLB. A comparator 2 compares an SID of the TLB retrieved by a logical page address with a program space identifier. A decoder 3 decodes the SID of the TLB retrieved by the logical page address and produces an output when above mentioned space number is obtained. A gate circuit 4 uses the outputs of the comparator 2 and the decoder 3 as inputs produces a TLB fault signal in case no coincidence is obtained via the comparator 2 with no common area and at an invalid TLB. In such a way, the memory elements can be decreased with deletion of the I and C bits of the TLB.

Description

[Detailed Description of the Invention] [Summary] Regarding the configuration method of the translation index buffer corresponding to the multiplexed virtual memory method, the translation index buffer holds data of physical page addresses and space identifiers for the purpose of reducing the amount of hardware. In the case of an area common to all spaces or invalid data, it is configured to hold a specific space number in the space identifier field, and the space identifier in the conversion index buffer data indexed by the logical page address and the running program. A comparator that compares spatial identifiers, a logic page,
A decoder that decodes the space identifier in the conversion index buffer data indexed by the space address and generates an output when the space number is the specified space number, a comparator, and a decoder that receives the output of the decoder as input and detects a common area when the comparison results of the comparator do not match. and a gate circuit that generates an output when the data is not valid or invalid data, and is configured to output the output of the gate circuit as a conversion index buffer fault signal.

[Industrial application field]

The present invention relates to an address translation mechanism in an information processing apparatus using a virtual storage system, and particularly to a configuration method of a translation index buffer compatible with a multiple virtual space system.

[Conventional technology]

An information processing device using a virtual storage system includes a dynamic address conversion mechanism to convert a logical address (virtual address) into a physical address (real address) on a main storage device during execution of an instruction.

A dynamic address translation mechanism is usually equipped with a translation lookaside buffer (hereinafter abbreviated as TLB) to perform address translation at high speed.If the input logical address does not exist in the TLB, it is stored in main memory as a TLB fault. A necessary segment is taken out from the stored address translation table, and an unnecessary segment is expelled from the TLB and replaced.

In a computer system in which a multiple virtual space system is adopted in which a plurality of programs each have a virtual space, and an address translation mechanism is realized using a TLB, the configuration of the TLB has conventionally been as shown in FIG.

In FIG. 5, PPA is a physical page address,
SID is a space identifier that identifies an address space. ■
is the invalid TLB bit J (referred to as the I bit), which indicates whether the TLB at this address is valid or invalid;
is a common area bit J (referred to as C bit) which indicates that the space indicated by the logical address is a common area of all spaces.

■ The bit and C bit are used as follows.

As shown in FIG. 6, the space identifier SID of the TLB data indexed by the logical page address is compared with the operating program space identifier PSID by a comparator, and if there is a mismatch and the C bit is not set (common area generates a TLB fault signal. Also,
(2) When the bit is set (invalid TLB), a TLB fault signal is generated regardless of whether the SIDs match or do not match.

[Problem to be solved by the invention]

In recent computer systems, the main memory capacity has been actively increased, and the physical page address (PPA) in the TLB has accordingly increased. There is a problem in that this increase in physical page addresses also increases the capacity of the TLB.

Furthermore, as the scale of individual programs increases, there is a strong desire to increase the capacity of a single space. Furthermore, there is a desire to have a large-capacity TLB in order to increase the TLB hit rate (the rate at which TLB faults do not occur).

This demand for increased TLB capacity poses a problem in that the amount of hardware increases.

The problem to be solved by the present invention is to provide a method for reducing hardware without reducing the capacity of the TLB.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of means for solving the above-mentioned problem.

In the figure, l is a TLB (translation lookaside buffer), which holds data of PPA (physical page address) and 5ID (space identifier), and holds a specific space number in SID8 in the case of a common area or invalid TLB. .

A comparator 2 compares the SID of the TLB indexed by the logical page address and the program space identifier.

3 is a decoder which decodes the SID of the TLB indexed by the logical page address and generates an output when the specific space number is reached.

Reference numeral 4 denotes a gate circuit which receives the outputs of the comparator 2 and decoder 3 and generates a TLB fault signal when the comparison result of the comparator 2 does not match and is not in the common area, or when the TLB is an invalid TLB.

[For production]

In the present invention, the number of bits in the TLB is reduced in order to reduce the amount of hardware without reducing the capacity of the TLB.

There are two ways to reduce the number of TLB bits: (1) reducing the number of spaces, and (2) deleting the I and C bits.

However, if the SID, which is a space identifier, is simply reduced by 1 bit, the number of spaces will be halved.

Furthermore, if the I bit and C bit are to be deleted, their roles must be provided by other means.

Therefore, in the present invention, the ■ bit and the C bit are eliminated, and the common area and invalid TLB are each allocated to one space. That is, for example, in the case of a common area, all 1s are set in SID, and in the case of invalid TLB, SID is set to 1.
Set all 0 cents to the ID.

As a result, the number of usable spaces can be reduced to two spaces. For example, if the SID is 7 bits, the number of usable spaces will be reduced from 128 to 126.

In the present invention, the TL indexed by the logical page address
A decoder 3 is provided which decodes the SID data in the B data and outputs an output when these specific space numbers are present, and the output serves as the ■ bit and the C bit. The comparator 2 and gate circuit 4 may be the same as the conventional example shown in FIG.

The delay due to the decoder is generally smaller than the delay due to the comparator and this does not add any additional delay.

In this way, the TLB can be reduced by 2 bits, and by increasing the capacity per space, the reduction in 2 spaces can be compensated for.

〔Example〕

The present invention will be explained in more detail below with reference to embodiments shown in FIGS. 2 to 4.

FIG. 2 is a diagram showing the configuration of a TLB in one embodiment of the present invention.

The TLB has a 24-bit physical page address (PPA).
and a 7-bit spatial identifier (SID). The SID of the invalid TLB is set to 1111111'', and the common area is set to ``1111110''.

In this way, invalid TLB is set to 5ID="1111"
111” and the common area as 5ID="11111".
10'', these space numbers cannot be used as address space numbers, and the number of spaces that can be used is 126.

FIG. 3 is a diagram showing the configuration of an embodiment 0 of the present invention.

In the figure, 10 is a TLB.

20 is a comparator (CMP), and SI in TLB data
D and the contents of the register 50 where the running program space identifier PSID is set are compared, and if they do not match, NEQS is executed.
Output the ID.

30 is a decoder (DEC) which decodes the SID and outputs INVTLB when it is "1 oiin", and outputs "111".
1110'', outputs COMMMN.

41 is an AND gate, which connects the COMMN signal and Nu! Q
The SID signal is input.

42 is an OR gate which inputs the INVTLB signal and the output of the AND gate 41 and outputs a TLB fault signal.

FIG. 4 is a circuit diagram of a decoder and a comparator in one embodiment of the present invention.

Figure 4(a) shows the decoder circuit, which is a 7-person AND
It consists of two gates and one inverter. Input SID, output INVTLB when "1111111",
When it is "1111110", the COM interval 'N is output.

FIG. 4(b) shows the comparator circuit, which consists of seven exclusive OR circuits and seven OR gates. Each bit of SID and PSID is input to each of the seven exclusive OR circuits, and if all bits match, the output NEQSID from the OR gate is 0'', but there is at least one bit that does not match. and 1'' are output.

In the comparator circuit and decoder circuit shown in Figure 4, the exclusive OR circuit in the comparator has a delay equivalent to two stages of gates, so the maximum pass is three stages of gates, and the decoder has a maximum pass of two stages. , the comparator is slower and the decoder delay is not an issue.

The decoder circuit consists of several gates, and together with comparators etc.
Since it can be configured within the SI, the amount of hardware hardly increases.

On the other hand, since the TLB has a large capacity, the number of bits itself greatly affects the amount of hardware.

That is, the case of this embodiment is compared with the conventional case as follows.

The physical address is 32 bits, page size 4 bytes, and the physical page address is 20 bits.

The number of bits in one entry is 29 bits in the conventional example, and 27 bits in this embodiment. Increase the number of TLB entries to 6
4, the TLB capacity is 1, which is 29 pins in the conventional example)
x64K, which in this embodiment is 27 bits x 64.

If this is configured with 64K×1-bit memory elements, the number will be 29 in the conventional example and 27 in the present embodiment, which means that the amount of hardware can be reduced by about 7%.

〔Effect of the invention〕

As explained above, according to the present invention, the I bit of the TLB,
By deleting the C bit, it is possible to reduce the number of memory elements used in the TLB without affecting the operation, and the effect of reducing the amount of hardware is particularly large in the case of a large-capacity TLB.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the principle of the present invention. and decoder!
Figure 8 Figure 4 (X) +920212
2 28 Diagram showing the integrity of TLB according to conventional example Figure 5 Figure 6

Claims (1)

[Claims] In an information processing system that adopts a multiple virtual space system and configures a mechanism for dynamic address translation using a translation index buffer (1), the translation index buffer (1) is configured to handle physical page addresses and spaces. The space identifier in the conversion index buffer data indexed by the logical page address is configured to hold identifier data and hold a specific space number in the space identifier column in the case of an area common to all spaces or invalid data. and a decoder (3) that decodes the space identifier in the conversion index buffer data indexed by the logical page address and generates an output when the specific space number is reached. , a gate circuit (4) which receives the outputs of the comparator (2) and the decoder (3) and generates an output when the comparison results of the comparator (2) do not match and are not in the common area, or when the data is invalid.
A conversion index buffer configuration method characterized in that the conversion index buffer is configured to output the output of the gate circuit (4) as a conversion index buffer fault signal.