JPS5953633B2 - computer system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a computer system that can operate in either a virtual computer system mode using a multiple virtual memory method or a normal computer system mode using a multiple virtual memory method. The present invention relates to a computer system in which the number of bits of a space identifier is increased in a computer system mode, thereby reducing the number of times a translation lookaside buffer (hereinafter referred to as TLB) is purged.

TL of a virtual computer system that uses multiple virtual memory method
Each entry in B contains a virtual machine identifier (hereinafter referred to as VM-
ID), space identifier (hereinafter referred to as space ID),
Logical address and system absolute address are entered.

The VM-ID identifies which virtual computer the logical address belongs to, and the space [D] identifies which virtual space the logical address belongs to. Note that the logical address and system absolute address of the TLB are for pages. When a virtual machine accesses memory using a logical address, the TLB is indexed, and if a corresponding entry exists, the main memory is accessed using the system absolute address of this entry. A computer system that can operate on a virtual computer system using a multiple virtual memory method is sometimes operated on a normal computer system using a multiple virtual memory method (a system that is not a virtual computer system). 71) The VM-ID field is invalid. By the way, if the number of bits of the space ID of the TLB entry is small and the number of virtual spaces that can be specified is small, the TL
It is desirable to increase the number of bits of the space ID since the number of times that B is changed from time to time increases.

The present invention is based on the above considerations, and provides a computer system that can operate in either a virtual computer system mode using a multiple virtual memory method or a normal computer system mode using a multiple virtual memory method. It is an object of the present invention to provide a computer system that can reduce the number of TLB purges when operating as a normal computer system compared to the conventional system.

To that end, the computer system of the present invention provides an address translation index buffer having a plurality of entries having an m-bit first identifier field, an n-bit second identifier field, a logical address field, and a system absolute address field. In a virtual computer system using a multiple virtual memory system, the spatial identifier generation circuit generates an m-bit virtual machine identifier for identifying a virtual computer, and also generates a segment.
It is configured to generate an n-bit space identifier based on the table starting address, write an m-bit virtual machine identifier into the first identifier field, and write an n-bit space identifier into the second identifier field. In a normal computer system using a multiple virtual memory system, the space identifier generation circuit generates an m+n bit space identifier based on the segment table starting point address, and m of the m+n bit space identifier.
Write the bit part into the first identifier field,
The present invention is characterized in that the remaining n bits can be written into the second identifier field. Hereinafter, the present invention will be explained with reference to the drawings. FIG. 1 is a diagram explaining the allocation of main memory in a virtual computer system, FIG. 2 is a diagram illustrating an example of an address translation mechanism according to the present invention, FIG. 3 is a block diagram of an example of an identifier generation circuit, and FIG. The figure is a diagram illustrating the expansion of space 1D in a normal computer system.

As shown in Figure 1, VM#1 is used for each of the virtual machines M#1, VM#2,...VM#1.
Region, VM#2 region, . . . VM#i region is given.

The VMM region is assigned to a virtual machine monitor. The VMM region is divided into a VMM prefix area and a VMM program area. VM#
The i region is also divided into an M#i playfix area and an M#i program area. The system absolute address is an address used by the program that manages the host machine (VMM program), and is used to access all areas of the host machine's main memory (including the VM program area and VM playfix area). It is possible. A region absolute address is a region given to a virtual machine, starting with the start address 101, and continuously addressing the system absolute address in the direction of increase.The region absolute address corresponds to the maximum allocated system absolute address. This address is assigned so that the end address is the end address, and is the lowest level address that can be recognized by the M program. The start address of the VM#i region assigned to virtual machine M#i is set in the region base address register RBA, and its final address is set in the region limit address register RLA.
is set to . FIG. 2 shows an address translation mechanism that translates logical addresses into system absolute addresses.

In Figure 2, 1 is TLB12 is an address register, 3 to 5 are comparison circuits, 6 is an AND circuit, and 7 is a DAT.
Address conversion processing unit using a table; 8 is a prefix processing unit; 9 is an adder; 10 is a region base address register; 11 is a read register; 12 is a control register; 13 is an extended control register; 14 is an identifier generation circuit; 15 indicates output registers, respectively. Also, A
U indicates the upper part of the logical address, AM the middle part, AL the lower part, SAU the system absolute address, and ID-0 and ID-1 the identifiers, respectively. The address part AL is an address within the page, and the system absolute address SAU is for the page. When the computer system operates as a virtual machine system using multiple virtual memory, VM-1D for identifying the virtual machine is written in the ID-1 field of TLB1, and ID-1 is written in the ID-1 field of TLB1.
A space [D] for identifying the virtual space is written in the 0 field.

Control register 12 is a segment table starting point address register. The extended control register 13 stores virtual machine instruction information that uniquely specifies a virtual machine. The identifier generation circuit 14 has a configuration as shown in FIG. In FIG. 3, 16 is an STO stack;
7 is a hatch circuit, 18 and 19 are comparison circuits, 20 is an AN
A circuit D is shown. When operating as a virtual computer system using multiple virtual memory, D-0 becomes space 1D and ID-1 becomes VM-ID, but VM-1D is limited to hashing the contents of extended control register 13. The space D is generated by hashing the contents of the control register 12. The hashing circuit 17 performs the above-mentioned hashing process, and the output of the hashing circuit 17 is set in the output register 15. The output of hashing circuit 17 also indicates the entry address of STO stack 16. The entries in STO stack 16 include:
The contents of control register 12 and extended control register 13 are written. When the contents of the control register 12 and extended control register 13 are changed, the STO stack 16
If the contents of control register 12 and extended control register 13 do not match the contents of control register 12 and extended control register 13, a TLB purge command is sent to TLB1, and an entry with the same identifier as the contents of output register 15 is sent. is purged. The DTA table-based address conversion processing unit 7 converts logical addresses into real addresses using segment tables and page tables. By prefixing the real address obtained by the address conversion processing section 7, a region absolute address is obtained, and the RBA register 1 is added to the region absolute address.
By adding the contents of 0, the system absolute address is obtained. When the virtual machine accesses the main memory using a logical address, data is read from TLB1. This read data is compared with the contents of the corresponding registers 2 and 15 by comparison circuits 3 to 5, and if they match, it becomes TLBFUND, and the system absolute address SAU read from TLB1 is used. T.L.B.
In the case of NOTFOUND, the address conversion processing section 7, prefix processing section 8 and adder 9 are used to convert the logical address into a system absolute address. If the computer system operates as a normal computer system using virtual memory, the ID-0 field and ID of the TLB
The −1 field is assigned to space D.

Assuming that the D-0 field has an m-bit configuration and the D-1 field has an n-bit configuration, in the normal computer system mode with multiple virtual memory, the hashing algorithm of the hashing circuit 17 in FIG. This change makes it possible to generate an m+n bit space 1D that can take on 2m+n patterns based on the contents of the control register 12. Note that in the case of the normal computer system mode, the extended control register 13 is disabled. Figure 4 shows
This indicates the status of the ID-0 field and ID-1 field of the TLB entry in a virtual computer system using a multiple virtual memory method and in a normal computer system using a multiple virtual memory method. In the system (VM system), D-1
VM-1D is written in the field.

In a normal computer system with multiple virtual memory,
The upper part of space 1D is written into the ID-0 field, and the lower part of space D is written into the ID-1 field. As is clear from the above description, according to the present invention,
In a computer system that generates an m-bit space 1D and an n-bit VM-1D in a virtual computer system using a multiple virtual memory method, the above-mentioned VM-1D becomes unnecessary in a normal calculation system using a multiple virtual memory method. Focusing on this, and using the bits used in VM-1D,
Since the bit width of the space 1D of the TLB entry is expanded, it is possible to increase the number of virtual spaces that can be identified in the space 1D compared to the conventional method. The number of times can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining main memory allocation by a virtual computer system, FIG. 2 is a diagram illustrating an example of an address translation mechanism in the present invention, FIG. 3 is a block diagram of an example of an identifier generation circuit, and FIG. The figure shows space 1D in a normal computer system.
It is a figure explaining expansion of. 1...TLBl2...Address register, 3 to 5...Comparison circuit, 6...
・AND circuit, 7...Address conversion processing unit based on DTA table, 8...Prefix processing unit, 9...Adder, 10...Return unit・Base address register, 11... Read register, 12... Control register, 13...
- Extension control register, 14...Identifier generation circuit, 5...Output register.

Claims (1)

[Claims] 1 an address translation index buffer having a plurality of entries having an m-bit first identifier field, an n-bit second identifier field, a logical address field, and a system absolute address field, and an identifier generation circuit; In the case of a virtual computer system using a multiple virtual memory method, the space identifier generation circuit generates an m-bit virtual machine identifier for identifying a virtual machine, and also generates an n-bit space identifier based on the segment table starting point address. In a computer system configured such that a bit virtual machine identifier can be written in the first identifier field and an n-bit space identifier can be written in the second identifier field, in a normal computer system with multiple virtual memory system, the above The space identifier generation circuit generates m+n based on the segment table start address.
A bit space identifier is generated, and an m bit part of the m+n bit space identifier is written in the first identifier field, and the remaining n bit part is written in the second identifier field. A computer system featuring: