JP2000267932A - Tag address comparing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption needed to read and write an inputted tag address and perform comparing operation by providing a retrieving means, etc., which retrieves the entry matching the tag address inputted from a central processing unit from an entry storage means. SOLUTION: The device is equipped with the entry retrieving means, etc., which retrieves the entry matching the tag address inputted from the central processing unit from the entry storage means. This comparing device controls the latch timing of an inputted virtual page number by setting a tag comparison enable bit so that the virtual page number is neither read out of nor written to an area set as a comparator non-operation area with the tag comparison enable bit and a comparator gives no variation to an inputted signal. An address converting buffer 1 including this tag address comparing device is formed in a package forming the central processor 3 and connected to a control register 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a cache device which is a temporary storage device for instructions and data in a main memory. In particular, the present invention relates to a tag address comparison device that compares a tag address whose input timing of a tag address input from a central processing unit is partially controlled according to a tag comparison enable bit with a tag address set in a cache entry.

[0002]

2. Description of the Related Art Recently, microprocessors having a cache memory mounted on a chip have become mainstream in order to eliminate a bottleneck in memory access. In particular, the virtual memory system is widely adopted as a technique for reducing the programming load by coping with the limit of the main memory capacity of a computer. The virtual memory logically realizes a large-capacity main memory by forming a large-capacity virtual memory by controlling an operating system or the like to supplement a memory capacity in a main memory and an auxiliary memory such as a hard disk. . In addition, when virtual storage is employed, only data necessary at the time of operation of the program can be stored in the main memory, so that the memory can be efficiently shared between a plurality of programs. In virtual storage, address conversion is required to convert a virtual address indicating an address in the virtual memory into a physical address indicating an actual address in the main memory. Generally, a virtual address is divided into a virtual page number and an intra-page offset, and a physical address is also divided into a physical page number and an intra-page offset. In the address conversion, a page table for storing a virtual page number and a physical page number in association with each other is provided, and the physical page number is extracted from the requested virtual address with reference to the page table to obtain the physical address. And convert. Since the virtual address and the physical address have the same intra-page offset, a physical address is generated by concatenating a predetermined intra-page offset to the physical page number. By the way, this page table is very large and needs to be stored in the main memory. Therefore, every time there is a request for access to the main memory from the central processing unit, there are two accesses, one for accessing the page table and the other for accessing actual data.
Access to the main memory is performed twice, resulting in a delay in processing time. In order to improve such a processing time delay, in recent years, an address translation buffer (hereinafter, referred to as “TLB”) has been provided in addition to the page table. The TLB is a cache memory dedicated to address conversion that stores a correspondence between a frequently used virtual page number and a physical page number in a page table. TL
In the case where B is provided, when the central processing unit accesses the main memory, the TLB is searched first. If the page number of the input virtual address is in the entry of the TLB, the TLB is searched. It can be converted to the corresponding physical address at high speed. If there is no virtual address to be found here, the page table in the main memory or the like is searched. The efficiency of access to the main memory can be improved by appropriately determining the storage content of the TLB and increasing the hit rate of the TLB. However, this T
In order to improve the performance of the processor and to eliminate the bottleneck of the memory access, the LBs having the number of entries of 32 to 64 are becoming mainstream. Since TLB generally uses a fully associative associative memory, the area occupancy of the chip is increasing year by year, and the power consumed by the entire on-chip cache is about 30% of the power consumed by the chip. Due to the occupation, the necessity of reducing the chip size and reducing power consumption has arisen. For example, (Reference: Hitachi SH
From the microcomputer specifications), Hitachi's SH series employs a set associative method as a configuration of cache memory. As a method of reducing power consumption, when set to a low power consumption mode, The number of ways is reduced, and the same operation as in the direct map method is performed. In such a low power consumption mode, the cache capacity decreases and the degree of association decreases, so that the miss rate increases and the performance decreases, but the power consumption can be reduced.

[0003]

However, in the method of reducing the capacity of the cache operating to reduce the power consumption as in the above-described low power consumption mode, the cache miss rate increases, so that the access to the external memory is not performed. Power consumption may increase as a result of the increase in execution time due to performance degradation. The same can be said for the address translation buffer. When the number of entries in the address translation buffer that operates to reduce power consumption is reduced, the miss rate of the address translation buffer increases, so that access to the main memory increases. The power consumption may increase. An object of the present invention is to use a cache entry as it is in a cache including an address translation buffer, without lowering the cache miss rate, and at the time of tag address comparison, without partially changing an input tag address, Further, it is an object of the present invention to provide a tag address comparing device that reduces the operating range of the tag address comparator, thereby reducing the power consumption required for reading and writing the input tag address and comparing operation compared with a commonly used cache. It is.

[0004]

According to a first aspect of the present invention, there is provided a tag address comparing apparatus for storing a plurality of entries in which data is recorded in association with each tag address. A tag address storage unit for storing a tag address input from a central processing unit with respect to the first tag address; and a tag for partially controlling a tag address input timing from the central processing unit in the tag address storage unit. An address input control unit and a tag address comparison unit that compares the second tag address with the first tag address stored by the entry storage unit generate a tag address comparator non-operating area, and always partially Minimize signal changes to a part of the second tag address storage area that holds a constant value Thus, a structure is such that power consumption is minimized, a hit signal is always output, and for a tag address input from the central processing unit, an entry that matches this tag address is stored in the entry storage. And an entry search means for searching by means. In the tag address comparison device according to claim 2,
The tag address input control means is provided in the tag address storage area, and the tag address input control means uses a tag comparison enable bit composed of a plurality of bits. In the tag address comparing device according to the third aspect, in addition to the tag address comparing device according to the first or second aspect, the tag address comparing device of the tag address set to be unnecessary to be compared by the program can be used. And a tag expected value determining means for determining whether the program correctly uses the value of "0". In the tag address comparison device according to the fourth aspect, the entry of the first tag address corresponding to the second tag address set as the comparator non-operation area by the tag comparison enable bit according to the second aspect Only physically implement. In the tag address comparing device according to a fifth aspect, in the tag address comparing device according to the third aspect, the first tag address corresponding to the second tag address set as the comparator non-operation area by the tag expected value determining means.
Physically implement only the tag address entry.

[0005]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a TLB 1 including a tag address comparing device according to the present embodiment.
The TLB 1 is provided in a package forming the central processing unit 3 and includes a memory element that can be accessed at high speed with the central processing unit 3 and is controlled by operating software and a control circuit. Also, TLB1
Is connected to the control register 2 for storing the process identifier PIDc of the currently executing process. The control register 2 is rewritten each time the central processing unit 3 switches the execution process. These devices are incorporated in a general computer system. The TLB 1 stores a plurality of entries e1, e2, e3,... E32 which store a virtual page number and a physical page number in association with each other.
Each entry storage unit is divided into a tag unit 10 storing a virtual page number and the like and a data unit 14 storing a corresponding physical page number and the like. Further, the data section 14 of all entry storage sections is arranged in the data array section 1b of the TLB1. The tag section 10 is a virtual page number storage area 10
1, a process identifier storage area 102, a global bit storage area 103, and a valid bit storage area 104, and a virtual page number VPN, a process identifier PID, a global bit G, and a valid bit V are stored in the respective storage areas. A virtual address input unit 11 to be compared with each virtual page number stored in the tag unit 10 stores a virtual address consisting of a virtual page number X input from the central processing unit 3 and an offset. A tag comparison enable bit storage area 111 for storing a tag comparison enable bit TE for specifying whether or not the virtual page number output from the central processing unit, which is input to the storage area 112, is input to the virtual page number storage area X. You.

Here, the tag comparison enable bit TE
Uses 4-bit information and has only a pair of storage areas for the page number of the virtual address input from the central processing unit.

A specific process is represented by using a plurality of bits of information as a process identifier. The global bits serve as comparison information that defines the comparison and no comparison of the process identifier. The valid bit V is provided in consideration of a case where the physical page number and the virtual page number in the entry do not correspond to each other when the central processing unit 3 is reset by a program. If it is active, it indicates that the physical page number in the current entry correctly corresponds to the virtual page number, and if it is inactive, it indicates that they do not correspond appropriately. The tag comparison enable bit 111 serves as input control information for controlling the input timing of the virtual page number storage area X constituting a part of the virtual address X requested by the central processing unit 3. Also, the tag comparison enable bit 11
A virtual page number comparator 12 as a virtual page number comparing means for comparing the virtual page number vpn inputted from the central processing unit 3 with the virtual page number VPN in response to 1.
The process identifier PIDc of the process currently in progress sent from the control register 2 and the process identifier storage area 1
There is provided a process identifier comparator 13 as a process comparison means for comparing the process identifier PID stored in H.02 with the value of the global bit G. The output value of the virtual page number comparator 12, the output value of the process identifier comparator 13, and the effective bit storage area 1
04 is stored in the AND gate 10
5 is ANDed. The first comparator 12 and the second comparator
The signal value "1" is output from the AND gate 105 only when the comparison result of the comparator 13 matches and the valid bit is active, that is, only when an appropriate virtual page number exists. The virtual page number comparator 12 and the AND gate 105 constitute an entry search unit. The output value of the AND gate 105 is sent to the data section 14 and also to the OR gate 15, where the OR gate 15 performs a logical OR operation on the output values of all the AND gates 105. The output signal value “1” of the OR gate 15 is output as a hit signal, and the output signal value “0” is output to the central processing unit 3 as a miss signal. The data section 14 has a physical page number storage area 141, a page attribute storage area 1
The storage area stores page attribute information such as a physical page number PPN, a page protection bit PR, a dirty bit D, and a page valid bit PV. In the data section 14, when the output value “1” is sent from the AND gate 105, the physical page number PPN stored in the physical page number storage area 141
Is output. The output physical page number PPN is linked to the in-page offset and sent to the central processing unit 3 as the physical address Y.

FIG. 2 is a block diagram showing the configuration of the virtual page number comparator 12. The virtual page number comparator is input to each comparator for each bit with respect to the virtual page number X input from the central processing unit and the virtual page number 101 of each entry, and outputs the output of each tag comparator as an input. AND
It is composed of a gate 123.

FIG. 3 is a block diagram showing a configuration of a virtual page number storage area X used in a general computer system. A signal 303 in which the virtual page number X input from the central processing unit 3 is output as the logical product of the clock 301 and the latch enable signal 302
The input timing is controlled by the CPU and stored in the virtual page number storage area X. However, in the present invention, unlike the virtual page number storage area X in FIG. 3 used in a general computer system, the virtual address input unit configured in FIG. 1 for performing input control according to the tag comparison enable bit 11 is constituted. FIG. 4 is a block diagram showing a configuration of a virtual page number storage device using a tag comparison enable bit. For the 20-bit virtual page number input from the central processing unit 3, the upper 2 bits and the lower 1
For 0-bit virtual page numbers X1 and X6,
It has the same configuration as the general virtual page number storage area shown in FIG. However, regarding the virtual page number X2 of the upper 3 bits and the upper 4 bits, the output of the logical product 403a of the clock 401 and the latch enable 402 and the tag comparison enable bit TE1 are input to the AND gate 403b, and the output of the AND gate 403b is virtual. It is a data fetch control signal for the page number storage area X2. Similarly,
4 for the virtual page number storage areas X3, X4, X5
Data is taken in by the output control signals of the AND gates 03c, 403d and 403e. With this configuration, when the tag comparison enable bit TE is inactive, A
Since the output of the ND gate is always "0", the virtual page number from the central processing unit is not input, and the data in the virtual page number storage area does not change. That is, in the configuration of FIG. 3, even when the same signal is input from the central processing unit, power is consumed because the input control signal fluctuates in synchronization with the clock. In the configuration, the virtual page number is fetched as in the normal operation only when the tag comparison enable bit is "1", and when the tag comparison enable bit is "0", the value is always a constant value and the input control signal does not switch. Means that little power is consumed. The reason why the power consumption is small is that either the PMOS or the NMOS is shut off at the time of rest and only a small leak current flows, and almost no current flows as a whole.

Next, a description will be given of a setting example of memory mapping necessary for realizing the present invention. Now, consider the allocation of the memory area of a certain process as shown in FIG. Here, since the description is made using a 32-bit virtual address, the virtual memory space has a 4 GB memory space. Further, in the address translation apparatus described so far, when performing the address translation, the virtual page numbers are compared and the process identifiers are compared at the same time. That is, this means that address conversion is performed only for the same process as the currently running process. Also, if there is another process that can share the memory area between the processes, by setting the global bit to the active state, if the virtual page numbers match during address translation,
Address conversion can be performed without comparing process identifiers. In this way, mapping the memory space from the virtual memory space to the physical memory space according to the process identifier is not a single virtual address space as shown in FIG. Means that a multiple virtual address space having a 4 GB memory space is used for each process as shown in FIG. In other words, in the case of a single virtual memory space, as shown in FIG. 5A, the memory mapping of each process is assigned as shown in each hash, but it is not desired that different processes share the same memory area. Although a memory area must be shared, a multiple virtual address space can have a virtual memory space for each process as shown in FIG. 5 (b). You may. Therefore, it can be seen that a huge memory space as large as 4 GB can be further handled independently between processes, so that the logical memory space can be greatly expanded logically. However, most programs actually created have a memory capacity of about several MB even when a large memory capacity is required, and a memory space of as much as 4 GB is not necessarily required to create each program.
In the present invention, an address translation device is used by effectively utilizing this multiple virtual address space. For example,
Assume that a mirror space is created without uniformly using a memory space of 4 GB as shown in FIG. The mirror address space will be described with reference to FIG. For example, consider an 8-bit virtual address space. The 8-bit address space is a 256B memory space. Suppose now that a page table is created for an 8-bit address with a page size of 16B (4 bits) as shown in FIG. 6B and the address is converted. Here, an example is shown in which address conversion is performed from a 256B virtual memory space to a 32B physical memory space. The 0x80 address (8 bits wide) is mapped to 0x10 (5 bits wide), and the 0x10 (8 bits wide) address is 0x10
A page table that is mapped to 00 (5 bit width) is created in advance. Here, it is assumed that no particular mapping is performed for the address of 0xc0. However, if the address conversion is performed without considering the third bit of the virtual page number in this address conversion, 0x80 (page number 1000) and 0xc0 (page number 1100) have the same virtual page number (1? 00). Is assumed to have been accessed, and is mapped to 0x10 (? Is not considered as a comparison target during address translation). When a memory map is created based on this idea, a configuration as shown in FIG. 6C is obtained. As described above, performing the address translation without considering a certain bit creates a virtual memory space mapped to the same physical space in the memory space. That is, 0
x80-0x8f address space and 0xc0-0xcf
Address space represents the same address space. Similarly, for other addresses, FIG.
Is mapped (mirror) to the same physical space with respect to the same hash area. By making effective use of this concept, FIG. 7 shows an example in which the same applies to a 32-bit address. Here, a case is considered where no distinction is made between the upper 5 bits and the upper 8 bits. By doing this, actually 0x *? ****
* (? Is a bit area that is not compared during address translation,
* Indicates an arbitrary value).

In the 32-bit address space, the value of the upper 4 bits is 0x00000000-0x0ffffff.
If f is considered as one area, 4G
The memory space of B can be classified into 16 areas. In addition, each of these areas is further divided into 16 bits with 4 bits from the upper 5 bits to the upper 8 bits. Here, the second upper 4 bits are fixed to 0 and used. That is, each one of the 4 GB memory space
It is assumed that only the first one of the sixteen divided areas is used among the sixteen divided areas. By doing this, 0x80000000-0
Using only the x80ffffff area, the subsequent 0x8
For the 15 areas after 1,000,000-0x81ffffff, 0x80000000-0x80ff
It exists as a mirror of ffff. In an actual program, the address space is determined by the upper few bits,
Taking advantage of the fact that the lower few bits are used to specify a detailed address area and the middle few bits are relatively unused in specifying an address area in a program, TLB and the like can be obtained by the above memory mapping. When comparing tags, always use the upper 5 bits to the upper 8 bits
Bits always have 0s. When the actual address conversion is performed, the virtual page number vpn input from the central processing unit and the virtual page number VPN set in each entry are always compared with a fixed value 0, and the TLB relating to the bit is compared. Tag comparison need not be performed. In the present embodiment, four bits are used as the tag comparison enable bit TE, and each bit is the upper third, fourth, upper fifth, sixth, and upper seven bits of the virtual page number input from the central processing unit. , 8th bit and upper 9th and 10th bits.
Furthermore, if the tag enable bit TE is set to 1001 during the above memory mapping, the upper 5 to 8 bits of the virtual page number vpn are not input. In the virtual page number comparator 12 of the TLB 1, four bits from the upper 5th bit to the upper 8 bits are fixed to always hit. That is, the signal is set so that the four bits are always active. Thereby, the input virtual page number vpn
In the upper 5th to 8th bits in the middle, the above-described portion of the second tag address storage area does not operate even when the tag address is input from the central processing unit that changes every moment, and the signal value of the storage area may change. Absent. Further, since the signal values of the comparators for all entries corresponding to the four bits of the first comparator do not change, power consumption can be significantly reduced. A tag comparison enable bit for the effective use of the memory space and the hardware, and a virtual page number storage area vp for suppressing a signal change to reduce power consumption
by using n. In effect, a TLB that requires a tag comparison for only certain bits can be created. As a result, it is possible to reduce the power consumption required for tag comparison and reading / writing from / to the tag storage area. Similarly, considering how this affects the page table, it can be said that, in the entries registered in the TLB, the upper 5th to 8th bits of the virtual page table are always 0. Since this is known, it is not necessary to have information on these 4 bits when performing the tag comparison operation in the TLB and when performing a table walk to search the page table in the main memory. A hit signal can be issued without this. In this case, the virtual page number storage area 804 and the virtual page number 804 are used in accordance with the value of the tag comparison enable bit 801 by using the circuit described in FIG. By fixing the signal of the comparator 802, the power consumption required for tag comparison can be reduced without changing the signal of the tag comparator for the area 804 in which the constant value of the virtual page number will always be set. Since the main memory does not need to have information on these bits, the memory capacity for managing the page table can be reduced.

In this embodiment, the memory-mapped program shown in FIG. 7 is stored in the memory shown in FIG.
By using the tag address comparison device, the associative memory of the address conversion buffer is operated for bits that do not need to be compared due to the mirror space when the physical address is converted to the virtual page number sent from the central processing unit. Address conversion can be realized as before without any problem. However, virtual storage has two major advantages. First, as described above, a program can be created on the assumption that there is a logically larger memory space without being limited to the physical memory space. Another is to efficiently share the memory space among multiple programs. Of course, at the time of compiling the program, it is not known which program and which program will share the physical memory. In fact, programs that share physical memory may change dynamically during execution of the program. Therefore, we want to compile each program into its own address space. Here, the unique address space means that a memory space is separately allocated to each program, and only that program can access the space. However, a single physical memory is shared by a plurality of user programs. Further, the operating system also shares physical memory. Therefore, it must be possible to protect one program from breaking another program. As described above, the virtual memory has both a function of converting an address space unique to each program into a real address space and a function of protecting the address space of another program. However, in the present invention, since the virtual page number comparator is improved as shown in FIG. 4 and a mirror of the virtual address is created, there is a possibility that unauthorized access to the mirror area may occur due to a bug in a program or the like. That is, this method cannot sufficiently satisfy the function of memory protection. Because the TLB is operated on the assumption that the upper 5 bits to the upper 8 bits are 0 in the TLB tag comparison, if the address is not illegally compared due to a program bug or the like, Even when an access is made with an address having an unexpected value, the address conversion is executed, and the memory is illegally accessed due to incorrect address generation. That is, as in the example of FIG. 6, the page table is set so that the address conversion is performed to 0x10 for the virtual address of 0x80, but 0xc0 is not set. However, when the circuit of FIG. 4 is used, a virtual address of 0xc0 which should not be mapped is also mapped to a physical address of 0x10. That is, a memory area is infringed by unintended access. This impairs the function of another area of virtual storage, that is, protection of a storage area. In order to solve this problem, the present invention further adds a function as shown in FIG. In FIG. 9, the tag enable bit 901 is set in each entry of the TLB on the assumption that the upper 5 bits to the upper 8 bits are 0. However, as described above, it is not necessary to use a comparator to determine whether a value of “0” is correctly used as an operating system for a bit for which tag comparison is not performed. Since it is used, the determination can be made based on the output of the signal 905 obtained by calculating the logical product of the inverted signal of the tag comparison enable bit 901 and the signal output from the central processing unit. When this output becomes "1", it means an access exception. That is, regarding TE1 in which the tag comparison enable bit 901 is active, since TE1 is "1", the inverter 90
4a, it changes to “0”, and this is the AND gate 90
The output is always "0" when it is input to 5a and 905b. That is, here, since the signal is always input, the above illegal access does not occur. In addition, TEb is changed to “1” through the inverter 904b,
This is input to AND gates 905c and 905d.
Since the output of the AND gate at this time is determined by the other signal X3, if the address "1" assumed by the program is used, the AND gate 905 is used.
The outputs of c and 905d become "1". That is, an access exception can be detected. Therefore, these outputs 905a, 905a
05b, 905c, 905d, 905e, 905f, 9
By taking the logical sum of 05g and 905h, it can be determined whether or not there is an access exception. The tag expected value determination means 906 is not necessary for each entry of the TLB. This increases the number of AND gates for several bits, but the operation limitation of the comparator for all entries can still be realized. Please note that. Basically, this signal is always set to 0, and the contents of the tag expected value comparator 705 do not change as long as normal access is performed, so that almost no power is consumed. If there has been an unauthorized access, the tag expected value comparison result issues a miss signal 706 to inform the operating system that an access exception has occurred. By doing so, it is possible to reduce the power consumption of the address translation device described above without losing the original performance of the virtual storage.

FIG. 10 shows a tag address comparing device including a tag expected value determining means. More ultimately, FIG.
In the case where memory mapping is performed on the address conversion buffer shown in FIG. 8 according to the purpose as in 1 and hardware is mass-produced accordingly, tag comparison is performed instead of not performing tag comparison. Only things can be physically implemented. Similarly, in the case where memory mapping is performed for the address translation buffer shown in FIG. 10 as shown in FIG. 12 according to the purpose and hardware is mass-produced accordingly, tag comparison is not performed. Only those that perform tag comparison can be physically implemented. In this way, unnecessary tag memories can be reduced, so that the total power consumption required for the deleted tag memories can be reduced, and further, the area can be reduced and the chip size can be reduced.

Although the embodiment of the present invention uses an address translator, the present invention can also be applied to a tag address comparing device using a cache. Also, the number of tag comparison enable bits is 4 bits,
Although the tag address storage means having the tag address input control means is used for 8 bits, the number is not limited to this.

[0016]

According to the above description, the present invention has the following effects.

First, the tag address comparison device according to the first aspect controls the latch timing of the virtual page number input by setting the tag comparison enable bit, and sets the comparator non-operable area by the tag comparison enable bit. The power consumption can be suppressed by reading and writing the virtual page number to and from the input area and making the comparator not change the input signal. In particular, with respect to the tag address storage means for the comparator non-operating area, in the conventional device, even when the same signal is input, the signal for controlling the input timing is input in synchronization with the clock, so that the change in the signal causes However, as for the tag address storage means used according to the present invention, the input control timing is fixed for the storage device disabled by the tag comparison enable bit. Power consumption does not occur. Further, as for the tag address comparison operation, the same "0" signal is always compared as long as the operation is normal, and there is no change in the signal, so that power consumption can be reduced.

According to the address translation device of the third aspect, the power consumption can be reduced, and a value other than the value assumed by the program in the non-comparison area of the virtual page number due to a bug in the program or the like. Even when an illegal access is made using the value, an access exception can be detected without using a comparator, and the function of memory protection inherent in the virtual storage device can be exhibited.

In the address translation device according to the present invention, since the tag comparison enable bit is input to the virtual page number storage area, the tag comparison enable bit is set to non-active after inputting this signal. Power is hardly consumed for the virtual page number storage area.

In the address translation device according to the fourth or fifth aspect, the tag memory for address translation only needs to be mounted in a necessary area, so that not only the power consumption of the chip can be reduced, but also the chip area can be reduced. You can also
This leads to improved cost performance.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a tag address comparison device according to an embodiment.

FIG. 2 is a block diagram showing a configuration of a general tag address comparator.

FIG. 3 is a block diagram showing a configuration of a general tag address storage unit;

FIG. 4 is a block diagram showing a configuration of a tag address storage unit using a tag comparison enable bit;

FIG. 5 is a conceptual diagram of a single virtual address space and a multiple virtual address space.

FIG. 6 is a diagram schematically illustrating an example of performing address conversion in a virtual address space.

FIG. 7 is a diagram schematically illustrating an example of allocation of a virtual address space using a mirror space;

FIG. 8 is a block diagram of a tag address comparing unit shown in FIG. 1;

FIG. 9 is a block diagram in which tag expected value determination means is inserted into the tag address storage means shown in FIG. 1;

FIG. 10 is a block diagram in which tag expected value determination means is inserted in the tag address comparison unit shown in FIG. 8;

11 is a block diagram showing a configuration in which only a tag memory unit that is not a non-comparison area is mounted on the tag address comparison unit shown in FIG. 8;

12 is a block diagram showing a configuration in which only a tag memory unit that is not a non-comparison area is mounted on the tag address comparison unit shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 TLB 2 Control register 3 Central processing unit 10 Tag part 11 Tag address input part 12 Tag address comparator 13 Process identifier comparator 14 Data part 101 Virtual page number storage area 102 Process identifier storage area 103 Global bit storage area 111 Tag comparison enable Bit storage area 141 Physical page number storage area 906 Tag expected value determination means

Claims (5)

[Claims] 1. An entry storage means for storing a plurality of entries in which data is recorded in association with each tag address, and a second tag address input from a central processing unit for the first tag address. A tag address storage means, a tag address input control means for partially controlling a tag address input timing from a central processing unit in the tag address storage means, the second tag address, and a tag address stored in the entry storage means. A tag address comparing device, comprising: a tag address comparing unit that compares the first tag address with the first tag address; 2. The tag address according to claim 1, wherein said tag address input control means is provided in said second tag address storage area, and said tag address input control means is a tag comparison enable bit composed of a plurality of bits. Comparison device. 3. In an area of a second tag address where input update is not performed based on the tag comparison enable bit,
3. The tag address comparison device according to claim 1, further comprising tag expected value determination means for determining whether the program uses a value of "0" correctly. 4. The tag address comparing device according to claim 1, wherein the first tag address storing means determines that it is necessary to compare a plurality of entries based on the tag comparison enable bit. Tag address comparison device that only implements. 5. The tag address comparing device having the tag expected value determining means according to claim 3, wherein the tag expected value determining means determines that a plurality of entries need to be compared. 3. The tag address comparison device according to claim 1, wherein only the storage unit is implemented.