JPS62126447A - Address conversion method - Google Patents

Abstract

PURPOSE:To reduce the capacity of a transferring image table for converting a logical address to a cache address by making the same logical address correspond to data on a physical address to be used among respective jobs in common. CONSTITUTION:An arithmetic unit 11 inputs a logical address 12 to a cache transfer image table address converting circuit 13 to obtain a cache address 14 directly. In such a case, the same logical address is made to correspond to the data on the physical address to be used among respective jobs in common and these plural transfer image tables are formed on one physical address space, so that the part to be used by respective jobs in the transfer image tables in common can be prevented from being overlapped. Thus, the capacity of the transfer image tables can be sharply reduced by the prevention of overlap.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an address conversion method for accessing data in a storage device provided in an information processing device.

[Conventional technology]

Generally, in an information processing device, a predetermined work (job)
When executing a job, programs and data necessary for executing this job are stored in advance in a storage device for arithmetic processing such as a main storage device.

Furthermore, since there is no essential difference between the program and the data,
In the following, both will be referred to as data.

The job is composed of a series of work procedures, and each step of the work is given a number that identifies that step. This number is called a logical address. Jobs are executed in the order of logical addresses, and these logical addresses are also used for instructions such as so-called jump instructions within the job.

On the other hand, a storage device for arithmetic processing is assigned a physical address that specifies the data stored therein, for example, in units of one byte.

In executing arithmetic processing, the arithmetic device accesses data stored in the physical address corresponding to the logical address of the job according to the flow of the job, and proceeds with various processing.

In order to associate this logical address with a physical address, table data generally called a mapping table is created. In arithmetic processing, address conversion is performed while referring to this mapping table to obtain target data.

Here, if the storage device for arithmetic processing has a large capacity, the time required for address conversion and access becomes so long that it cannot be ignored, which impedes speeding up of arithmetic operations. Therefore, a method has been adopted in which data that is currently undergoing calculation processing or a portion of data that is likely to be used is transferred to another small-capacity memory, and this memory is accessed to perform calculations. This memory is called a cache memory, and each piece of data is stored in a location specified by a cache address. During arithmetic processing, if it is determined that the desired data does not exist at this cache address, an appropriate amount of data including the required data is transferred to the cache memory. In this way, the arithmetic device can always access the small-capacity cache memory and perform high-speed arithmetic operations.

When such a method is adopted, it is necessary to perform address conversion from a logical address to a cache address when executing a job.

In this case, in addition to the mapping table between logical addresses and physical addresses created before the start of the job, a mapping table between physical addresses and cache addresses is created, and the addresses are arranged in the order of logical address → physical address → cache address. The conversion is performed to access the desired data.

FIG. 11 is a block diagram showing such a conventional address conversion procedure.

The arithmetic unit 21 inputs the logical address 22 to the logical/physical mapping table address conversion circuit 23, and converts the logical address 22 into the physical address 2.
Get 4. The physical address 24 thus obtained is then input to a Cassini mapping table address conversion circuit 25, and a cache address 26 is obtained.

[Problem that the invention seeks to solve]

However, in this conventional method, address conversion is performed in two steps.
Since the process is performed in stages, the access time becomes long, which is a serious factor that hinders speeding up the processing.

On the other hand, it is conceivable to create a mapping table that directly associates logical addresses with cashier addresses.

However, this mapping table is relatively large.

Moreover, if a plurality of jobs are being executed in parallel, creating this table for each job would require a large amount of memory to store these tables, making it impractical.

The present invention has been made with attention to the above points, and an object of the present invention is to provide an address conversion method that reduces the capacity of a mapping table for address conversion between the logical address and the cashier address. .

[Means for solving problems]

The address translation method of the present invention includes a storage device that stores data in a location specified by a physical address, and a cache memory that transfers a part of the data in this storage device to a location specified by a cache address, When the above data is read from this cache memory and multiple jobs are executed in parallel, the correspondence relationship between the logical address attached to each step of each job and the above cache address is shown for each above job. Create a mapping table on one logical address space,
This method is characterized in that the same logical address is associated with each of the data on the physical address that is commonly used among the jobs.

[Operation] In this way, by associating the same logical address with the data on the physical address shared between each job, and creating these multiple mapping tables on one logical address space, the mapping It is possible to prevent duplication of portions of the table that are commonly used by each job.

That is, if a mapping table is created separately for each job, a unique logical address will be assigned to each piece of data at the same physical address. Therefore, separate mapping tables for associating logical addresses and cache addresses are required. The capacity of the main memory device is approximately constant, and a portion of it may be shared by multiple jobs.If this duplication is prevented, the capacity of the mapping table can be significantly reduced.

〔Example〕

FIG. 1 is a basic conceptual diagram of the address translation method of the present invention.

In the present invention, the arithmetic unit 11 manually inputs the logical address 12 to the cache mapping table address conversion circuit 13 to obtain the cache address 14 directly.

2 to 4 are conceptual diagrams showing the configuration of three types of jobs A, B, and C that are executed in parallel.

Figure 2 shows that job A is CAL, CA2, UAI, UA.
This figure shows that the data area is composed of six pages worth of data areas: 2, UA3, and UA4. As mentioned above, data includes programs and the like.

Further, it is assumed that the area for one page corresponds to, for example, 100 bytes of data. For example, in the CAL area, logical addresses correspond to data from LAO to LA99.

It is well known that such pagination allows data to be accessed in page units, facilitating high-speed access.

FIG. 3 shows that job B consists of an area of CAI, CA2, and nine pages from UBI to UB7.

Similarly, in FIG. 4, job C is CAL, CA2 and U.
It shows that it is composed of an area of 8 pages from CI to UC6.

Here, CAL and CA2 are each job ASB.

The data area is commonly used by C, and the other data is used uniquely for each job.

Note that the logical address includes an address for identifying each job and an address (L) attached to the data area within each job.
AO, LAloo, etc.) are synthesized. For each job, "00" for job A and 01 for job
A job address of ``10'' was attached to job C.

FIG. 5 shows a conceptual diagram of a mapping table that corresponds to a logical address and a cache address at a certain point in time when these jobs are being executed.

This mapping table is created for three jobs ASB and C, and these are created in the same logical address space. Each job uses this mapping table to perform address conversion between its respective logical address and cache address.

At this time, the common areas CAI and CA2 between each job ASBSC have the same job address "
00” is attached, and from other job addresses, CA
The parts corresponding to L and CA2 are excluded.

That is, in this figure, for example, LIB2 of job B obtains a cache address from a logical address with contents of upper bit "01" and lower bit "300". Further, CA2 of job C obtains a cache address from a logical address with contents of upper bit "OO" and lower bit "100".

FIG. 6 is a conceptual diagram showing the state of the cache memory at this time.

This cache memory has cache addresses from RO to R800, but from RO to R19
In the area up to 9, the above CA l.

Data corresponding to CA2 is stored. Below, as each job progresses, UAI, UB3, UA2, tJ
Data in each area of B4, LIC6, and UB5 is stored and rewritten.

FIG. 7 shows a specific example of the configuration of the logical address.

This logical address is, for example, a job address (JI)
71 contains 2 bits, an address (LAP) that specifies areas such as CAL and UAI? 2, and 8 bits to address 73 (referred to as displacement (DISP)) which specifies data for each byte in the thus specified page.

FIG. 8 specifically shows the contents of the mapping table shown in FIG.

This mapping table includes a logical address (CSL) 82, a cache address (C3A) 83, and mask information (C3
M) consists of 81.

The logical address 82 is made up of only the upper 8 bits of those shown in FIG. 7 that specify the page.

In this case, the cache address 83 has a 3-bit configuration.

The mask information 81 is configured such that "10" is added to the logical address of the area common to each job as described above, and "00" is added to the logical address of the unique area for each job.

FIG. 9 is a wiring diagram showing an example of a circuit that performs address conversion using such a mapping table.

This circuit consists of an input register 91 for manually inputting logical addresses to be compared, a table register 92 for manually inputting a mapping table, and a logic circuit 93 for comparing data in both registers.
and an output register 94 that outputs the corresponding cache address.

This logic circuit 93 includes an exclusive or gate group 931 that checks whether the logical address part 82 of the table register 92 matches the logical address of the manual register 91.
and cache address portion 8 of table register 92
3 to the output register 94;
An AND gate 933 is provided to open the gate group 932 when the above-mentioned two-wheel drive addresses match.

Further, a masking gate group 934 is provided that blocks the comparison result of the upper bits of the logic/address inputted to the AND gate 933 according to the contents of the masking information 81.

In this circuit, it is assumed that the logical address to be checked in the input register 91 is inputted as, for example, "00000001" as shown in the figure. This register 91 holds this logical address until the mapping table reference is completed.

On the other hand, logical address data of the mapping table is sequentially input to the table register 92 at a predetermined period, and verification is performed each time.

Exclusive OR gate group 931 corresponds to logical address 8 of input register 91 and table register 92, respectively.
2 are compared bit by bit, and only when all bits match, the AND gate 933 outputs a signal to open the gate 932.

Here, the logical address "00000001" means that job A has issued a request to access area CA2.

This area CA2 is common to each job, and as shown in FIG. 8, matching information is stored second from the top of the mapping table. Further, the mask information is 10''.

The circuit shown in FIG. 9 simply checks all bits of the logical address when the mask information is "00", but when the mask information is "10", the upper two bits of the logical address, that is, job address (Figure 7) and mask this 2
The bit is ignored and the verification is performed. As a result, the cache address "o ot" is obtained.

That is, the mask gate group 934 prevents the verification result of the upper two bits of the logical address from being output to the AND gate 933.

As a result, for example, even if the logical address is related to the job name "01000001", the same cache address "001" as before is obtained by the matching information second from the top in FIG.

Furthermore, as shown in FIG. 10, for example, the logical address "
10000111" is input, this accesses the unique area tJc6 of job C, and the matching information exists in the sixth position from the top in FIG. 8. In this case, the mask information is "00". Therefore, all bits of the logical address are verified to obtain the cache address "110".

As described above, according to the address conversion method of the present invention, duplication of mapping tables can be prevented and addresses can be directly converted from logical addresses to cache addresses using a relatively small-capacity mapping table.

[Modified example]

The address translation method of the present invention is not limited to the above embodiments.

The configuration of the mapping table, the number of bits used, the number of jobs, etc.
You may select it arbitrarily.

Further, the common logical address does not necessarily need to be set at the beginning of each job. In addition, it does not matter if some or all of the parts are shared.

〔Effect of the invention〕

The address conversion method of the present invention described above provides mapping tables for a plurality of jobs on one logical address space,
By making some or all of these parts common, the capacity of the mapping table is reduced, making it practical to use a mapping table that directly obtains a cache address from a logical address.

It goes without saying that this makes it possible to speed up arithmetic processing.

[Brief explanation of drawings]

Figure 1 is a basic conceptual diagram explaining an embodiment of the address conversion method of the present invention, Figures 2 to 4 are conceptual diagrams showing the contents of each job, and Figure 5 is an address conversion method of the present invention. FIG. 6 is a conceptual diagram showing an example of the contents of the cache memory; FIG. 7 is a diagram showing an example of the logical addresses; FIG. The figure is a block diagram specifically showing a part of the mapping table in Figure 5, Figure 9 is a connection diagram of an address conversion circuit suitable for implementing the present invention, and Figure 11) shows another operation of the circuit. FIG. 11 is a conceptual diagram showing a conventional address conversion method. 12...Logical address, 13...Mapping table, 14...Cache memory. Applicant: NEC Corporation Representative

Claims (1)

[Claims] A storage device that stores data in a location specified by a physical address and a cache memory that transfers a part of the data in this storage device to a location specified by a cache address are provided, and the data is read from the cache memory. When multiple jobs are executed in parallel, a mapping table indicating the correspondence between the logical addresses assigned to each step of each job and the cache address is stored in one logical address for each job. An address conversion method characterized in that data on the physical address created in space and used in common between jobs is associated with the same logical address.