JPH035620B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the control of an address translation device in an information processing device, and in particular converts a real address on a virtual machine or a virtual address into a main memory address on a real machine. The present invention relates to an address translation device for converting an address into an address.

(Prior Art) As shown in FIG. 1, a conventional address translation device of this type has an effective address register 1 for holding an effective address output from an address generation circuit (not shown) and a register 1 for holding a virtual address. Address translation buffer 2 for performing address translation
, a match detection circuit 3, and an address conversion control section 4
and a real address conversion circuit 5 for converting a real address into an address on the main memory, that is, a physical address, and for switching and selecting the output of the real address conversion circuit 4 or the output of the address conversion buffer 2. The selection circuit 6 is comprised of a selection circuit 6. The real address conversion circuit 5 performs a conversion called prefix conversion, which converts a part of the real address area into a part of the address area on the main memory, using information provided in each processor. When conversion is required between a physical address on the computer and a physical address in real memory, conversion is performed according to that method. Conversion from a real address to a physical address is executed by the real address conversion circuit 5 as described above. On the other hand, translation from a virtual address to a physical address is performed by the address translation control unit 4. In this case, in order to achieve high speed, the conversion result and information necessary for the conversion process are registered in address conversion buffer 2, and if information corresponding to the virtual address to be converted exists in address conversion buffer 2, Then, the address translation buffer 2 performs translation into a physical address. In this way, according to the conventional technology, conversion from a real address to a physical address can be performed by a simple procedure, so even if a conversion circuit from a real address to a physical address is prepared independently, the amount of hardware required is reduced. There were few. However, when the conversion procedure becomes complicated, such as address conversion on a virtual machine, there is a drawback that the amount of hardware and the burden on the control method increase.

(Object of the Invention) An object of the present invention is to provide an address translation buffer for both addresses when converting a real address to a physical address or a virtual address to a physical address. It is an object of the present invention to provide an address translation device configured to eliminate the above drawbacks and to easily control address translation on a virtual machine with a simple hardware configuration.

(Structure of the Invention) The address translation device according to the present invention includes an effective address register, an address translation buffer, a coincidence detection circuit, and an address translation control section, and is configured by improving the above.

The effective address register is used to store an effective address, and the address conversion buffer is formed by pairing a part of the effective address with a physical address in order to convert the effective address given to the address register into a physical address. A conversion pair is used as an entry, and a plurality of these entries are stored. The coincidence detection circuit is for detecting a mismatch between the contents of the effective address register and the contents of the address translation buffer. The address conversion control unit is for converting virtual addresses to physical addresses.

In the present invention, a first display bit is provided inside the entry to indicate whether the translated address is a virtual address or a real address corresponding to a translation pair of the address translation buffer, and the effective address A second indicator bit is formed to indicate whether the translated address applied to the register is a virtual address or a real address. Therefore, a comparator circuit is provided to detect coincidence between the first and second display bits. When a real address is given to the effective address register and the corresponding entry does not exist inside the address translation buffer, a predetermined address translation operation is performed and the above translation pair is performed using the real address instead of the virtual address. The entry is registered in the address translation buffer such that the first display bit and the first display bit indicate the real address. When a real address is given to the effective address register, a corresponding translation pair exists inside the address translation buffer, and a match is detected by the comparator circuit, the physical address inside the translation pair is obtained as the translation address. It is composed of

(Example) Next, the present invention will be described in detail with reference to the drawings.

In FIG. 2 showing an embodiment of the present invention, an address translation device according to the present invention includes an effective address register 1 for holding a real address or a virtual address, a translation pair of a virtual address and a physical address, or a real address. The address translation buffer 2 includes a plurality of entries, a match detection circuit 3, and an address translation control unit 4. There is. Address translation buffer 2 stores a plurality of entries in the format shown in FIG. Each entry is a virtual address or
a translated address section 2-a corresponding to the connection 13 of the effective address register 1 that holds the real address;
Connections 13 and 12 of the effective address register 1 with the physical address determined by the address conversion control unit 4.
The contents of the translated address 2-b corresponding to the address 2-b and the translated address section 2-a are composed of display bits 2-c indicating whether the address is a virtual address or a real address. When a real address or a virtual address is set in the effective address register 1, one of the entries of the address translation buffer 2 is read out from part of the information, and part of the entry is connected to the coincidence detection circuit 3. , is compared with some information in the effective address register. At the same time, the display bit inside the entry is also read, and this information is used to determine whether the address inside the effective address register 1 sent from the address translation control section 4 is a real address or not.
Alternatively, it is compared with information indicating whether it is a virtual address. If both match, the internal physical address of the entry is obtained as the main memory address. If at least one of the above does not match, the NFP signal is reported to the address conversion control unit 4, and the address conversion control unit 4 converts the real address or virtual address into a physical address according to a predetermined procedure. will be held.

Although FIG. 2 shows the case where there is only one address translation buffer 2, if multiple address translation buffers are installed, each address translation buffer is provided with a matching detection circuit corresponding to the address translation buffer. The physical address outputs from the buffers are collected in a selection circuit and can be switched by the output of each coincidence detection circuit. Further, the NFP signal reported to the address conversion control unit 4 is the logical product of the NFP signals output from the respective coincidence detection circuits.

Next, the address translation control section 4 will be explained in detail with reference to FIG. In Figure 3, 10
0, 110, 120, 610, and 700 are the first to fifth registers, 130 is a reference signal generation circuit, 200 is a buffer, 300 is an adder circuit, and 4
00,410,420,430,440,620
are first to sixth selection circuits, 450 is a comparator circuit,
500 is an alignment circuit, 510 is a shift circuit, 600
630 is an address conversion control memory, and 630 is a step circuit. Lines 14 and 34 are each connected to like-numbered lines in FIG.

When the NFP signal is sent from the match detection circuit 3 of FIG. 2, a valid display bit for the address translation control memory 600 is set in the fifth register 700 for holding address translation control information. When this valid display bit is set,
In the address translation control section 4, address translation is executed by the address translation microprogram held inside the address translation control memory 600. Also, the fifth register 70 is activated by the NFP signal.
Address translation control memory 600 according to the output of a plurality of bits to represent the type of address translation in 0 and the type of request to the address translation device.
The start address of the address conversion microprogram is generated by the sixth selection circuit 620, which is used to generate an address for the address conversion microprogram. Therefore, this start address is stored in the address conversion control memory 600.
a fourth register 61 for holding the address of
Set to 0. Thereafter, the address translation control unit 4 is controlled by the output of the address translation control memory 600 until the end of the microprogram.

On the other hand, when the NFP signal is generated, since the value of the valid display bit is 0, control circuits other than address conversion control memory 600 perform control as described below. That is, address information such as a real address or a virtual address in the effective address register 1 is written into a buffer 200 that can be read and written simultaneously and independently. If it is a virtual address along with this,
The first selection circuit 400 extracts from the virtual address the displacement that occurs in entry units from the beginning of the first conversion table on the main memory that is first referenced in the address conversion process, and sends it to the third selection circuit 420. 1 register 100. Further, the first real address information of the first conversion table held in the buffer 200 is read out, and the fourth selection circuit 4
30 to the second register 110. On the other hand, at the time of a real address, the real address in the effective register is selected by the first and third selection circuits 40.
0,420 to the first register 100, and the second register 110 to 0. The register 120 is a work register for the address translation control memory 600, and is a register for the selection circuit 4.
10 switches the input data of the register 120.
The buffer 200 is equipped with the latest information and work areas necessary for address conversion, such as the real address information at the head of the first conversion table and the address information subject to prefix conversion. Information necessary for the above address conversion is written and read out. The reference signal generation circuit 130 stores a value indicating the area to be converted for prefix conversion and a value specifying the area for the conversion result, and the comparison circuit 450 is connected to the value specifying the area to be converted. The latter conversion area designation value is connected to the selection circuit 440. Thereafter, the processing is continued under the control as described below based on the output of the address translation control memory 600. The contents of the first register 100 and the second register 110 are stored in the adder circuit 30.
0 is added, and the addition result is prefix-converted by comparator circuit 450 and fifth selection circuit 440 as necessary. The output of the selection circuit 440 is connected to the address conversion buffer 2 of FIG. 2, serves as an input for the physical address portion of the conversion pair, and is also connected to the main memory as the main memory address (not shown). At the time of a real address, the result of the prefix translation represents a main memory address, that is, a physical address, but at the time of a virtual address, it represents the physical address of an entry of the first translation table within the first translation table. , will issue a read request for the first conversion table entry to the main memory. The read first conversion table entry is returned to the alignment circuit 500 from the main memory. After alignment, address information is extracted by the fourth selection circuit 430 and loaded into the second register 110. When virtual machines with various architectures operate, the value obtained by multiplying the extracted address information by 16 may be the real address information in the virtual machine with a specific architecture. The address information inside the second register 110 is sent to the shift circuit 510, and after the shift is executed, this data is set in the second register 110 again. The first translation table entry is the second entry in main memory that is referenced second by the address translation.
, the displacement inside the second conversion table from the virtual address held in the buffer 200 is stored in the first register 10.
0, reading of the second translation table entry is performed, and processing continues until the entry containing the translated physical address is retrieved. When the physical address is determined as described above, the physical address is registered in the address translation buffer 2 as a translation pair.

In this embodiment, a virtual machine may be operated. A real computer has a virtual computer running flag that can be controlled by software instructions, and the value of the flag determines whether the virtual computer is running.
In address conversion when a virtual machine is operating, if the main memory address on the virtual machine is allocated from address N on the real main memory, the virtual machine may operate differently from the above virtual machine. A description will be given next, focusing on the differences in this case. By prefix converting the output of the adder circuit 300, the main memory address on the virtual machine can be obtained, but in order to generate the real main memory address, it is necessary to further add N. Therefore, the output of the fifth selection circuit 440 is set in the first register 100, and at the same time, the information at the address N on the real main memory is sent to the buffer 200 in correspondence with the physical address 0 on the virtual machine. The physical address is determined by reading from the physical address, setting it in the second register 110, and then performing the addition by the adder circuit 300. When a virtual machine operates, the procedure for converting a real address to a physical address becomes complicated.

(Effects of the Invention) As explained above, the present invention uses an address translation buffer in both the translation from a real address to a physical address and the translation from a virtual address to a physical address. This simplifies the control of address translation in the system, which has the effect of reducing the amount of hardware required.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional address translation device. FIG. 2 is a block diagram showing an embodiment of an address translation device according to the present invention. FIG. 3 is a detailed block diagram of the address translation control section of FIG. 2. FIG. 4 is a diagram showing the format of entries in the address translation buffer. DESCRIPTION OF SYMBOLS 1... Effective address register, 2... Address translation buffer, 3... Match detection circuit, 4... Address translation control unit, 5... Real address translation circuit, 6
...Selection circuit, 100, 110, 120, 61
0,700...Register, 200...Batsuhua,
300... Adder circuit, 400, 410, 42
0,430,440,620...selection circuit, 45
0... Comparator circuit, 500... Alignment circuit, 510
...Shift circuit, 600...Address conversion control memory, 630...Step circuit.

Claims (1)

[Claims] 1. An effective address register for storing an effective address, and for converting the effective address given to the address register into a physical address,
A translation pair formed by pairing a part of the effective address and the physical address is provided as an entry,
an address conversion buffer for storing a plurality of the entries; a coincidence detection circuit for detecting a mismatch between the contents of the effective address register and the contents of the address conversion buffer; and a conversion from the effective address to the physical address. In the address translation device, the address translation device includes an address translation control unit for performing the above-mentioned address translation buffer.
a second display bit indicating whether the address to be translated given to the effective address register is a virtual address or a real address; and a second display bit indicating whether the address to be translated given to the effective address register is a virtual address or a real address; A comparator circuit for detecting a match with the bit is provided inside the address conversion control section,
When a real address is given to the effective address register and the corresponding entry does not exist in the address translation buffer, a predetermined address translation operation is performed and the real address is used instead of the virtual address. The entry is registered in the address translation buffer such that the translation pair and the first display bit indicate a real address, and the corresponding translation pair exists inside the address translation buffer, and the comparator An address translation device characterized in that, when a match is detected by a circuit, a physical address inside the translation pair is obtained as a translation address.